TWI779923B - Pattern verification system and operating method thereof - Google Patents

Abstract

An operating method of a pattern verification system includes: performing commands to a to-be tested device to generate a two-dimensional pattern with a first area and a second area; and sequentially removing the commands and performing tests to the to-be tested device simultaneously, in which when at least one of the commands is removed such that the second area of the two-dimensional pattern is transformed as the first area of the two-dimensional pattern, the at least one of the commands is recovered, and the at least one of the commands is set as at least one key command.

Description

Pattern verification system and method of operation thereof

The present disclosure relates to a pattern verification system and an operation method of the pattern verification system.

Generally speaking, machine operators usually use the two-dimensional pattern test method (shmoo) to test memory products. When the machine operator uses the two-dimensional pattern test method to detect the abnormality of the memory product, the two-dimensional pattern generated by the two-dimensional pattern test method will have a pass area and a failure area. Since the machine operator needs to manually select test points to analyze the failure area of the two-dimensional pattern, the workload of the machine operator is increased, and the overall efficiency of the two-dimensional pattern test method for testing is reduced.

One technical aspect of the present disclosure is a pattern verification system.

According to an embodiment of the present disclosure, a pattern verification system includes a first processor and a second processor. The first processor is configured to execute a plurality of operation instructions on the element to be tested to generate a two-dimensional pattern with a first area and a second area. The second processor is electrically connected to the first processor and configured to sequentially remove the operation instructions and simultaneously test the DUT. When at least one of the operation instructions is removed to cause the second area of the two-dimensional pattern to be converted into the first area, the second processor returns at least one of the operation instructions being removed, and at least one of the returned operation instructions or set as at least one key operation instruction.

In an embodiment of the present disclosure, the above pattern verification system further includes a scanning unit. The scanning unit is electrically connected to the first processor and configured to scan the two-dimensional pattern to locate the center point of the second area of the two-dimensional pattern.

In an embodiment of the present disclosure, the above-mentioned pattern verification system further includes an output unit. The output unit is electrically connected to the second processor and configured to output at least one key operation instruction.

In an embodiment of the present disclosure, the above-mentioned pattern verification system further includes a memory. The memory is electrically connected to the second processor and configured to store at least one key operation instruction.

Another technical aspect of the present disclosure is an operation method of a pattern verification system.

According to an embodiment of the present disclosure, an operating method of a pattern verification system includes: performing a plurality of operating instructions on a device to be tested to generate a two-dimensional pattern having a first region and a second region; and removing the operating instructions sequentially and treating them simultaneously The test element is tested, wherein when at least one of the operation instructions is removed and the second area of the two-dimensional pattern is converted into the first area, at least one of the operation instructions in the removal is replied, and the returned operation instructions are At least one of them is set as at least one key operation instruction.

In an embodiment of the present disclosure, the above method further includes scanning the two-dimensional pattern by using the scanning unit to locate the center point of the second area of the two-dimensional pattern.

In an embodiment of the present disclosure, the above method further includes setting a center point of the second area of the two-dimensional pattern as a test point to obtain a test environment.

In an embodiment of the present disclosure, the test environment includes a test voltage value and a test speed value.

In an embodiment of the present disclosure, the above method further includes using a memory to store at least one key operation instruction.

In an embodiment of the present disclosure, the above method further includes using the output unit to output at least one key operation instruction.

In the above embodiments of the present disclosure, when the removal of the operation command results in the conversion of the second area of the two-dimensional pattern into the first area, the pattern verification system can reply the operation command being removed. In detail, the pattern verification system can remove operation instructions not related to the second region of the two-dimensional pattern, and set operation instructions related to the second region of the two-dimensional pattern as key operation instructions. In this way, the pattern verification system only needs to retain key operation instructions instead of the original number of operation instructions, so the number of reserved instructions of the pattern verification system can be reduced. Since the machine operator can directly obtain the key operation instructions instead of the unanalyzed operation instructions, the time for the machine operator to manually analyze the operation instructions can be saved, so as to improve the test efficiency of the pattern verification system. In addition, the pattern verification system can set the center point of the second area of the two-dimensional pattern as the test point by the scanning unit, thus saving the machine operator from manually setting the test points, thereby improving the test efficiency of the pattern verification system.

The embodiments disclosed below provide many different implementations, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present case. Of course, these examples are only examples and are not intended to be limiting. In addition, the present case may repeat element symbols and/or letters in various instances. This repetition is for the purposes of brevity and clarity and does not in itself dictate a relationship between the various implementations and/or configurations discussed.

Spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein for convenience of description to describe The relationship of one element or feature to another element or feature as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 shows a block diagram of a pattern verification system 100 according to an embodiment of the present disclosure. FIG. 2 shows a schematic diagram of a two-dimensional pattern 200 having a first region 210 and a second region 220 according to an embodiment of the present disclosure. The pattern verification system 100 includes a first processor 110 and a second processor 120 . The first processor 110 is configured to execute a plurality of operation instructions 112 on the device under test 300 to generate a two-dimensional pattern 200 having a first region 210 and a second region 220 . For example, the device under test 300 can be a memory product, such as dynamic random access memory (Dynamic random access memory, DRAM), but not limited thereto. In some embodiments, the pattern verification system 100 can use the two-dimensional pattern test method (Shmoo) to test the device under test 300 , and generate the two-dimensional pattern 200 having the first region 210 and the second region 220 according to the test result. In detail, the first area 210 of the two-dimensional pattern 200 may represent the test result of the DUT 300 as pass, and the second area 220 of the two-dimensional pattern 200 may represent the test result of the DUT 300 as failure.

In addition, the second processor 120 of the pattern verification system 100 is electrically connected to the first processor 110 and configured to sequentially remove the operation instructions 112 and simultaneously test the device under test 300 . When at least one of the operation instructions 112 is removed and the second region 220 of the two-dimensional pattern 200 is converted into the first region 210, the second processor 120 of the pattern verification system 100 replies with at least one of the operation instructions 112 being removed. or, and set at least one of the returned operation instructions 112 as at least one key operation instruction 122 . Specifically, the second processor 120 of the pattern verification system 100 removes each operation command 112 in sequence and then tests the device under test 300 , when the operation command 112 is removed and the second region 220 of the two-dimensional pattern 200 When it remains in the second region 220, it means that the operation instruction 112 being removed has nothing to do with the test result of the second region 220 of the two-dimensional pattern 200, that is, the operation instruction 112 being removed has nothing to do with the failure of the DUT 300 The result is irrelevant, so the operation instruction 112 can be removed.

On the other hand, when the operation instruction 112 is removed and the second region 220 of the two-dimensional pattern 200 is converted into the first region 210, it represents the test between the removed operation instruction 112 and the second region 220 of the two-dimensional pattern 200 The result is related, that is to say, the operation instruction 112 being removed is related to the failure result of the device under test 300, so the second processor 120 of the pattern verification system 100 can reply the operation instruction 112 being removed, and the operation instruction 112 of the reply The instruction 112 is set as a key operation instruction 122 . In this way, the machine operator can obtain key operation instructions 122 through the pattern verification system 100 , and each key operation instruction 122 is related to the failure result of the DUT 300 .

Specifically, the pattern verification system 100 can remove the operation instructions 112 not related to the second region 220 of the two-dimensional pattern 200 , and set the operation instructions 112 related to the second region 220 of the two-dimensional pattern 200 as key operation instructions 122 . In this way, the pattern verification system 100 only needs to retain the key operation instructions 122 instead of the original number of operation instructions 112 , so the number of reserved instructions in the pattern verification system 100 can be reduced. Since the machine operator can directly obtain the key operation instruction 122 instead of the unanalyzed operation instruction 112 , the time for the machine operator to manually analyze the operation instruction 112 can be saved, so as to improve the testing efficiency of the pattern verification system 100 .

In some embodiments, the pattern verification system 100 further includes a scanning unit 130 , an output unit 140 and a memory 150 . The scanning unit 130 of the pattern verification system 100 is electrically connected to the first processor 110 and configured to scan the second area 220 of the two-dimensional pattern 200 to locate the center point 222 of the second area 220 of the two-dimensional pattern 200 . The output unit 140 and the memory 150 of the pattern verification system 100 are electrically connected to the second processor 120 . The output unit 140 is configured to output the key operation instruction 122 , and the memory 150 is configured to store the key operation instruction 122 . The machine operator can obtain the key operation instruction 122 instead of the unanalyzed operation instruction 112 through the pattern verification system 100 , thus saving the time for the machine operator to manually analyze the operation instruction 112 .

In the following description, an operation method of the pattern verification system will be explained. The described component connection relationship and materials will not be repeated, but will be described first.

FIG. 3 is a flow chart illustrating the operation method of the pattern verification system according to an embodiment of the present disclosure. The method of operation of the pattern verification system includes the following steps. Firstly, in step S1, a plurality of operation instructions are performed on the component to be tested to generate a two-dimensional pattern having a first area and a second area. Then in step S2, the operation instructions are removed in sequence and the device under test is tested at the same time, wherein when at least one of the operation instructions is removed to cause the second area of the two-dimensional pattern to be converted into the first area, the shift is reversed. deleting at least one of the operation instructions, and setting at least one of the returned operation instructions as at least one key operation instruction. In the following description, the above-mentioned steps will be described in detail.

FIG. 4 shows a schematic diagram of the operation instruction 112 in FIG. 1 . Referring to FIG. 1 , FIG. 2 and FIG. 4 at the same time, a plurality of operation instructions 112 are performed on the device under test 300 to generate a two-dimensional pattern 200 having a first region 210 and a second region 220 . In detail, a plurality of operation instructions 112 are arranged in order, and the pattern verification system 100 tests the component under test 300 according to the order of the operation instructions 112, and generates a two-dimensional pattern 200 having a first region 210 and a second region 220 according to the test result. . For example, the first area 210 of the two-dimensional pattern 200 may represent the state in which the test result of the DUT 300 is passed, and the second area 220 of the two-dimensional pattern 200 may represent the state in which the test result of the DUT 300 is failed. .

In some embodiments, the operation method of the pattern verification system 100 further includes: using the scanning unit 130 to scan the second area 220 of the two-dimensional pattern 200 to locate the center point 222 of the second area 220 of the two-dimensional pattern 200; The center point 222 of the second area 220 of the three-dimensional pattern 200 is set as a test point 230 to obtain a test environment including a test voltage value and a test speed value. Performing the operation instruction 112 on the DUT 300 through the selected test voltage value and test speed value will keep the test result of the DUT 300 as failure (corresponding to the second region 220 of the two-dimensional pattern 200 ). In addition, the pattern verification system 100 can set the center point 222 of the second area 220 of the two-dimensional pattern 200 as the test point 230 through the scanning unit 130, so the machine operator does not need to manually set the test point 230, which can save the machine operation Personnel manually time the test point 230 .

FIG. 5A to FIG. 5B are schematic diagrams of the removing operation instruction 112 according to an embodiment of the present disclosure. Referring to FIG. 1 , FIG. 2 , FIG. 5A and FIG. 5B at the same time, when the test result of the device under test 300 remains as failure, the next step can be performed. Then, after removing each operation instruction 112 in sequence, the device under test 300 is tested. For example, the operation instructions 112 can be sequentially removed by using the approximation method in FIG. 5A and the group deletion method in FIG. 5B . The approximation method in FIG. 5A can remove the operation instruction 112 by means of up-down approximation to test the device under test 300 . The group deletion method in FIG. 5B can group the operation instructions 112 with similar functions to generate different groups, and remove the grouped operation instructions 112 to test the device under test 300 .

In some embodiments, when the operation instruction 112 is removed and the device under test 300 is tested and the second region 220 of the two-dimensional pattern 200 remains the second region 220, it means that the operation instruction 112 and the two-dimensional pattern are being removed. The test results of the second area 220 of 200 are irrelevant. That is to say, the operation instruction 112 being removed has nothing to do with the failure result of the device under test 300 , so the operation instruction 112 can be removed. When the operation instruction 112 is removed and the device under test 300 is tested and the second area 220 of the two-dimensional pattern 200 is converted into the first area 210, it means that the operation instruction 112 and the second area 220 of the two-dimensional pattern 200 are being removed. related to the test results. That is to say, the operation instruction 112 being removed is related to the failure result of the device under test 300 . The second processor 120 of the pattern verification system 100 can reply the operation instruction 112 being removed, and set the returned operation instruction 112 as the key operation instruction 122 .

FIG. 6 is a schematic diagram of a key operation instruction 122 according to an embodiment of the present disclosure. Referring to FIG. 1 and FIG. 6 at the same time, the operation method of the pattern verification system 100 further includes: using the memory 150 to store the key operation instruction 122 ; and using the output unit 140 to output the key operation instruction 122 . The machine operator can obtain the key operation instruction 122 instead of the unanalyzed operation instruction 112 through the pattern verification system 100, so the time for the machine operator to manually analyze the operation instruction 112 can be saved to improve the testing efficiency of the pattern verification system 100 .

To sum up, when the operation instruction is removed and the second area of the two-dimensional pattern is transformed into the first area, the pattern verification system can reply the operation instruction being removed. In detail, the pattern verification system can remove operation instructions not related to the second region of the two-dimensional pattern, and set operation instructions related to the second region of the two-dimensional pattern as key operation instructions. In this way, the pattern verification system only needs to retain key operation instructions instead of the original number of operation instructions, so the number of reserved instructions of the pattern verification system can be reduced. Since the machine operator can directly obtain the key operation instructions instead of the unanalyzed operation instructions, the time for the machine operator to manually analyze the operation instructions can be saved, so as to improve the test efficiency of the pattern verification system. In addition, the pattern verification system can use the scanning unit to set the center point of the second area of the two-dimensional pattern as the test point, so the machine operator does not need to manually set the test point, which can save the time for the machine operator to manually set the test point .

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. It should be appreciated by those skilled in the art that they may readily use the present disclosure as a basis for designing or modifying other processes and structures, so as to achieve the same purposes and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

100:Pattern Verification System 110: The first processor 112: Operation instruction 120: second processor 122: Key operation instructions 130: scanning unit 140: output unit 150: Memory 200: 2D pattern 210: The first area 220: Second area 222: center point 230: test point 300: component under test S1: step S2: step

One embodiment of the present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a block diagram of a pattern verification system according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram of a two-dimensional pattern having a first region and a second region according to an embodiment of the present disclosure. FIG. 3 is a flow chart illustrating the operation method of the pattern verification system according to an embodiment of the present disclosure. FIG. 4 shows a schematic diagram of the operation command in FIG. 1 . FIG. 5A to FIG. 5B are schematic diagrams of removing operation instructions according to an embodiment of the present disclosure. FIG. 6 is a schematic diagram of key operation instructions according to an embodiment of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

100:Pattern Verification System

110: The first processor

112: Operation instruction

120: second processor

122: Key operation instructions

130: scanning unit

140: output unit

150: memory

300: component under test

Claims (10)

A pattern verification system comprising: A first processor configured to perform a plurality of operation instructions on a device under test to generate a two-dimensional pattern with a first area and a second area; and A second processor, electrically connected to the first processor and configured to sequentially remove the operating instructions and simultaneously test the device under test, wherein when at least one of the operating instructions is removed, the When the second area of the two-dimensional pattern is converted into the first area, the second processor returns the at least one of the operating instructions being removed, and sets the at least one of the returned operating instructions to is at least one key operation instruction. The pattern verification system as described in Claim 1 further includes: A scanning unit is electrically connected to the first processor and configured to scan the two-dimensional pattern to locate a central point of the second area of the two-dimensional pattern. The pattern verification system as described in Claim 1 further includes: An output unit is electrically connected to the second processor and configured to output the at least one key operation instruction. The pattern verification system as described in Claim 1 further includes: A memory electrically connected to the second processor and configured to store the at least one key operation instruction. A method of operating a pattern verification system, comprising: performing a plurality of operation instructions on a DUT to generate a two-dimensional pattern with a first area and a second area; and removing the operating instructions in sequence and testing the device under test at the same time, wherein when at least one of the operating instructions is removed to cause the second area of the two-dimensional pattern to be converted into the first area, reply removing the at least one of the operating instructions in progress, and setting the at least one of the restored operating instructions as at least one key operating instruction. The method as described in claim item 5 further includes: A scanning unit is used to scan the two-dimensional pattern to locate a central point of the second area of the two-dimensional pattern. The method as described in Claim 6, further comprising: The center point of the second area of the two-dimensional pattern is set as a test point to obtain a test environment. The method according to claim 7, wherein the test environment includes a test voltage value and a test speed value. The method as described in claim item 5 further includes: A memory is used to store the at least one key operation instruction. The method as described in claim item 5 further includes: An output unit is used to output the at least one key operation instruction.

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