CN115237036B

CN115237036B - Full-digitalization management device for wafer-level processor system

Info

Publication number: CN115237036B
Application number: CN202211155809.2A
Authority: CN
Inventors: 张坤; 邓庆文; 胡守雷
Original assignee: Zhejiang Lab
Current assignee: Zhejiang Lab
Priority date: 2022-09-22
Filing date: 2022-09-22
Publication date: 2023-01-10
Anticipated expiration: 2042-09-22
Also published as: CN115237036A

Abstract

The invention discloses a full-digital management device for a wafer-level processor system, which realizes the refined control of main functional units of the wafer processor system by using a programmable logic device, provides an independent main controller and a physical channel for each unit by utilizing the advantages of multi-pin and parallel processing of the programmable logic device, realizes high-efficiency and high-real-time management and fault isolation, and realizes the normalization of the addresses of all slave machines of managed functional units with bus protocols. In topology, a plurality of programmable logic devices form a structure with a master and a plurality of slaves, and the master is connected with the slaves through a full-duplex high-speed interface, so that the expansion of management IO pins is realized. The master control unit and the slave expansion unit are arranged on different layers of a power supply system, so that the space of a power supply board of the wafer processor is effectively utilized, and the management device consisting of the programmable logic devices does not influence the whole size, power supply density and power distribution loss of the system.

Description

Full-digitalization management device for wafer-level processor system

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a full-digital management device for a wafer-level processor system.

Background

With the increasing demands of the fields of deep learning, large-scale data exchange and the like on the computing power of the processor, a single processor cannot meet all scenes for large-scale data processing. Thus, wafer-level processors have been proposed with the advantages of extremely high interconnect bandwidth and power density, and a very large processor cluster is realized by integrating a large number of homogeneous or heterogeneous processors Die on a wafer or similar high-speed medium, and interconnecting the Die with each other via a high-speed bus.

The wafer processor system includes a plurality of processors Die and necessary configuration debugging circuits, voltage conversion circuits, clock circuits, reset circuits, etc. In addition, the power supply of the processor Die requires the voltage conversion circuit of multiple voltage domains and the power-on sequence control circuit to cooperate to satisfy the power-on sequence and time delay required by the processor Die. In order to control the junction temperature of the processor Die within a certain range, heat is generally taken out of the wafer processor system by using heat dissipation methods such as air cooling or liquid cooling, and a fan of the air cooling system and a water pump of the liquid cooling system need to control and manage the processor Die in real time according to the temperature of the processor Die. These circuits need to interact with the outside world, or control them externally, or feed back status information to the outside world for monitoring and statistics.

The functional modules of the wafer processor system contain a large number of PMBus interfaces and IIC interfaces for configuring parameters and monitoring states, the interfaces are usually connected in the form of buses, a designer or a user needs to allocate a unique slave address to each slave interface device, which increases the workload of design and production, and meanwhile, most of the IIC and PMBus addresses are 7-bit addresses, and when the number of the slaves exceeds 128, the slave addresses will be duplicated.

The wafer processor system is used as an enterprise server level application, and needs to ensure that if one processor Die needs to be reset due to fault run-off, the processor Die can be reset independently without influencing the normal work of other modules.

The wafer processor uses a large-size silicon substrate as a substrate, a large number of processors Die are bonded to the silicon substrate, then a high-density power supply system is used for supplying power to the silicon substrate, for a bottom power supply framework, a large number of TSV holes are required to be etched in the silicon substrate for power supply and signal transmission, meanwhile, the silicon substrate is thinned to about 120um in a chemical mechanical polishing mode, the silicon substrate is very fragile and fragile, and therefore, no matter in test debugging or actual use, direct contact, plugging and the like of the silicon substrate and a high-density power supply board are required to be avoided as much as possible, so that influence of external stress on warping degree of the silicon substrate is avoided, poor contact is caused, and even the silicon substrate is locally broken. In addition, since the bump pitch of the processor Die is small, when the processor Die is bonded to a silicon substrate, a bump short circuit of a part of the processor Die may occur, so that when a bus (such as IIC or SPI) is used for configuration management of a large number of processors Die, if a configuration management pin of one processor Die is short-circuited, the level of the whole bus may be disturbed, and further, the configuration management function of all the processors Die may be broken down, so that a fault isolation needs to be performed on a bus management interface of each processor Die.

In a traditional processing system, because the number of internal functional units is small, the circuit density is low, and an independent control key or an interface is designed for each functional unit to independently control the functional units, for example, the independent key is used for carrying out reset control on a processor, the independent JTAG is used for carrying out processor debugging, the independent UART output processor LOG is used, the CPLD or a gate circuit is used for carrying out power-on time sequence control and the like, the functional units in the wafer processor system have the characteristics of complex structure, large number, high density and the like, and the independent control key and the independent interface are configured for each functional unit, so that a large amount of installation space is occupied, the density of a power supply board is further reduced, and the power supply board is difficult to operate during use. Meanwhile, each functional unit in the wafer processor comprises various interfaces and protocols, the total communication rate is high, and direct interactive communication cannot be realized among the modules, so that a management device for the wafer processor is needed to uniformly manage the wafer processor, and high-speed, high-efficiency and fine management of the wafer processor is conveniently realized.

In order to improve the calculation power to the maximum extent, the distance between the processor Die of the wafer processor and the corresponding power supply circuit is small, and a large number of external high-speed connectors are also distributed around the wafer processor and are responsible for large data volume interaction with the outside, so that the management device of the wafer processor needs not to influence the overall size of the power supply system, the density and power distribution loss of the power supply circuit, the installation space of the external high-speed connectors and the signal quality.

Disclosure of Invention

In order to solve the technical problems, the invention provides a full-digital management device for a wafer-level processor system, which has the advantages of high management efficiency, high concurrent communication, fine-grained management, high real-time performance, simplicity in operation, low power consumption, small size and the like.

The technical scheme adopted by the invention is as follows:

a full-digital management device for a wafer-level processor system comprises a management hub and a plurality of functional units, wherein the management hub adopts an independent controller and a channel to uniformly manage the functional units, the management hub is composed of a plurality of programmable logic devices, one of the programmable logic devices is used as a main control unit, the other programmable logic devices are used as slave IO extension units, the main control unit manages the behavior of the slave IO extension units, the slave IO extension units are responsible for the management of the quadrants of the distributed wafer processor, the functional units are linked through the programmable logic devices, receive the command of the management hub and perform corresponding operation, the management hub communicates with an upper computer through a gigabit Ethernet, and manages configuration information and state information of each functional unit in an interactive mode.

Preferably, the programmable logic device is a CPLD or an FPGA.

Preferably, the functional unit includes a processor Die, a voltage conversion module, a clock, a reset, a power-on sequence, and a heat sink, which are connected to each other.

Preferably, the slave addresses of all the bus-type functional units in the functional units are unified default addresses.

Preferably, the management hub is composed of five programmable logic devices and comprises a main control unit and four slave IO extension units, the main control unit is connected with each slave IO extension unit through an independent channel, and each channel uses four common IO pins to perform full-duplex high-speed communication through a custom protocol.

Preferably, the main control unit includes a gigabit ethernet controller, a TCP/IP protocol stack, a destination parsing module, a data distribution and summary module, and a controller module of a custom protocol, which are connected to each other.

Preferably, the slave IO extension unit includes a custom interface controller, a data distribution and aggregation module, a data parsing and encapsulation module, and a communication protocol controller for each managed unit, which are connected to each other.

Preferably, in terms of physical structure, the master control unit and the slave IO extension units are located on two different PCB carrier boards of a power supply system, the master control unit is located on a lowest carrier board far away from the processor Die, the slave IO extension units are located on a middle power supply carrier board close to the processor Die, four slave IO extension units are installed at four corners of the power supply carrier board, and each slave IO extension unit is responsible for management of a functional circuit in 1/4 wafer processor.

The invention has the advantages that a plurality of programmable logic devices form a two-layer structure to form a full digital management device of the wafer processor system, an upper computer is used for connecting the management device through the Ethernet, a non-contact and visual management mode is provided for the wafer processor system, and an independent management interface is distributed for each processor Die in comparison, so that the installation space of a system management circuit is greatly saved, and the adverse effect on the warping degree of the system in the process of debugging and using the wafer processor system by direct contact is solved. By combining and arranging the installation positions of the plurality of programmable logic devices, the installation space of the wafer processor system is effectively utilized on the premise of not changing all functions, the whole size, the power supply density and the power distribution loss of the wafer processor. By distributing independent interfaces and controllers for each managed functional unit in the wafer processor system, full-parallel independent management channels are realized, the communication speed and the management efficiency are improved, the slave address normalization of the bus functional unit is realized, the problem that the whole bus is influenced by the short circuit of a certain management bus in the bonding process of the wafer processor Die and the silicon substrate is solved, and fault isolation is realized. Therefore, the invention can provide a convenient, efficient and refined management mode for the wafer processor system and an integrated solution for the management of the wafer processor system.

Drawings

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is a block diagram of a programmable logic device connection;

FIG. 3 is a functional block diagram of a main control unit of the programmable logic device;

FIG. 4 is a functional block diagram of a slave IO expansion unit of the programmable logic device;

FIG. 5 is a schematic view of the IO expansion unit installation location;

fig. 6 shows connection signals between the master control unit and the slave IO extension unit.

Reference numeral 5

The system comprises a power supply board 1, a high-density power supply board 2, a connecting channel 3, a slave IO expansion unit 4, a fixing screw 5, an external high-speed communication connector 6-12 inches, a silicon substrate 7, a deployment area of a processor Die, a horizontal line 8-quadrant division and a vertical line 9-quadrant division.

Detailed Description

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention relates to a full-digital management device for a wafer-level processor system, which is suitable for a top power supply framework and a bottom power supply framework, and as shown in figure 1, the full-digital management device comprises a management hub and a plurality of functional units, wherein the management hub adopts an independent controller and a channel to uniformly manage the functional units, the management hub consists of a plurality of programmable logic devices, the functional units are linked through the programmable logic devices and communicate with an upper computer through a gigabit Ethernet, configuration information and state information of each functional unit are interactively managed, the functional units comprise a processor Die, a voltage conversion module, a clock, a reset, a power-on time sequence and a heat dissipation device, and slave addresses of all bus type functional units are uniform default addresses.

The management hub is composed of five programmable logic devices, as shown in fig. 2, the management hub comprises a master control unit and four slave IO extension units, the master control unit and the four slave IO extension units are located in a two-layer power supply system composed of a master control board and a high-density power supply board, the master control unit is connected with an upper computer through an Ethernet interface, the slave IO extension units are connected with a controlled function unit through metal wires in a power supply PCB (printed circuit board) carrier board or a silicon substrate, the master control unit and the slave IO extension units are connected through a small number of IO interfaces by using common connectors, and a user-defined full-duplex communication protocol is used for interaction. The master control unit is connected with each slave IO expansion unit through an independent channel, the wafer processor is logically divided into four quadrants, and each slave IO expansion unit is responsible for managing the functional unit of the quadrant.

The master control unit is located in the master control board and is a CPLD or an FPGA, and as shown in fig. 3, the master control unit is connected with the upper computer through an ethernet interface, connected with the four slave IO extension units through custom interfaces, and connected with the heat dissipation system controller through a common serial interface. The main control unit mainly comprises an Ethernet controller, a TCP/IP protocol stack, a purpose analysis module, a data distribution/collection module, a controller module with a plurality of self-defined protocols, a PID algorithm and a heat dissipation system controller which are connected with each other. The Ethernet controller and the TCP/IP protocol stack are mainly responsible for communicating with an upper computer, receiving instructions sent by the upper computer, uploading states fed back from all managed functional units, when receiving data, the TCP/IP protocol stack unpacks received messages and sends the unpacked messages to the data analysis module, the data analysis module analyzes destination addresses in the data analysis module, then the data are distributed to custom interface controllers of corresponding quadrants, and the custom interface controllers send the data to corresponding slave IO extension units by using custom protocols. In addition, the temperature information fed back by the voltage conversion module and the processor Die from the custom interface controller is reported to the upper computer through the Ethernet interface, and the PID algorithm is used for adjusting the rotating speed of a radiating fan or the rotating speed of a water pump of a liquid cooling system through the radiating system controller, so that the wind speed of the air-cooled radiating device or the water cooling liquid flow speed of the liquid cooling radiating device can be flexibly controlled.

The slave IO extension unit is located in the high-density power supply board, is a CPLD or an FPGA, and as shown in fig. 4, includes a custom interface controller, a data distribution and summary module, a data parsing and packaging module, a communication protocol controller (such as IIC, PMBus, SPI, UART, general IO, and the like) connected to each other, and is responsible for undertaking the IO interface extension of the master control unit and managing the functional units of the corresponding quadrants, where the functional units include a processor Die, a voltage conversion module, a clock, a reset, a power-on timing sequence, and a heat dissipation device, where the heat dissipation device includes an air-cooled heat dissipation device and a liquid-cooled heat dissipation device.

And for a clock circuit and a reset circuit of each processor Die, directly using an IO interface of a CPLD or an FPGA for control, wherein each clock circuit and each reset circuit correspond to a single IO interface. For the clock circuit, the switch tube is connected in series to the power supply pin of the crystal oscillator, and when the corresponding processor Die fails or does not bear any processing task, the base electrode or grid electrode voltage of the switch tube is controlled, the power supply channel of the corresponding clock circuit is closed, and electric energy is saved. For the reset circuit, the controller is responsible for delaying for a period of time after monitoring that the power-on is completed and the clock is stable, then the reset is released, the wafer processor system is in operation, if one processor Die is abnormal, the system temporarily distributes the task of the processor Die to other processors Die, then the main controller independently resets the processor Die through the corresponding IO without influencing the normal operation of other processors Die, and after the abnormal processor Die is reset to normally operate, the system redistributes the task to the processor Die for operation.

For the configuration debugging circuit of each processor Die, interfaces such as JTAG, IIC, SPI, UART and the like are generally used, and the corresponding main controller is connected with the configuration debugging interface of each processor Die through an independent channel, so that parallel communication is realized, and the speed of concurrent communication is improved. For the IIC slave addresses of the processors Die, since the configuration management channels of the processors Die are independent from each other, there is no need to additionally set slave addresses different from each other, and a uniform default address is adopted. Because the bump of the high-performance processor Die is dense, and the level of the configuration management signal line is abnormal due to solder overflow of the bump when the processor Die is bonded with a silicon substrate, the invention adopts an independent controller and a channel to manage the processor Die, thereby avoiding the condition that the level of the whole bus is influenced when an individual processor Die fails, so that other processors Die cannot be accessed by a system management device.

The management of the voltage conversion module mainly comprises monitoring the states of the voltage, the current, the temperature and the like of the voltage conversion module, modifying parameters such as a soft start mode, a switching frequency, an output voltage and the like, and controlling a power-on sequence, delay time and the like. For each voltage conversion module, a PMBus protocol is used for carrying out state monitoring and parameter configuration on the voltage conversion module through an independent channel, for a plurality of voltage domains of each processor Die, a timer is realized in a corresponding slave IO extension unit, and power-on time sequence control is carried out on the plurality of voltage conversion modules by matching with corresponding time sequence logic. The same as the processor Die, each function of the voltage conversion module adopts an independent channel for parallel management, so that the communication speed and the management efficiency are improved, and the normalization of the PMBus address and the fault isolation among the functions are realized.

The target analysis logic and data distribution and summary module is responsible for extracting data output by the controller module of the user-defined protocol, wherein the data comprise a target address, a target configuration item and effective data. The internal memory area stores a mapping table of destination configuration item and destination register address. After receiving the configuration message, the custom interface controller firstly searches a mapping table, changes a target configuration item into a corresponding register address, then sends the target register address and valid data to a main controller of a functional module corresponding to the target address according to the target address, and directly configures the target address into a Die processor or a power supply default slave address for the main controller needing to configure the target address, such as IIC or PMBus. And the second part is responsible for receiving the state data fed back by the managed functional unit, summarizing the state data into a uniform format, uploading the state data to a main control unit in the main control panel through the user-defined interface controller, and further uploading the state data to an upper computer through the Ethernet.

The communication interface between the master controller and the slave IO extension unit is a full-duplex interface, and comprises an independent sending channel and an independent receiving channel, each channel only comprises a clock line and a data line, the data lines are responsible for serial transmission of configuration information and state information, the configuration information mainly comprises a destination device address, a destination configuration item, data, a check field, a response field and the like, and the state information mainly comprises a source address, a state identifier, state data, a corresponding check field, a corresponding response field and the like. In addition, in addition to a clock line and a data line responsible for transmitting and receiving data, a reset signal line and a JTAG signal line for debugging configuration are connected between the master controller and each slave IO extension unit, and the programmable logic device as the master control unit manages each slave IO extension unit connected through the reset and JTAG signal lines.

The installation positions of the slave IO extension units are, as shown in fig. 5, installed at four corners of the high-density power supply board, two dotted lines in the horizontal and vertical directions in the drawing divide the wafer processor into four quadrants, and each IO extension unit is responsible for the management of each functional unit in the corresponding quadrant, so that the transmission distance of a management signal line is shortened, the area of a single chip management device in the digital management device of the wafer processor is reduced, the remaining space of the power supply system is effectively utilized, the number of IO pins required by the master control unit and each IO extension unit is further simplified, the model selection difficulty of the IO extension function programmable logic device is further reduced, a multi-pin management device can be formed by combining a plurality of CPLDs or FPGAs with lower resource quantity, and the digital management of a plurality of functional units in the wafer processor system is realized.

Example 1

The system structure schematic diagram of the wafer processor is shown in fig. 1, and is a bottom power supply structure, that is, the wafer processor is composed of a large number of processors Die and a complete silicon substrate in a bonding mode, a liquid cooling radiator is installed at the top of the processors Die, TSVs are used as power supply channels in the silicon substrate, a high-density power supply board is butted at the bottom of the silicon substrate to provide electric energy and necessary matching interfaces for the silicon substrate, and the whole system mainly comprises the processors Die, the silicon substrate, the high-density power supply board, a main control board, the liquid cooling radiator and corresponding heat dissipation circulating devices. The main control unit and the IO extension unit which are realized by the programmable logic unit are respectively arranged on the main control board and the high-density power supply board.

Fig. 5 is a top perspective view of the high-density power supply board, the high-density power supply board 1 is fixed by fixing screws, the main control unit is located on the high-density power supply board 1, the surface layer of the high-density power supply board 1 is a 12-inch silicon substrate 6, an arrangement region 7 of the processors Die is arranged in the center of the 12-inch silicon substrate 6, the processors Die are arranged according to the layout of the arrangement region 7 of the processors Die and are bonded on the 12-inch silicon substrate 6, a total number of 308 processors Die with 10G ethernet switching functions are included in the whole wafer processor, the size of the processing Die is 12 × 12mm, an IIC is used as a configuration management interface, and the distance between the two processors Die is 100um. The size of high density power supply board 1 is 400 × 400mm, it is unanimous with the size of radiator, mainly bear voltage conversion circuit, clock circuit, high-speed communication connector, IO extension unit, wherein voltage conversion circuit installs the position that corresponds perpendicularly with treater Die, be equipped with external high-speed communication connector 5 on the silicon substrate 6, set up from IO extension unit 3 on four angles of high density power supply board 1, it is connected with the main control unit of high density power supply board 1 bottom through connect channel 2 from IO extension unit 3, horizontal line 8 is cut apart to the quadrant and vertical line 9 is cut apart to the quadrant divides wafer processor into 4 quadrants, every is responsible for the management of all functional units in one of them quadrant from IO extension unit 3.

The main control board is positioned at the bottommost layer of the system, and the type of the FPGA of Zynq-7000 series of Xilinx company is Z-7010, and the FPGA is used as a main control unit of the wafer processor management device. The size of the power supply is 13 × 13mm, resources such as a dual-core ARM Cortex-A9 processor, two gigabit Ethernet controllers and a 28K FPGA logic unit are arranged inside the power supply, the ARM processor carries a Linux operating system, a TCP/IP protocol stack is arranged inside the power supply, a gigabit Ethernet interface is connected with an upper computer through a universal network cable, and a custom interface is connected with an upper-layer high-density power supply board. The main control unit internally comprises a PID algorithm and uses an RS232 interface to control the heat dissipation circulating device.

When the wafer processor system works, the main control unit receives a command message issued by an upper computer through an Ethernet interface, transmits the message to a TCP/IP protocol stack to analyze effective data, wherein the effective data comprises an address code, a function code and configuration data corresponding to a controlled unit (a processor Die, a voltage conversion module, a clock, reset, a power-on time sequence and a heat dissipation device). Meanwhile, the main control unit receives the state information uploaded from the IO expansion unit in real time, wherein the state information comprises voltage, current and temperature information fed back by a power supply through PMBus and state information fed back by the processor Die through IIC. The main control unit stores the received data into a storage in the FPGA, sets a corresponding completion flag to be 1, sets priorities for all received state data in the main control unit, reads out the corresponding data when detecting that interruption indicates that the data completion flag is set to be 1, encapsulates the data into a network data packet, sends the network data packet to an upper computer through an Ethernet interface, sets a data completion flag to be 0, and sequentially reads and uploads the data from high to low according to the priorities when a plurality of completion flag positions are set to be 1 simultaneously.

In addition, as shown in fig. 6, the main control unit implemented based on the FPGA is responsible for controlling and managing the slave IO extension unit in addition to completing the above function management, and is connected to the global reset input of the slave IO extension unit by using the output IO pin to control the slave IO extension unit, and the main control unit and the four slave IO extension units are connected in series by using the daisy chain structure, so that access and debugging can be performed on the FPGA device on the daisy chain only by using one JTAG interface on the main control board.

The slave IO expansion unit is composed of four FPGAs, the wafer processor is logically and averagely divided into four quadrants, and each IO expansion unit is responsible for management of all functional units in the quadrant. Because the number of the processors Die is 308 in the embodiment, each IO extension unit is responsible for 77 processor dies and function management of related power supplies, clocks and resets, an IIC configuration interface of each processor Die needs two signal lines, a reset function needs one signal line, a PMBus interface corresponding to a power supply needs two signal lines, a power-on timing control function needs two signal lines, a function management pin of each quadrant needs 539, 10 communication pins connected with the FPGA as a main control unit are added, each IO extension device needs 549 single-ended IO pins in common, in the embodiment, an FPGA of Spartan-6 series of Xilinx corporation is selected, the type of the FPGA is XC6SLX150, IO extension of the management device is completed by matching with a peripheral clock and Flash, the XC6SLX150 comprises 576 single-ended IO pins, and the size is 31 × 31mm, and requirements of the embodiment on the size of each IO extension device and the number of IO pins are met.

Because the IIC and the PMBus adopt independent channel management, the IIC slave address of the processor Die and the PMBus slave address of the power module are set to be the unified default address. When the wafer processor works, taking the management of the power module as an example, the downlink configuration data (such as parameters of output voltage, working frequency, OVT/OCT/OTP threshold, soft start mode, and the like) received from the custom interface includes a destination address, a function code, configuration data, and a CRC check field. The data distribution module firstly calculates effective data by using a CRC algorithm to obtain a CRC value, then compares the effective data with check field data to determine whether the effective data is consistent or not, if the effective data is inconsistent, feeds back an error identifier for response and returns to a receiving state to wait for receiving the next data, if the effective data is correct, feeds back a correct identifier for response, then continues to analyze a destination address and a function code of the data distribution module, distributes the function code and configuration data to a PMBus main controller of a corresponding channel according to the destination address, the PMBus main controller is configured with a uniform slave address, and when the data input is detected, a function code lookup table is converted into a register address corresponding to a managed function unit, and then the register address and the configuration data are packaged into a PMBus protocol and sent to a power module. When the upper computer reads the monitoring information of the power module, the PMBus main controller feeds back the received data to the storage area of the data distribution and collection module and finishes the feedback to mark the position 1, then a state machine in the data distribution and collection module reads out the data of the storage area marked by the position 1, and the data are uploaded to a main controller board through a user-defined interface and then uploaded to the upper computer. In addition, for a small number of functional units in the wafer processor system, which cannot normally establish communication with the functional units due to process, assembly and the like in the debugging and actual use processes, the upper computer records the functional units according to the fed-back address information for subsequent positioning and maintenance.

The liquid cooling radiator divides into 9 districts with every quadrant, and 36 independent heat dissipation districts are altogether distinguished in 4 quadrants of whole wafer processor, and a liquid cooling radiator is installed in every district, uses 36 water pumps cooperation extrinsic cycle device to carry out independent control respectively to cooling liquid velocity of flow of cooling system again, uses 36 RS232 interfaces to receive the velocity of flow control signal that the master control board transmitted, adjusts the rotational speed of the water pump that corresponds the region.

In summary, the embodiments of the present invention provide a digital management device for a wafer level processor system, which provides an independent management channel for each functional unit (processor Die, voltage conversion module, clock, reset, power-on timing sequence, and heat dissipation device) through a combination of one ZYNQ and four FPGAs, and is uniformly managed by an upper computer through an ethernet, so that the digital management device has the characteristics of convenience, high efficiency, and fine granularity, and can provide an integrated solution for the management of the wafer level processor system.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, as the present invention is not only applicable to the bottom power architecture, but also applicable to the top power architecture, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A fully digital management apparatus for a wafer-level processor system, comprising: the management hub adopts an independent controller and a channel to carry out unified management on the functional units so as to realize parallel communication, the management hub is composed of a plurality of programmable logic devices, one of the programmable logic devices is used as a main control unit, the other programmable logic devices are slave IO extension units, the main control unit manages the behavior of the slave IO extension units, the slave IO extension units are responsible for managing the quadrants of the distributed wafer processor, the functional units are linked through the programmable logic devices, receive the command of the management hub and carry out corresponding operation, the management hub communicates with an upper computer through a gigabit Ethernet, and the management configuration information and the state information of each functional unit are interacted;

the management hub is composed of five programmable logic devices and comprises a main control unit and four slave IO expansion units, the main control unit is connected with each slave IO expansion unit through an independent channel, and each channel uses four common IO pins to perform full-duplex high-speed communication through a custom protocol;

the main control unit comprises a gigabit Ethernet controller, a TCP/IP protocol stack, a target analysis module, a data distribution and collection module, a self-defined protocol controller module, a PID algorithm and a heat dissipation system controller which are connected with each other; the target analysis is responsible for extracting data output by the controller module of the custom protocol, and the data comprises a target address, a target configuration item and effective data; the data distribution and collection module is used for receiving the state data fed back by the managed functional unit, collecting the state data into a uniform format, uploading the state data to the main control unit through the controller module with a custom protocol, and uploading the state data to the upper computer through the Ethernet;

the slave IO expansion unit comprises a custom interface controller, a data distribution and collection module, a data analysis and encapsulation module and a communication protocol controller aiming at each managed unit, which are connected with each other;

in physical structure, the master control unit and the slave IO expansion units are located on two different layers of PCB carrier plates of a power supply system, the master control unit is located on the lowest carrier plate far away from the processor Die, the slave IO expansion units are located on a middle layer power supply carrier plate close to the processor Die, the four slave IO expansion units are installed on four corners of the power supply carrier plate, and each slave IO expansion unit is respectively responsible for the management of functional circuits in 1/4 wafer processors.

2. A fully digital management apparatus for a wafer level processor system, as recited in claim 1, wherein: the programmable logic device is a CPLD or an FPGA.

3. A fully digital management apparatus for a wafer level processor system, as recited in claim 1, wherein: the functional unit comprises a processor Die, a voltage conversion module, a clock, a reset, a power-on time sequence and a heat dissipation device which are connected with each other, and the management hub uses a PMBus protocol to carry out state monitoring and parameter configuration on the voltage conversion module through an independent channel.

4. A fully digital management apparatus for a wafer level processor system, as recited in claim 3, wherein: in the functional units, slave addresses of all bus type functional units are unified default addresses.

5. A fully digital management apparatus for a wafer level processor system, as recited in claim 1, wherein: the communication interface between the master control unit and the slave IO expansion unit is a full-duplex interface and comprises an independent sending channel and an independent receiving channel, each channel only comprises a clock line and a data line, and the data lines are responsible for serial transmission of configuration information and state information.