JP2009211780A - Address error detector and address error detecting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an address error detector having a small area, capable of detecting an obstacle with high probability, which is generated at an address decode section of a memory circuit. <P>SOLUTION: The address error detector includes: an X-encoder 105 for generating redundant codes having a plurality of bits from an output of an X-decoder 103; a Y-encoder 106 for outputting redundant codes having the number of bits same as that of the redundant codes from an output of a Y-decoder 104; an XOR circuit 107 for operating an exclusive OR of each bit for an output 10 of the X-encoder 105 and an output 11 of the Y-encoder 106; and an error detector 108 for detecting the error by inputting outputs 12 of the XOR circuit 107 and address signals 1. By the X-encoder 105, the Y-encoder 106 and the XOR circuit 107, a redundant section 12 is generated, by which the address signal is hamming coded. In the error detector 108, a multiplication of inspection matrix is carried out to an initial address signal and the generated redundant codes, and it is detected whether error is generated or not, to obtain the error output 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an address error detection device and an address error detection method for detecting a failure occurring in an address input unit and an address decoding unit in a memory circuit.

  In a system that requires high reliability, a mechanism for detecting a failure that occurs during operation is essential. The installed memory is no exception, but since it is a part that holds data, particularly high reliability is required. The memory includes a memory cell array unit that stores data and a decoder unit that decodes an address that designates a position where the data is stored. With respect to data held in the memory array, a mechanism for detecting a fault in which one or two bits of data are erroneous by adding redundant bits such as parity and error correction code is widely used.

  For example, Patent Document 1 shows an example in which a synchronous DRAM (Dynamic Random Access Memory) performs error recovery at the time of refresh by storing data after error correction encoding. In addition, since redundant code portions are distributed and held in a plurality of memory arrays, a mechanism is shown that performs error detection by integrating error detection codes obtained separately. As described above, for data, a number of methods for performing error detection by holding redundant codes in a memory area are disclosed.

  In many cases, the decoder unit is not provided with a mechanism for detecting a failure. However, in order to detect a failure, in Patent Documents 2, 3, and 4, the memory array that holds data is expanded, and a parity code generated from an address, a redundant code of an error correction code, or an address value itself is expanded. It is stored and the output of the extension portion is inspected at the time of reading to detect whether an incorrect address is accessed.

A method for detecting a failure occurring in the decoder has also been proposed. A large number of data is held in the memory array according to addresses. In a general memory, focusing on a certain bit of data, a plurality of pieces of data with different addresses are arranged in the row direction (X direction) and the column direction (Y direction). The cells in the Y direction are selected by the remaining bits and one cell is selected. In Patent Document 5, a circuit that generates and outputs a parity of a corresponding address portion from one signal selected by decoding an address that specifies an X direction and an address that specifies a Y direction are selected by decoding. Equipped with a circuit that generates and outputs the parity of the corresponding address part from the single signal, and generates the parity of the entire address by XOR (eXclusive OR) the output of each circuit, and the input address The failure of the address decoder unit is detected by comparing with the parity.
JP 2004-46969 A JP-A-5-181757 JP 7-105102 A JP-A-11-161560 JP-A-5-225797

  However, there are some problems in the method of increasing the memory area and holding the redundant code and address value. The first problem is that the memory capacity needs to be increased, and the size of the memory macro increases. Furthermore, the number of bits that can be handled by a memory macro may be limited, and it may not be possible to mount such a redundant code. In particular, when the number of bits is large, it may be divided and held in a plurality of memory macros, but this redundant code to be stored for detecting a failure of the decoder unit must be mounted in each memory macro. Yes and requires a lot of space. The second problem is an increase in power consumption. This is accompanied by an increase in memory capacity in order to retain redundant codes.

  There is also a problem with the method of incorporating a parity generation circuit in the decoder unit. That is, the fault detection capability is not so high. This is because only one bit error of the address bits can be detected by parity alone, and the decoder output in the X direction is 2 n if the bit to be decoded is n bits. This is because there are many signals that cannot be connected.

  The invention disclosed in Patent Document 1 relates to an apparatus for detecting data errors, and has a different purpose and configuration from the address error detection apparatus of the present invention described later. Patent Documents 2, 3, 4, and 5 are different in configuration from the present invention and cannot sufficiently solve the above problem.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a small area address error detection device and an address error detection method capable of detecting a failure occurring in an address decoding unit of a memory with high probability. To do.

  An address error detection device according to the present invention is an address error detection device for a memory circuit that designates a storage position in a memory array based on an address signal, and decodes a part of the address signal to select a row of the memory array. A first decoder means for generating a signal; a second decoder means for decoding the remainder of the address signal and generating a signal for selecting a column of the memory array; and an output signal output by the first decoder means. A first code generating means for generating a first code of a plurality of bits based on an input value of the first decoder, and a second decoder means for receiving an output signal output from the second decoder means. Second code generation means for generating a second code of a plurality of bits based on the input value of the first and second bit generation exclusive OR of the first code and the second code Wherein the XOR means for obtaining the code, and error detection means for inputting a third code determined by the address signal and the XOR unit, in that it comprises.

  In the address error detection apparatus according to the present invention, the first code generation means generates a first code based on a partial matrix of a generation matrix for generating an error correction code of the address signal, and the second code generation means A second code is generated based on partial matrices of different parts of the matrix, and the third code obtained from the exclusive OR of the first code and the second is a redundant part of the error correction code. Features.

  An address error detection apparatus according to the present invention decodes a part of an address signal and generates a signal for selecting a divided one of the memory array, and another part of the address signal. Second decoder means for generating a signal for selecting a row of the memory array; third decoder means for decoding the remainder of the address signal and generating a signal for selecting a column of the memory array; and first decoder means And a first code generation means for generating a first code of a plurality of bits based on an input value of the first decoder means, and an output signal generated by the second decoder means. In response, the second code generating means for generating a second code of a plurality of bits based on the input value of the second decoder means, and the output signal generated by the third decoder means And a third code generating means for generating a third code of a plurality of bits based on an input value of the third decoder means, and bits of the first code, the second code, and the third code XOR means for obtaining a fourth code from each exclusive OR, and error detection means for inputting the address signal and the fourth code obtained by the XOR means.

  In the address error detection apparatus according to the present invention, the first code generation means generates a first code based on a partial matrix of a generation matrix for generating an error correction code of the address signal, and the second code generation means The second code is generated based on the partial matrices of the different parts of the matrix, and the third code generation means generates the third code based on the partial matrices of the different parts of the generation matrix, and the first code and the first code The fourth code obtained from the exclusive OR of the code 2 and the third code is a redundant part of the error correction code.

  An address error detection method according to the present invention is an address error detection method for a memory circuit that designates a storage position in a memory array based on an address signal, and decodes a part of the address signal to select a row of the memory array. A first decoder step for generating a signal; a second decoder step for decoding a remainder of the address signal to generate a signal for selecting a column of the memory array; and an output signal output by the first decoder step. And receiving a first code generation step for generating a first code of a plurality of bits based on an input value of the first decoder step, and an output signal output by the second decoder step, and a second decoder A second code generation step for generating a second code of a plurality of bits based on the input value of the step, the first code and the second code And XOR determining a third code from the exclusive OR of each bit of the item, characterized in that it comprises, an error detecting step of inputting a third code determined by the address signal and the XOR step.

  In the address error detection method according to the present invention, the first code generation step generates a first code based on a partial matrix of a generation matrix that generates an error correction code of the address signal, and the second code generation step generates A second code is generated based on partial matrices of different parts of the matrix, and the third code obtained from the exclusive OR of the first code and the second is a redundant part of the error correction code. Features.

  An address error detection method according to the present invention includes a first decoder step for decoding a part of an address signal and generating a signal for selecting a divided one of the memory array, and another part of the address signal. A second decoder step for generating a signal for selecting a row of the memory array; a third decoder step for decoding a remainder of the address signal and generating a signal for selecting a column of the memory array; and a first decoder step A first code generation step for receiving the output signal selected by the first decoder step and generating a first code of a plurality of bits based on the input value of the first decoder step; and the output signal generated by the second decoder step And a second code generation step for generating a second code of a plurality of bits based on the input value of the second decoder step, A third code generation step for receiving the output signal generated by the decoder step and generating a third code of a plurality of bits based on an input value of the third decoder step; a first code and a second code; And an XOR step for obtaining the fourth code from the bitwise exclusive OR of the third code and the third code, and an error detection step for inputting the address signal and the fourth code obtained by the XOR step. Features.

  The first code generation step generates a first code based on a partial matrix of a generation matrix that generates an error correction code of the address signal, and the second code generation step based on a partial matrix of a different part of the generation matrix. A second code is generated, and a third code generation step generates a third code based on a partial matrix of a further different part of the generation matrix, and the first code, the second code, the third code, The fourth code obtained from the exclusive OR of is a redundant part of the error correction code.

  According to the present invention, the memory area can be reduced by providing the redundant code generation circuit for error detection. The present invention is particularly suitable for detecting a failure that occurs in an address input unit and an address decoding unit in a semiconductor memory circuit (memory) used in a system that requires a high degree of reliability.

  Embodiments of the present invention will be described below with reference to the drawings.

  A first embodiment of the present invention will be described below. FIG. 1 is a block diagram showing a configuration example of an error detection apparatus according to an embodiment of the present invention. In FIG. 1, the error detection apparatus includes a memory array 101, a Y selector 102, an X decoder 103, a Y decoder 104, an X encoder 105, a Y encoder 106, an XOR circuit 107, an error provided in the memory circuit 100. The detector 108 is configured as shown. An address input 1 is given to the X decoder 103, the Y decoder 104, and the error detector 108, and data input / output 2 is performed to the Y selector 102. Then, an error output 3 in which an error is detected is obtained from the error detector 108. The illustrated arrows indicate the word lines 4, 4 ′, the Y selection lines 5, 5 ′, and the bit line 6.

  The memory array 101 is a memory that holds data. In the memory array 101, 1 bit has a plurality of column configurations, and one of them is selected by the Y selector 102 according to the address. The X decoder 103 generates a signal for selecting a row in the vertical direction (X direction) of the memory array 101 in accordance with the address. The Y decoder 104 generates a signal for selecting a column in the vertical direction (Y direction) of the memory array 101 in accordance with the address. The X encoder 105 generates a redundant code 10 having a plurality of bits from the output of the X decoder 103. The Y encoder 106 outputs the redundant code 11 having the same number of bits as the redundant code generated by the X encoder 105 from the output of the Y decoder 104. The XOR circuit 107 performs an exclusive OR operation on the output 10 of the X encoder 105 and the output 11 of the Y encoder. The error detector 108 receives the output 12 of the XOR circuit 107 and the address signal 1 and performs error detection.

  FIG. 2 is a diagram showing an operation when an input address is 4 bits, 3 bits of them are decoded by the X decoder 103 and the remaining 1 bit is decoded by the Y decoder 104. The X decoder 103 receives 3 bits and outputs a signal to one of the 8 word lines 4 corresponding to 000 to 111. In response to this signal, the X encoder 105 outputs a 3-bit code 10. The code 10 is a value determined by using a part of a generation matrix of a Hamming code, which will be described later, and a different 3-bit code is assigned to each of the eight decoded signals.

  The Y decoder 104 decodes one bit and outputs a signal to one of the two Y selection lines 5. In response to this signal, the Y encoder 106 outputs a 3-bit code 11. This code 11 is also determined by using a part of a Hamming code generation matrix, which will be described later. The codes 10 and 11 of the 3-bit output of the X encoder 105 and the Y encoder 106 are exclusively ORed by the XOR circuit 107 for each bit to become a redundant portion 12 of the Hamming code of the address, and an error detector 108 is input.

  FIG. 3 is a configuration diagram illustrating an output code of the encoder according to the embodiment of the present invention. The codes 10 and 11 output from the X encoder 105 and the Y encoder 106 will be described with reference to FIG. If a 4-bit signal is Hamming encoded, a 7-bit code is obtained. Of these, 4 bits are the original signal itself, and 3 bits are the redundant portion 12. The operation for creating such a Hamming code will be described below.

  In FIG. 3, a check matrix H for checking a 3-bit code is created first. This is a matrix in which 7 types of 3-bit codes excluding 000 are arranged in each column, and is a matrix of 3 rows and 7 columns. The columns may be arranged in any order, but in order to make the code so that the Hamming code obtained by creating the generator matrix created from this check matrix can be neatly divided into the original 4-bit value and the redundant code part, The 3 columns are made to be a 3 × 3 unit matrix. For convenience, three independent values are selected in the three rows from the left. The term “independent” as used herein refers to three values that do not become the remaining values when two values are selected and added (exclusive OR).

  To create a 4 × 7 generator matrix G from this parity check matrix, a 3 × 4 portion of the parity check matrix H that is not a unit matrix is transposed to form a 4 × 3 matrix and placed in the right 3 columns. A 4-by-4 unit matrix may be added to the left side. In order to generate a Hamming code of a certain 4-bit value, the 4-bit value may be multiplied by the generation matrix G from the right. Since a 4 × 7 matrix is multiplied, a 4-bit value becomes a 7-bit code. At this time, since the result obtained by multiplying the unit matrix portion is the value itself, the left 4 bits are the original 4-bit value, and the remaining 3 bits are added with redundant code bits.

  Using the 4 × 3 portion of the generator matrix G, the redundant code of the redundant portion 12 of the present invention is created. The 4 bits of the address is multiplied by the matrix of 4 rows and 3 columns. The X encoder 105 generates a code using the upper 3 rows and 3 columns of the 4 rows and 3 columns. The X decoder 103 outputs one corresponding to eight values from 000 to 111, and in accordance with this, encoding is performed so as to output the result of multiplying this 3-bit value by a 3 × 3 matrix. Make a vessel. For example, when 000 is multiplied by this matrix, the result is 000. Therefore, when a signal corresponding to 000 is received on the word line 5, the X encoder 105 outputs 000. Since the result multiplied by 111 is 001, the output is 001. Similarly, a 3-bit value is output for other values.

  One of the outputs 5 of the Y decoder 104 is output for 0 and 1 of 1 bit. Here again, the code to be output is determined by multiplying the lower right 1 × 3 matrix of the generator matrix G. That is, 000 is output for 0 and 110 is output for 1.

  The XOR circuit 107 performs an exclusive OR operation on the two codes 10 and 11 output by these, thereby multiplying a 4 × 3 matrix. This is the code itself of the redundant part 12. The error detector 108 obtains an error output 3 based on the code of the redundant unit 12 and the address input 1.

  FIG. 4 shows a simple circuit example of the 0 output circuit 120 and the 1 output circuit 121. FIG. 5 shows another configuration example of the 0 output circuit and the 1 output circuit. For the X encoder 105 and the Y encoder 106, a 0 output circuit 120 and a 1 output circuit 121 are used. An example of the configuration will be described with reference to FIGS.

  As shown in FIG. 4, two output lines 21 and 21 ′ are prepared for each bit of the code, and precharged in advance by pMOS (Positive channel Metal Oxide Semiconductor) transistors 200 and 201 by a precharge signal 22. Keep it. In the 0 output circuit 120, the output line 21 is discharged by an nMOS (Negative channel Metal Oxide Semiconductor) transistor 300 having a drain connected to the output line 21 and a gate connected to the selection line 20.

  In the 1-output circuit 121, the output line 21 ′ is discharged by the nMOS transistor 301 having the drain connected to the output line 21 ′ and the gate connected to the selection line 20 ′. It may be detected that 0 is output when the output line 21 is discharged and 1 is output when the output line 21 ′ is discharged. Since this circuit can be formed with the smallest number of transistors, it can be used not only with the X encoder 105 but also with the Y encoder 106. In the X encoder 105, the selection lines 20 and 20 ′ correspond to the word line 4, and in the Y encoder 106, the selection lines 20 and 20 ′ correspond to the Y selection line 5.

  Since the X encoder 105 is normally arranged adjacent to the memory cell, it is easy to lay out if an ordinary 6-transistor memory cell is an improved circuit. FIG. 5 shows a circuit of a 6-transistor 0 output circuit 120 ′ and 1 output circuit 121 ′ composed of two pMOS transistors and four nMOS transistors.

  In the 0 output circuit 120 ′, the drain of the load pMOS transistor 203 on the output line 21 ′ side is disconnected from the drain of the drive nMOS transistor 305 and the source of the access nMOS transistor 303, and the gates of the pMOS transistor 203 and the nMOS transistor 305 are connected to the ground potential. To do. As a result, the pMOS transistor 203 is always turned on, the pMOS transistor 202 constituting the inverter on the opposite side is turned off, the nMOS transistor 304 is turned on, and the output line 21 is pulled down when the selection line 20 rises.

  The 1 output circuit 121 'is obtained by replacing the output line 21 and the output line 21' of the 0 output circuit 120 '. Similar to the circuit of FIG. 4, it is sufficient to detect 0 when the output line 21 is pulled down and 1 when the output line 21 'is pulled down. The selection lines 20 and 20 ′ correspond to the word line 4.

  Here, a case where a 4-bit address signal is divided into a 3-bit X decode and a 1-bit Y decode is shown. Further, when the address bit length is long, a 4-bit redundant code may be used up to an 11-bit address, and a similar circuit can be created using a 5-bit redundant code up to 26 bits.

  When creating the parity check matrix H, a 4-bit redundant code with 11-bit address results in a 4-row, 15-column matrix, but only 4 columns can be selected as independent columns. Can not do it. In the case of more decoded signals, the same code is output. For this reason, an error in the decoded signal cannot be completely detected, but the detection capability is greatly improved as compared with the case where there are only 0 and 1 such as parity. Further, when it is desired to completely detect errors, the number of redundant code bits may be increased in order to increase independent rows. An n-bit redundant code is sufficient to distinguish between n-bit decoded outputs.

  The above operation will be described in summary. In FIG. 1 and FIG. 2, the memory array 101 operates when a row direction selection signal generated by the X decoder 103 and passed through the X encoder 106 and output to the word line 4 ′ is input. Data is input / output to / from the line 6, and the column direction selection signal output to the Y selection line 5 ′ through the Y encoder 105 is input to the Y selector 102. Input / output 2 is performed.

  The X encoder 105, the Y encoder 106, and the XOR circuit 107 generate the redundant part 12 in which the address signal is Hamming encoded. The Hamming code can be generated by multiplying the original bit string by a generator matrix. Here, since the binary system is used, when performing the inner product operation in the multiplication of the matrix, each element is ANDed to obtain an exclusive logical ring. Since this inner product operation is based on a coupling rule, it can be performed in parallel for each part. Therefore, the inner product operation of the bit portion decoded by the X decoder 103 is performed by the X encoder 105, the inner product operation of the bit portion decoded by the Y decoder 103 is performed by the Y encoder 106, and finally the XOR circuit 107. It is possible to calculate together.

  The error detector 108 multiplies the generated Hamming code by a check matrix, detects whether an error has occurred, and obtains an error output 3. The result of Hamming encoding the address value can be obtained by combining the original address value and the output of the XOR circuit 107. These are multiplied by a check matrix. If all the results are 0, there is no error, and if any bit is 1, an error is detected.

  FIG. 6 shows an example where the bit lines have a hierarchy. A second embodiment of the present invention will be described with reference to FIG. In FIG. 6, parts corresponding to those in FIGS. 1 and 2 described above are denoted by the same reference numerals and redundant description is omitted.

  When the bit line has a hierarchy, the memory array is divided into a plurality of parts, and the X decoder has a hierarchical structure. This is a hierarchical configuration of a first X decoder 109 that selects a row in the X direction in one memory array and a second X decoder 110 that selects one of the plurality of memory arrays.

  Of the 7-bit address, the first X decoder 109 decodes 3 bits, the second X decoder 110 decodes the other 3 bits, and the Y decoder 104 decodes the remaining 1 bit. Since the address is 7 bits, the redundant code of the redundant part 12 'requires 4 bits. In response to the decode signal from the first X decoder 109, the X encoder 105 outputs a 4-bit redundant code 10 "corresponding to codes 000 to 111. The Y encoder 104 receives the output from the Y decoder 104 and encodes Y. The unit 106 outputs a 4-bit code 11 '.

  Further, the first X decoder 109 and the Y decoder 104 are operated by one signal 7 of the eight bank selection lines output from the second X decoder 110, and the 4-bit code of the corresponding bit is also detected from this signal. 13 and XOR of these three outputs 10 ″, 11 ′, and 13 to generate a redundant code of the redundant part 12 ′. The error detector 108 uses the 7-bit address input 1 and the redundant code. An error is detected and an error output 3 is obtained, although only one memory array is shown in Fig. 6, but the same circuit configuration is adopted for the other seven memory arrays.

  FIG. 7 is a diagram showing a method for generating a 4-bit redundant code from a 7-bit address. A 15-bit Hamming code can be generated by adding a 4-bit redundant code to an 11-bit numerical value. However, in the case of a 7-bit address, a check matrix H is generated assuming that 4 of 11 bits are 0. Consider the matrix G. The check matrix H is a 4 × 15 matrix in which 15 4-bit values excluding 0000 are arranged in each column. As in the case of FIG. 3 described above, the right four columns are unit matrices. For convenience, the left four columns are arranged with four independent values, the next four columns are arranged with another four independent values, and the next three columns are arranged with three independent values.

  The generator matrix G is an 11-row 15-column matrix in which an 11-row 4-column matrix obtained by transposing a 4-row 11-column matrix obtained by removing the unit matrix portion from the parity check matrix H to a 11-row 11-column unit matrix is added to the right. is there. In order to generate an 11-bit hamming code, a 15-bit value may be obtained by multiplying the generator matrix G from the right. Since the right 11 rows and 11 columns are unit matrices, the left 11 bits of the generated Hamming code are the original values themselves, and a 4-bit redundant code is added to this. A portion for generating a 4-bit code corresponding to the X encoder 105, the Y encoder 106, and the first X decoder 109 is generated from an 11 × 4 matrix for generating a redundant code portion.

  The X encoder 105 generates a 4-bit code using 3 of the 4 rows from the top. Since the four rows from the top are independent values for each row, even if the three rows and four columns obtained by selecting the three rows are multiplied by a 3-bit value, all different codes can be generated. On the other hand, a different code is output. Similarly, for the eight outputs of the second X decoder 110, three of four independent rows from the fifth row to the eighth row are selected and multiplied by a matrix of 3 rows and 4 columns to obtain a different 4-bit It is possible to generate a code. Also for the Y decoder 104, a code is generated by selecting one line from the last three lines.

  Here, for simplicity, the first X decoder 109 decodes 3 bits, the second X decoder 110 decodes 3 bits, and the Y decoder 104 decodes 1 bit. Since the matrix of 11 rows and 4 columns for generating redundant codes is an independent row of 4 rows, 4 rows and 3 rows, the first X decoder 109 and the second X decoder 110 decode 4 bits into 16 rows. Even in this case, it is possible to output different codes. The Y decoder 104 can output different codes even in a decoder that decodes 3 bits and outputs eight signals. With such a configuration, it is possible to detect a failure in which a different signal line is selected for each decoder.

  The effects of the first and second embodiments described above will be described. The first effect is that the memory area can be reduced. This is because it is not necessary to secure an area for storing redundant codes in the memory macro by adding a redundant code generation circuit for error detection. For example, if the memory array has 4 columns per bit, the redundant code storage area needs 16 columns if the redundant code is 4 bits, but can be realized with an area of 4 columns. It is. Furthermore, if the configuration is 8 columns per bit, the 32 column width can be reduced to 4 column widths, so the area can be greatly reduced. In particular, it is suitable for detecting a failure that occurs in an address input unit and an address decoding unit in a semiconductor memory circuit (memory) used in a system that requires high reliability.

  The second effect is that power consumption can be reduced. The reason is that unnecessary power is not generated by eliminating the need for a memory area for holding redundant codes and address values. A third effect is that a failure occurring in the address decoder section can be detected with high probability. The reason is that a different redundancy code can be assigned to each signal after decoding, or even if different redundancy codes are not assigned to all of the decoded signals, there are two types of parity but more types of codes. This is because the selected decoded signal can be distinguished with high probability. In addition, the redundant code of the redundant part can be easily generated by using the Hamming coding.

  The operation of each means according to the embodiment of the present invention that brings about the above effect will be described. In the address error detection device according to the embodiment of the present invention, the address signal is divided into a row address, a column address, and further a bank address, and a plurality of codes of a plurality of bits are generated in parallel from the decoded results. A redundant part of one error correction code of the original address is generated by performing an exclusive OR. Error detection is performed by obtaining a syndrome from the code and the original address by an error detection circuit.

  In the address error detection apparatus according to the embodiment of the present invention, the bit length of the input address or the bit length divided into each decoder is given a restriction derived from the code bit length, so that it can be obtained corresponding to the decoding result. The error detection probability is increased by making all the signs of the output to be different.

It is a block diagram which shows the structural example of the error detection apparatus by embodiment of this invention. It is a block diagram explaining operation | movement of embodiment of this invention. It is a block diagram explaining the output code | symbol of the encoder which concerns on embodiment of this invention. It is a circuit diagram which shows 0 output circuit and 1 output circuit in embodiment of this invention. It is a circuit diagram which shows the other 0 output circuit and 1 output circuit in embodiment of this invention. It is a block diagram which shows the structure of the error detection apparatus by embodiment of this invention. It is a block diagram explaining the output code | symbol of the encoder in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Address input 2 Data input / output 3 Error output 4, 4 'Word line 5, 5' Y selection line 6 Bit line 10 X code 11 Y code 12 Redundant part 20, 20 'Selection line 21, 21' Output line 22 Precharge Signal 100 Memory circuit 101 Memory array 102 Y selector 103 X decoder 104 Y decoder 105 X encoder 106 Y encoder 107 XOR circuit 108 Error detection circuit 109 1st X decoder 110 2nd X decoder 120, 120 '0 output circuit 121, 121 '1 output circuit 200-204 pMOS transistor 300-309 nMOS transistor

Claims (16)

An address error detection device for a memory circuit that designates a storage position in a memory array based on an address signal,
First decoder means for decoding a portion of the address signal and generating a signal for selecting a row of the memory array;
Second decoder means for decoding the remainder of the address signal and generating a signal for selecting a column of the memory array;
First code generation means for receiving an output signal output from the first decoder means and generating a first code of a plurality of bits based on an input value of the first decoder means;
Second code generation means for receiving an output signal output from the second decoder means and generating a second code of a plurality of bits based on an input value of the second decoder means;
XOR means for obtaining a third code from a bitwise exclusive OR of the first code and the second code;
An address error detection device comprising: an error detection unit that inputs the address signal and the third code obtained by the XOR unit. The first code generation means generates the first code based on a partial matrix of a generation matrix that generates an error correction code of the address signal,
The second code generation means generates the second code based on partial matrices of different parts of the generation matrix,
2. The address error detection apparatus according to claim 1, wherein the third code obtained from an exclusive OR of the first code and the second code is a redundant part of the error correction code. The code length of the first code generated by the first code generation means is equal to the code length of the second code generated by the second code generation means,
The code length of the first code is equal to or longer than the input signal length of the first decoder means,
3. The address error detection apparatus according to claim 1, wherein the second code has a code length equal to or longer than an input signal length of the second decoder means.   4. The address error detection device according to claim 2, wherein the redundant section is obtained by Hamming encoding the address signal. An address error detection device for a memory circuit for designating a storage position in a memory array divided into a plurality based on an address signal,
First decoder means for decoding a part of the address signal and generating a signal for selecting a divided one of the memory array;
Second decoder means for decoding another portion of the address signal and generating a signal for selecting a row of the memory array;
Third decoder means for decoding the remainder of the address signal and generating a signal for selecting a column of the memory array;
First code generation means for receiving an output signal selected by the first decoder means and generating a first code of a plurality of bits based on an input value of the first decoder means;
Second code generation means for receiving an output signal generated by the second decoder means and generating a second code of a plurality of bits based on an input value of the second decoder means;
Third code generation means for receiving an output signal generated by the third decoder means and generating a third code of a plurality of bits based on an input value of the third decoder means;
XOR means for obtaining a fourth code from a bitwise exclusive OR of the first code, the second code, and the third code;
An error detection means comprising: an error detection means for inputting the address signal and the fourth code obtained by the XOR means. The first code generation means generates the first code based on a partial matrix of a generation matrix that generates an error correction code of the address signal,
The second code generation means generates the second code based on partial matrices of different parts of the generation matrix,
The third code generation means generates the third code based on a partial matrix of a further different part of the generation matrix,
6. The fourth code obtained from an exclusive OR of the first code, the second code, and the third code is a redundant part of the error correction code. The described address error detection device. The code length of the first code generated by the first code generation means, the code length of the second code generated by the second code generation means, and the code length of the second code generated by the third code generation means The code lengths of the third codes are all equal,
The code length of the first code is equal to or longer than the input signal length of the first decoder means,
The code length of the second code is equal to or longer than the input signal length of the second decoder means,
7. The address error detection apparatus according to claim 5, wherein a code length of the third code is equal to or longer than an input signal length of the third decoder means.   The address error detection device according to claim 6 or 7, wherein the redundancy section is obtained by Hamming encoding the address signal. An address error detection method for a memory circuit that designates a storage position in a memory array based on an address signal,
A first decoder step for decoding a portion of the address signal and generating a signal for selecting a row of the memory array;
A second decoder step for decoding a remainder of the address signal and generating a signal for selecting a column of the memory array;
A first code generation step of receiving an output signal output by the first decoder step and generating a first code of a plurality of bits based on an input value of the first decoder step;
A second code generation step of receiving an output signal output by the second decoder step and generating a second code of a plurality of bits based on an input value of the second decoder step;
An XOR step for obtaining a third code from a bitwise exclusive OR of the first code and the second code;
An error detection step comprising: an error detection step of inputting the address signal and the third code obtained in the XOR step. The first code generation step generates the first code based on a partial matrix of a generation matrix that generates an error correction code of the address signal,
The second code generation step generates the second code based on partial matrices of different parts of the generation matrix,
10. The address error detection method according to claim 9, wherein the third code obtained from an exclusive OR of the first code and the second code is a redundant part of the error correction code. The code length of the first code generated by the first code generation step is equal to the code length of the second code generated by the second code generation step;
The code length of the first code is equal to or longer than the input signal length of the first decoder step,
The address error detection method according to claim 9 or 10, wherein a code length of the second code is equal to or longer than an input signal length of the second decoder step.   The address error detection method according to claim 10 or 11, wherein the redundant section is obtained by Hamming encoding the address signal. An address error detection method for a memory circuit for designating a storage position in a memory array divided into a plurality based on an address signal,
A first decoder step for decoding a portion of the address signal and generating a signal for selecting a divided one of the memory array;
A second decoder step for decoding another portion of the address signal and generating a signal for selecting a row of the memory array;
A third decoder step for decoding a remainder of the address signal and generating a signal for selecting a column of the memory array;
A first code generation step of receiving an output signal selected by the first decoder step and generating a first code of a plurality of bits based on an input value of the first decoder step;
A second code generation step of receiving an output signal generated by the second decoder step and generating a second code of a plurality of bits based on an input value of the second decoder step;
A third code generation step of receiving an output signal generated by the third decoder step and generating a third code of a plurality of bits based on an input value of the third decoder step;
An XOR step of obtaining a fourth code from a bitwise exclusive OR of the first code, the second code, and the third code;
An error detection step, comprising: an error detection step of inputting the address signal and the fourth code obtained in the XOR step. The first code generation step generates the first code based on a partial matrix of a generation matrix that generates an error correction code of the address signal,
The second code generation step generates the second code based on partial matrices of different parts of the generation matrix,
The third code generation step generates the third code based on a partial matrix of a different part of the generation matrix,
14. The fourth code obtained from an exclusive OR of the first code, the second code, and the third code is a redundant part of the error correction code. The address error detection method described. The code length of the first code generated by the first code generation step, the code length of the second code generated by the second code generation step, and the code length of the second code generated by the third code generation step The code lengths of the third codes are all equal,
The code length of the first code is equal to or longer than the input signal length of the first decoder step,
The code length of the second code is equal to or longer than the input signal length of the second decoder step,
15. The address error detection method according to claim 13, wherein a code length of the third code is equal to or longer than an input signal length of the third decoder step.   16. The address error detection method according to claim 14, wherein the redundancy section is obtained by Hamming encoding the address signal.

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