EP3655950A4 - LOCK OFFSET CANCELLATION IN A MEMORY DEVICE - Google Patents
LOCK OFFSET CANCELLATION IN A MEMORY DEVICE Download PDFInfo
- Publication number
- EP3655950A4 EP3655950A4 EP18834622.5A EP18834622A EP3655950A4 EP 3655950 A4 EP3655950 A4 EP 3655950A4 EP 18834622 A EP18834622 A EP 18834622A EP 3655950 A4 EP3655950 A4 EP 3655950A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- latching
- memory device
- offset cancellation
- cancellation
- offset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2253—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2297—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0409—Online test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/655,644 US10163481B1 (en) | 2017-07-20 | 2017-07-20 | Offset cancellation for latching in a memory device |
| PCT/US2018/042584 WO2019018462A2 (en) | 2017-07-20 | 2018-07-18 | CANCELING LOCK OFFSET IN A MEMORY DEVICE |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP3655950A2 EP3655950A2 (en) | 2020-05-27 |
| EP3655950A4 true EP3655950A4 (en) | 2021-04-07 |
Family
ID=64692363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP18834622.5A Pending EP3655950A4 (en) | 2017-07-20 | 2018-07-18 | LOCK OFFSET CANCELLATION IN A MEMORY DEVICE |
Country Status (7)
| Country | Link |
|---|---|
| US (3) | US10163481B1 (ko) |
| EP (1) | EP3655950A4 (ko) |
| JP (1) | JP6812061B2 (ko) |
| KR (1) | KR102311984B1 (ko) |
| CN (1) | CN110959176B (ko) |
| SG (1) | SG11202000196RA (ko) |
| WO (1) | WO2019018462A2 (ko) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9899073B2 (en) * | 2016-06-27 | 2018-02-20 | Micron Technology, Inc. | Multi-level storage in ferroelectric memory |
| KR102643532B1 (ko) * | 2018-08-28 | 2024-03-06 | 에스케이하이닉스 주식회사 | 비트라인 센스앰프 회로 |
| US10692557B1 (en) | 2019-04-11 | 2020-06-23 | Micron Technology, Inc. | Reference voltage management |
| US11289146B2 (en) * | 2019-08-27 | 2022-03-29 | Micron Technology, Inc. | Word line timing management |
| US11869624B2 (en) | 2020-07-27 | 2024-01-09 | Changxin Memory Technologies, Inc. | Sense amplifier, memory and method for controlling sense amplifier |
| CN111863052B (zh) * | 2020-07-27 | 2022-11-01 | 安徽大学 | 灵敏放大器、存储器和灵敏放大器的控制方法 |
| CN111863050B (zh) | 2020-07-27 | 2022-10-28 | 安徽大学 | 灵敏放大器、存储器和灵敏放大器的控制方法 |
| KR102652188B1 (ko) * | 2023-09-08 | 2024-03-28 | 연세대학교 산학협력단 | 전류 래치 센스 앰프 및 메모리 장치 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150016183A1 (en) * | 2013-07-12 | 2015-01-15 | Nvidia Corporation | Sense amplifier with transistor threshold compensation |
| US20160300599A1 (en) * | 2015-04-09 | 2016-10-13 | Freescale Semiconductor, Inc. | Mismatch-compensated sense amplifier for highly scaled technology |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4069963B2 (ja) | 1996-11-14 | 2008-04-02 | 富士通株式会社 | Ｍｏｓトランジスタ敷居値補償回路及びこれを備えたフリップフロップ型センスアンプ |
| US6535025B2 (en) * | 2000-02-02 | 2003-03-18 | Broadcom Corp. | Sense amplifier with offset cancellation and charge-share limited swing drivers |
| US6466501B2 (en) * | 2000-06-28 | 2002-10-15 | Hynix Semiconductor Inc. | Semiconductor memory device having sense amplifier and method for driving sense amplifier |
| JP3959417B2 (ja) | 2004-10-29 | 2007-08-15 | 株式会社東芝 | 半導体メモリの読み出し回路 |
| JP2006186150A (ja) * | 2004-12-28 | 2006-07-13 | Hitachi Ltd | 半導体記憶装置の製造方法及び半導体設計装置 |
| JP5142906B2 (ja) * | 2008-09-18 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | センスアンプ、およびそのセンスアンプを搭載した半導体記憶装置 |
| US7898838B2 (en) | 2008-10-31 | 2011-03-01 | Seagate Technology Llc | Resistive sense memory calibration for self-reference read method |
| US8598912B2 (en) | 2010-06-14 | 2013-12-03 | Micron Technology, Inc. | Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers |
| US8405375B2 (en) * | 2011-06-24 | 2013-03-26 | Elite Semiconductor Memory Technology Inc. | Intermittently activated bandgap reference circuit |
| US8767482B2 (en) * | 2011-08-18 | 2014-07-01 | Micron Technology, Inc. | Apparatuses, devices and methods for sensing a snapback event in a circuit |
| KR101656599B1 (ko) * | 2012-06-28 | 2016-09-09 | 휴렛 팩커드 엔터프라이즈 디벨롭먼트 엘피 | 멀티-레벨 셀 메모리 |
| JP2014241181A (ja) | 2013-06-12 | 2014-12-25 | マイクロンメモリジャパン株式会社 | 半導体装置 |
| US9140747B2 (en) * | 2013-07-22 | 2015-09-22 | Qualcomm Incorporated | Sense amplifier offset voltage reduction |
| US9111623B1 (en) * | 2014-02-12 | 2015-08-18 | Qualcomm Incorporated | NMOS-offset canceling current-latched sense amplifier |
| US9286976B2 (en) * | 2014-05-29 | 2016-03-15 | Intel Corporation | Apparatuses and methods for detecting write completion for resistive memory |
| US9552864B1 (en) | 2016-03-11 | 2017-01-24 | Micron Technology, Inc. | Offset compensation for ferroelectric memory cell sensing |
| US9911501B2 (en) * | 2016-05-24 | 2018-03-06 | Silicon Storage Technology, Inc. | Sensing amplifier comprising a built-in sensing offset for flash memory devices |
| US9858979B1 (en) * | 2016-10-05 | 2018-01-02 | Micron Technology, Inc. | Reprogrammable non-volatile ferroelectric latch for use with a memory controller |
-
2017
- 2017-07-20 US US15/655,644 patent/US10163481B1/en active Active
-
2018
- 2018-07-18 WO PCT/US2018/042584 patent/WO2019018462A2/en unknown
- 2018-07-18 CN CN201880047927.7A patent/CN110959176B/zh active Active
- 2018-07-18 SG SG11202000196RA patent/SG11202000196RA/en unknown
- 2018-07-18 KR KR1020207004421A patent/KR102311984B1/ko active IP Right Grant
- 2018-07-18 JP JP2020501797A patent/JP6812061B2/ja active Active
- 2018-07-18 EP EP18834622.5A patent/EP3655950A4/en active Pending
- 2018-11-08 US US16/184,823 patent/US10679689B2/en active Active
-
2020
- 2020-05-04 US US16/866,204 patent/US11087817B2/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150016183A1 (en) * | 2013-07-12 | 2015-01-15 | Nvidia Corporation | Sense amplifier with transistor threshold compensation |
| US20160300599A1 (en) * | 2015-04-09 | 2016-10-13 | Freescale Semiconductor, Inc. | Mismatch-compensated sense amplifier for highly scaled technology |
Non-Patent Citations (1)
| Title |
|---|
| LEE ALBERT ET AL: "An embedded ReRAM using a small-offset sense amplifier for low-voltage operations", VLSI DESIGN, AUTOMATION AND TEST(VLSI-DAT), IEEE, 27 April 2015 (2015-04-27), pages 1 - 4, XP032781550, DOI: 10.1109/VLSI-DAT.2015.7114532 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20190147933A1 (en) | 2019-05-16 |
| KR20200020970A (ko) | 2020-02-26 |
| WO2019018462A3 (en) | 2019-02-28 |
| US20200265885A1 (en) | 2020-08-20 |
| US10163481B1 (en) | 2018-12-25 |
| KR102311984B1 (ko) | 2021-10-14 |
| CN110959176A (zh) | 2020-04-03 |
| US11087817B2 (en) | 2021-08-10 |
| CN110959176B (zh) | 2021-08-06 |
| US10679689B2 (en) | 2020-06-09 |
| JP6812061B2 (ja) | 2021-01-13 |
| WO2019018462A2 (en) | 2019-01-24 |
| JP2020528192A (ja) | 2020-09-17 |
| SG11202000196RA (en) | 2020-02-27 |
| EP3655950A2 (en) | 2020-05-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
| 17P | Request for examination filed |
Effective date: 20191224 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
| AX | Request for extension of the european patent |
Extension state: BA ME |
|
| DAV | Request for validation of the european patent (deleted) | ||
| DAX | Request for extension of the european patent (deleted) | ||
| A4 | Supplementary search report drawn up and despatched |
Effective date: 20210304 |
|
| RIC1 | Information provided on ipc code assigned before grant |
Ipc: G11C 11/22 20060101AFI20210226BHEP Ipc: G11C 29/02 20060101ALI20210226BHEP Ipc: G11C 7/06 20060101ALI20210226BHEP Ipc: G11C 29/04 20060101ALN20210226BHEP Ipc: G11C 7/08 20060101ALI20210226BHEP Ipc: G11C 11/4091 20060101ALI20210226BHEP |