EP3533146A4 - Verfahren und vorrichtung zur codierung und decodierung von ldpc-codes - Google Patents
Verfahren und vorrichtung zur codierung und decodierung von ldpc-codes Download PDFInfo
- Publication number
- EP3533146A4 EP3533146A4 EP17866591.5A EP17866591A EP3533146A4 EP 3533146 A4 EP3533146 A4 EP 3533146A4 EP 17866591 A EP17866591 A EP 17866591A EP 3533146 A4 EP3533146 A4 EP 3533146A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- encoding
- ldpc codes
- decoding ldpc
- decoding
- codes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/033—Theoretical methods to calculate these checking codes
- H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
- H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
- H03M13/6393—Rate compatible low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
- H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP23166566.2A EP4224718A1 (de) | 2016-11-03 | 2017-05-25 | Verfahren und vorrichtung zur codierung und decodierung von ldpc-codes |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/RU2016/000746 WO2018084735A1 (en) | 2016-11-03 | 2016-11-03 | Efficiently decodable qc-ldpc code |
PCT/CN2017/086017 WO2018082290A1 (en) | 2016-11-03 | 2017-05-25 | Method and apparatus for encoding and decoding ldpc codes |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP23166566.2A Division EP4224718A1 (de) | 2016-11-03 | 2017-05-25 | Verfahren und vorrichtung zur codierung und decodierung von ldpc-codes |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3533146A1 EP3533146A1 (de) | 2019-09-04 |
EP3533146A4 true EP3533146A4 (de) | 2019-10-09 |
Family
ID=57680462
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP17866591.5A Ceased EP3533146A4 (de) | 2016-11-03 | 2017-05-25 | Verfahren und vorrichtung zur codierung und decodierung von ldpc-codes |
EP23166566.2A Pending EP4224718A1 (de) | 2016-11-03 | 2017-05-25 | Verfahren und vorrichtung zur codierung und decodierung von ldpc-codes |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP23166566.2A Pending EP4224718A1 (de) | 2016-11-03 | 2017-05-25 | Verfahren und vorrichtung zur codierung und decodierung von ldpc-codes |
Country Status (9)
Country | Link |
---|---|
US (2) | US10567002B2 (de) |
EP (2) | EP3533146A4 (de) |
JP (1) | JP7152394B2 (de) |
KR (1) | KR102155539B1 (de) |
CN (1) | CN110572163B (de) |
AU (1) | AU2017355038B2 (de) |
BR (1) | BR112019009090A2 (de) |
RU (1) | RU2739465C2 (de) |
WO (2) | WO2018084735A1 (de) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2018128559A1 (en) | 2017-01-09 | 2018-07-12 | Huawei Technologies Co., Ltd. | Efficiently decodable qc-ldpc code |
CA3094841C (en) * | 2017-03-24 | 2023-05-02 | Zte Corporation | Processing method and device for quasi-cyclic low density parity check coding |
CN110535474B (zh) | 2017-05-05 | 2023-06-06 | 华为技术有限公司 | 信息处理的方法、通信装置 |
US10879927B2 (en) * | 2017-05-17 | 2020-12-29 | Futurewei Technologies, Inc. | Compact low density parity check (LDPC) base graph |
EP3588786B1 (de) | 2017-06-15 | 2022-11-16 | Huawei Technologies Co., Ltd. | Qc-ldpc kodes für 3gpp 5g mobilfunk |
CN109327225B9 (zh) | 2017-06-27 | 2021-12-10 | 华为技术有限公司 | 信息处理的方法、装置和通信设备 |
EP3771105B1 (de) | 2018-05-29 | 2022-10-05 | Mitsubishi Electric Corporation | Sender, empfänger, kommunikationssystem und verfahren zur revision der codierungsrate |
WO2020145516A1 (ko) * | 2019-01-07 | 2020-07-16 | 엘지전자 주식회사 | 무선 통신 시스템에서 저밀도 패리티 체크 행렬을 이용한 채널 코딩을 수행하는 방법 및 장치 |
CN109936379B (zh) * | 2019-01-24 | 2021-07-09 | 南京大学 | 一种多码率ldpc码的构造方法及其解码装置 |
CN110611510B (zh) * | 2019-09-17 | 2021-03-23 | 天地信息网络研究院(安徽)有限公司 | 一种二元ldpc短码构造方法及其构造装置、终端、存储介质 |
CN112583420B (zh) * | 2019-09-30 | 2024-01-09 | 上海华为技术有限公司 | 一种数据处理方法和译码器 |
CN112751571A (zh) | 2019-10-30 | 2021-05-04 | 华为技术有限公司 | 一种ldpc的编码方法及装置 |
US11513895B1 (en) | 2021-06-11 | 2022-11-29 | Western Digital Technologies, Inc. | Data storage device processing problematic patterns as erasures |
US11929762B2 (en) | 2021-11-24 | 2024-03-12 | Samsung Electronics Co., Ltd. | Low density parity check decoder and storage device |
KR20230164328A (ko) * | 2022-05-25 | 2023-12-04 | 삼성전자주식회사 | 통신 시스템에서 저밀도 패리티 검사 부호의 레이어드 복호화 방법 및 장치 |
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US20140229788A1 (en) * | 2013-02-13 | 2014-08-14 | Qualcomm Incorporated | Ldpc design for high rate, high parallelism, and low error floor |
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2016
- 2016-11-03 WO PCT/RU2016/000746 patent/WO2018084735A1/en active Application Filing
-
2017
- 2017-05-25 RU RU2019116852A patent/RU2739465C2/ru active
- 2017-05-25 CN CN201910723860.0A patent/CN110572163B/zh active Active
- 2017-05-25 JP JP2019522735A patent/JP7152394B2/ja active Active
- 2017-05-25 EP EP17866591.5A patent/EP3533146A4/de not_active Ceased
- 2017-05-25 WO PCT/CN2017/086017 patent/WO2018082290A1/en unknown
- 2017-05-25 KR KR1020197014018A patent/KR102155539B1/ko active IP Right Grant
- 2017-05-25 BR BR112019009090-8A patent/BR112019009090A2/pt unknown
- 2017-05-25 AU AU2017355038A patent/AU2017355038B2/en active Active
- 2017-05-25 EP EP23166566.2A patent/EP4224718A1/de active Pending
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2019
- 2019-05-01 US US16/400,877 patent/US10567002B2/en active Active
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2020
- 2020-01-22 US US16/749,453 patent/US11265014B2/en active Active
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Title |
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HUANG-CHANG LEE ET AL: "Two Informed Dynamic Scheduling Strategies for Iterative LDPC Decoders", IEEE TRANSACTIONS ON COMMUNICATIONS, IEEE SERVICE CENTER, PISCATAWAY, NJ. USA, vol. 61, no. 3, 1 March 2013 (2013-03-01), pages 886 - 896, XP011504983, ISSN: 0090-6778, DOI: 10.1109/TCOMM.2013.012313.120172 * |
LIU MINGSHAN ET AL: "The serial message-passing schedule for LDPC decoding algorithms", PROC., SPIE9817, SEVENTH INTERNATIONAL CONFERENCE ON GRAPHIC AND IMAGE PROCESSING, ICGIP 2015, vol. 9817, 9 December 2015 (2015-12-09), pages 98171E-1 - 98171E-6, XP060062605, ISBN: 978-1-62841-730-2, DOI: 10.1117/12.2228089 * |
See also references of WO2018082290A1 * |
SHARON E ET AL: "An efficient message-passing schedule for LDPC decoding", PROC., 23RD IEEE CONVENTION OF ELECTRICAL AND ELECTRONICS ENGINEERS IN ISRAEL, TEL-AVIV, ISRAEL, 6 September 2004 (2004-09-06) - 7 September 2004 (2004-09-07), pages 223 - 226, XP010743004, ISBN: 978-0-7803-8427-9, DOI: 10.1109/EEEI.2004.1361130 * |
Also Published As
Publication number | Publication date |
---|---|
CN110572163B (zh) | 2020-09-08 |
EP3533146A1 (de) | 2019-09-04 |
JP7152394B2 (ja) | 2022-10-12 |
US20200162107A1 (en) | 2020-05-21 |
KR20190065420A (ko) | 2019-06-11 |
CN110572163A (zh) | 2019-12-13 |
JP2019536341A (ja) | 2019-12-12 |
RU2019116852A (ru) | 2020-12-03 |
US20190260390A1 (en) | 2019-08-22 |
BR112019009090A2 (pt) | 2019-11-12 |
EP4224718A1 (de) | 2023-08-09 |
AU2017355038A1 (en) | 2019-05-16 |
WO2018082290A1 (en) | 2018-05-11 |
RU2019116852A3 (de) | 2020-12-03 |
WO2018084735A1 (en) | 2018-05-11 |
CN109891753A (zh) | 2019-06-14 |
AU2017355038B2 (en) | 2020-09-03 |
US11265014B2 (en) | 2022-03-01 |
US10567002B2 (en) | 2020-02-18 |
KR102155539B1 (ko) | 2020-09-14 |
RU2739465C2 (ru) | 2020-12-24 |
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