EP3149585B1 - Systems and methods for packing data in a scalable memory system protocol - Google Patents

Systems and methods for packing data in a scalable memory system protocol Download PDF

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Publication number
EP3149585B1
EP3149585B1 EP15802720.1A EP15802720A EP3149585B1 EP 3149585 B1 EP3149585 B1 EP 3149585B1 EP 15802720 A EP15802720 A EP 15802720A EP 3149585 B1 EP3149585 B1 EP 3149585B1
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EP
European Patent Office
Prior art keywords
packet
transaction
packets
data
memory
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EP15802720.1A
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German (de)
English (en)
French (fr)
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EP3149585A1 (en
EP3149585A4 (en
Inventor
J. Thomas Pawlowski
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Micron Technology Inc
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Micron Technology Inc
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Definitions

  • US 2014/0112339 discloses a physical layer coupled to a serial, differential link that is to include a number of lanes.
  • the PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes.
  • US 2013/0195210 discloses devices and systems for transmitting data packets over a chip-to-chip communications link.
  • the present disclosure generally relates to scalable memory system protocol. That is, the scalable memory system protocol may adjust certain operations based on characteristics of the data packets (e.g., requests, responses) being transferred.
  • the scalable memory system protocol (“scalable protocol”) may be a packet-based protocol that enables an efficient (e.g., power efficient, bit efficient) transmittal of packets of data between memory devices, computing devices, and the like.
  • the scalable protocol may be implemented in a number of combinations with various types of memory and processors such as Automata processors, a Processor-in-Memory, network devices, storage appliances, hierarchical memory, abstracted memory, and the like.
  • the scalable protocol may be designed to facilitate communication of data packets between various memory and processors while maintaining a lowest reasonable scalable protocol overhead.
  • the scalable protocol may be designed to provide a bit efficient transfer of data packets in that most, if not all, bits transferred via the scalable protocol are directly part of a corresponding data packet being transmitted.
  • the scalable protocol may enable request packets to be packed together without padding a signal with zeros unrelated to the respective packets, thereby maximizing a bit efficiency of data packets being transferred via transmission lanes of a bus.
  • the scalable protocol may, within reason, eliminate certain bits and messages that may be discerned from other bits or messages or may otherwise be unnecessary. For example, the scalable protocol may obviate the need for a device to transmit data related to information that may already be known to the receiver.
  • the scalable protocol may facilitate transactions that are "sent to the memory.”
  • the scalable protocol may also transfer local operations, where internal data flow is relatively low as compared to external control operations, with the external control operations.
  • the scalable protocol may implement an error control strategy that minimizes overhead using a dynamic field size that adjusts based on the amount of data (e.g., payload) being transmitted in the respective packet.
  • the scalable protocol may also be designed to use a minimum number of fields to convey data. As such, the scalable protocol may allow field size tuning and flexibility since every packet may not make use of all available fields.
  • the scalable protocol may also be designed to facilitate the coexistence of low-latency and high-latency data.
  • the scalable protocol may provide the ability to interlace the transmittal of low-latency data between the transmittal high-latency data.
  • the design of the scalable protocol may be characterized as simple and generic in that the variable packet size may be determined in a single field of the respective packet. Further, the scalable protocol may maintain simplicity in terms of its operations while remaining capable of performing complex transactions and operations. In addition, the scalable protocol may be flexible enough to enable future functions that it may not currently be designed to provide.
  • the scalable protocol may limit the order in which packets are sent using local ordering schemes. That is, the scalable protocol may not enforce certain global synchronization ordering rules or the like. To stay true to the notion that the scalable protocol remains abstract, the scalable protocol may facilitate operations with a special device or with different types of channel properties.
  • FIG. 2 depicts a block diagram of an embodiment of the memory device 14.
  • the memory device 14 may include any storage device designed to retain digital data.
  • the memory device 14 may encompass a wide variety of memory components including volatile memory and non-volatile memory.
  • Volatile memory may include Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM).
  • the volatile memory may include a number of memory modules, such as single inline memory modules (SIMMs) or dual inline memory modules (DIMMs).
  • the non-volatile memory may include a read-only memory (ROM), such as an EPROM, and/or flash memory (e.g., NAND) to be used in conjunction with the volatile memory. Additionally, the non-volatile memory may include a high capacity memory such as a tape or disk drive memory. As will be appreciated, the volatile memory or the non-volatile memory may be considered a non-transitory tangible machine-readable medium for storing code (e.g., instructions).
  • ROM read-only memory
  • EPROM e.g., EPROM
  • flash memory e.g., NAND
  • high capacity memory such as a tape or disk drive memory.
  • the volatile memory or the non-volatile memory may be considered a non-transitory tangible machine-readable medium for storing code (e.g., instructions).
  • the memory device 14 may include a system on chip (SoC) 22 that may be any suitable processor, such as a processor-in-memory (PIM) or a computer processor (CPU), tightly coupled to the memory components stored on the memory device 14.
  • SoC 22 may be on the same silicon chip as the memory components of the memory device 14.
  • the memory SoC 22 may manage the manner in which data requests and responses are transmitted and received between the memory components and the host SoC 12.
  • the memory SoC 22 may control the traffic between the memory components to reduce latency and increase bandwidth.
  • the memory device 14 may also include a buffer 23.
  • the buffer 23 may store one or more packets received by the memory SoC 22. Additional details with regard to how the memory SoC 22 may use the buffer 23 will be described below with reference to FIGS. 15-17 .
  • the memory device 14 may include memory types such as NAND memories 24, Reduced-latency Dynamic random access memory (RLDRAM) 26, double data rate fourth generation synchronous dynamic random-access memory (DDR4) 28, and the like.
  • the host SoC 12 and the memory SoC 22 may perform various operations based on computer-executable instructions provided via memory components, registers, and the like.
  • the memory components or storage may be any suitable articles of manufacture that can serve as media to store processor-executable code, data, or the like. These articles of manufacture may represent computer-readable media (i.e., any suitable form of memory or storage) that may store the processor-executable code used by the host SoC 12 or the memory SoC 22 to perform the presently disclosed techniques.
  • the memory and the storage may also be used to store the data, analysis of the data, and the like.
  • the memory and the storage may represent non-transitory computer-readable media (i.e., any suitable form of memory or storage) that may store the processor-executable code used by the host SoC 12 or the memory SoC 22 to perform various techniques described herein. It should be noted that non-transitory merely indicates that the media is tangible and not a signal.
  • the scalable protocol may facilitate communication between any two devices, such as communications between two processors, two memory modules, a processor and a memory module, and the like.
  • the memory SoC 22 may send packets of data structured according to a packet level view of a packet 30 illustrated in FIG. 3 .
  • the packet 30 may include a transaction type field 32, a payload field 34, and an error control code (ECC) field 36.
  • the transaction type field 32 may include data indicative of the type of transmittance, a type of packet being transmitted, or both.
  • the transaction type field 32 may also indicate a packet size to indicate a number of bits in the data payload and the number of bits in the ECC field, thereby indicating the number of bits in the entire packet.
  • the transaction type field 32 may indicate the size of the payload field 34 and the ECC field 36 in an indirect manner.
  • the data stored in the transaction type field 32 may serve as an index to a lookup table.
  • the lookup table may provide information regarding the sizes of the payload field 34 and the ECC field 36.
  • the memory SoC 22 may, in one example, receive the packet 30 and use the data stored in the transaction type field 32 as an index to a lookup table that may be stored within the memory device 14 to determine the sizes of the payload field 34 and the ECC field 36.
  • the transaction type field 32 may specify different types of packets based on whether the packet is being transmitted on a request bus Q or a response bus S, which may include the channels 16, the channels 29, or the like.
  • a request bus Q and the response bus S may be separate, unidirectional, or common inputs/outputs.
  • the request bus Q generally includes q lanes
  • the response bus S generally includes s lanes.
  • Example transaction type fields 32 for packets 30 transmitted on the request bus Q may include read operations (e.g., 8uRead, 8uRead2, varRead, where u might be an 8-bit unit or a 9-bit unit or possibly a non-integer unit size of data), message data (e.g., message), read-modify-write (RMW) operations (e.g., RMW1A, RMW2A, RMW3A, RMW4A), datasets (e.g., 32uData, 64uData, 128uData, 256uData), pattern write operations (e.g., 8uPatternWrite, 16uPatternWrite), write-with-enable operations (e.g., 8uWriteWithEnables, 16uWriteWithEnables), write operations (e.g., 8uWrite, 16uWrite, 32Write, 48uWrite, 64Write, 80uWrite, 96uWrite, 112uWrite, 128Write, 256Write),
  • Providing 32Write operations and 64Write operations may provide more flexibility to a system designer in picking a maximum packet size.
  • the scalable protocol may, in one embodiment, have a limit of 256Unit, but using a smaller maximum packet size may help with system latency. It should be understood that the difference between 32uWrite and 32Write is that 32uWrite is a single fixed size and the TransactionSize is not included in the packet. On the other hand, 32Write includes a TransactionSize and thus can involve additional 32U chunks of data, not just the 32U chunk included in the original request packet.
  • the packets 30 transmitted via the request bus Q may include a total of 26 native transactions (e.g., 8uRead, message, RMW1A, etc.), each of which may be represented using a 5-bit field for global (i.e., system that includes numerous CPU modules and/or numerous memory device modules in which packets may be relayed from unit to unit) or local systems (i.e., system that include few modules in which packets move point to point between units without relaying).
  • the transaction type field 32 for a packet 30 on the request bus Q may be 5 bits.
  • example transaction type fields 32 for packets 30 transmitted on the response bus S may include message data (e.g., message), datasets (e.g., 8uData, 16uData, 32uData, 48uData, 64uData, 80uData, 96uData, 112uData, 128uData, 256uData), and the like.
  • the packets 30 transmitted via the response bus S may include a total of 11 native transactions (e.g., message, 8uData, etc.), each of which may be represented using a 4-bit or 5-bit field for a local system.
  • the transaction type field 32 for a packet 30 on the response bus S may be 4 bits.
  • the total number of transaction types used by the request bus Q and the response bus S may be 32. These 32 transaction types may thus be represented in a 5-bit field. Additional details regarding the transaction types will be discussed further below.
  • the ECC field 36 may include the error control code to determine whether the packet 30 received by the receiving component includes any errors.
  • the error control code may include various algorithms, such as adding redundant data or parity data, to a message, such that the original data may be recovered by the receiving component even when a number of errors were introduced, either during the process of transmission, or on storage.
  • the error control code may provide the ability to detect an error within the limits of the code and indicate a further action, such as retransmitting the errant packet, when the error is detected.
  • the scalable protocol may be employed in a system having one or more request bus Q transactions and one or more response bus S transactions.
  • request bus Q and the response bus S has been described above as having a 5-bit field and a 4-bit field, respectively, it should be noted that the request bus Q and the response bus S may be designed to have a variety of different bit sizes.
  • request bus Q transactions may be indicated using a 5-bit field (e.g., 00000, 00001, ..., 11110, 11111), such that possible transaction types that may be associated with the 5-bit field as follows (where data unit u size is 8 bits):
  • the packet 30 may include the ECC field 36, which may be a fixed size as in conventional protocols. However, as will be appreciated, in certain embodiments, the ECC field 36 may be a variable size as will be discussed in greater detail below.
  • the example response bus S transactions above are listed in order of the ensuing packet size assuming a 5-bit transaction type on the request bus Q, a 4-bit transaction type on response bus S, a 4-bit transaction size, a 3-bit window, a 48-bit address, a 7-bit data sequence number, and extra bits in the data field which are stated specifically for each transaction type.
  • the transaction window may provide information related to a certain set of rules of engagement for each particular transaction.
  • the transaction window data may specify a set of lanes of a physical bus (e.g., channels 29) being used to transmit and receive packets for particular transactions.
  • the set of lanes specified by the transaction window may be referred to as a virtual channel accessible to the memory device 14.
  • the channels 29 described herein includes one or more lanes in which data may be transferred.
  • the scalable protocol may better manage the transmission of packets between processors.
  • the scalable protocol may designate a transaction window for each memory device.
  • the scalable protocol may use two fields to designate each transaction window: a 48-bit Address and a 3-bit Window (i.e., addressing Windows 0 through 7).
  • a transaction window field 42 and an address window field 44 may be part of the payload field 34.
  • the transaction window field 42 may specify a designated transaction window and the address window field 44 may specify the 48-bit address associated with the specified transaction window.
  • the 48-bit address may be a virtual address assigned to a virtual channel (i.e., window).
  • the virtual address space may reference a physical address located on a hard disk drive or some other storage device. As such, the memory device may have the ability to store more data than physically available.
  • the packet may include a start bit 46 and a level of indirection field 48.
  • the start bit 46 may indicate the beginning of a packet in a stream of bits.
  • the level of indirection field 48 may be part of the payload field 34 and may provide a value that indicates a number of levels of indirection the respective transaction may include. Additional details regarding the start bit field 46 and the level of indirection field 48 will be discussed in greater detail in other sections below.
  • each type of memory device may be assigned to a different transaction window.
  • DRAM0 may be assigned into Window0
  • DRAM1 into Window1
  • DRAM2 into Window2
  • NAND0 into Window3
  • SRAM buffers and control registers into Window7.
  • transactions 1, 3-6, 8, and 9 are part of Window0, which corresponds to a DRAM memory device.
  • Transactions 2 and 7, on the other hand, are part of Window3, which corresponds to a NAND memory device.
  • the receiving component may respond to the received requests using ordering rules established according to the respective transaction windows specified for each transaction. As such, the receiving component may use the transaction windows to provide a local ordering protocol between the transmitting component and the receiving component.
  • the ordering rules specified for a particular transaction window may be based on the respective latency associated with the respective transaction window. That is, the receiving component may respond to the requests involving lower latencies first before responding to the requests having longer latencies. Since the receiving component may be aware of the latency differences between each transaction window, the receiving component may decide to receive the transactions according to their window designations. As such, referring again to the example transactions described above, the receiving component implementing the scalable protocol may respond to the above requests as follows:
  • the receiving component may first respond to the low-latency requests of Window0 before responding to the higher latency requests of Window3. That is, the long latency requests may be transmitted later than the short latency requests.
  • the system bus servicing the requests is not hampered by the presence of different classes of memory on the same bus without adding various elaborate protocol complications, such as adding a field with REQUEST PRIORITY.
  • the scalable protocol provides a complex system operation using a minimal number of bits in a relatively simple manner.
  • the receiving component may employ a local ordering scheme based on a corresponding transaction window specified for each transaction. For the following transaction:
  • Another feature associated with the transaction window includes a simple system-level addressability of other spaces such as Window0 SRAM and system control registers without creating additional commands in the protocol. That is, SRAM and system control registers may be addressed by simply using Window0.
  • Prior protocols may use additional commands such as register.read and register.write to interact with these types of memories.
  • the same read and write commands used for other memory devices may also be used for SRAM and system control registers. That is, the read and write commands may simply point to an appropriate window.
  • the scalable protocol may employ fewer commands, thereby reducing the number of bits used in the protocol.
  • a typical DDR3 DRAM may include eight banks, and an internal bus may include eight such DRAMs.
  • the eight DRAMS may be organized such that Window1 represents bank 0 of a group of eight DDR3 DRAMs and Window2 provides access to bank 1 of this same group.
  • each window may specify a particular virtual address space of each DRAM.
  • suitable grouping methods are available since there could be any number of DRAMs grouped in a lock-step operation, each with pages, banks and ranks.
  • NANDs may also be grouped with pages, planes, and blocks.
  • multichannel devices can be further separated per channel and various aggregations thereof. Generally, the grouping options may be determined based on a complexity of logic chip design.
  • the scalable protocol may use the transaction windows to establish predictable data ordering in a system that contains memories that have different latencies.
  • the scalable protocol may support high and low priority requests without having an explicit protocol field that specified how the high and low priority requests are ordered.
  • FIG. 5 illustrates a flow chart of a method 50 for assigning transaction windows for various types of memories that are part of the memory device 14.
  • the method 50 is depicted in a particular order, it should be noted that the method 50 may be performed in any suitable order, and thus, is not limited to the order depicted in the figure. Additionally, the following description of the method 50 will be described as being performed by the memory SoC 22 for discussion purposes. As such, any suitable processor that is communicatively coupled to various types of memories may perform the operations described in the method 50.
  • the memory SoC 22 may receive an initialization signal from registers or other memory components stored within the memory SoC 22 itself.
  • the initialization signal may be received by the memory SoC 22 upon power up or when the memory device 14 initially receives power.
  • the memory SoC 22 may determine the memory types that it may be able to access. That is, the memory SoC 22 may scan its communication lanes (e.g., channels 29) and identify the different types of memories that may be communicatively coupled to the memory SoC 22. Referring back to the example memory device 14 depicted in FIG. 2 , the memory SoC 22 may determine that the RLDRAM 26, the DDR4 28, and the NAND 24 memory types are coupled to the memory SoC 22.
  • the memory SoC 22 may determine that the RLDRAM 26, the DDR4 28, and the NAND 24 memory types are coupled to the memory SoC 22.
  • the memory SoC 22 may, at block 58, assign a transaction window to each memory type identified at block 54 based on the respective capabilities of each memory type. Generally, the memory SoC 22 may assign each similar memory type to the same transaction window. That is, since each similar memory type has similar capabilities, the memory SoC 22 may assign the memory type to the same transaction window. For example, referring again to the example memory device 14 of FIG. 2 , the memory SoC 22 may assign the two DDR4 28 memories to the same transaction window because they are identical memory types. In the same manner, if two different memory types have a certain number of similar capabilities, the memory SoC 22 may also assign the two memory types to the same transaction window.
  • the scalable protocol may include other optional fields into the packet 30 to condition a request, such as a read, write, move, read-modify-write, and the like.
  • a condition may include indicating a number of levels of indirection to apply to a request.
  • the requesting component may initially send a request for the particular dataset with a first pointer.
  • the requesting component may receive the second pointer.
  • the requesting component may then send a second request for the particular dataset with the second pointer. This process may continue until the requesting component receives the particular dataset.
  • the traffic on the request bus Q may involve multiple requests before actually receiving the dataset requested by one single initial request.
  • the scalable protocol may specify within a design of an application-specific integrated circuit (ASIC), the memory SoC 22, the host SoC 12, or the like that implements the scalable protocol an indication of a number of pointers that the requesting component may receive before actually receiving the requested data.
  • ASIC application-specific integrated circuit
  • the memory system implementing the scalable protocol may identify the pointer chain between the original request and the location of the data and may service the request to the requested data based on the initial request from the requesting component. That is, one request, involving any number of levels of indirection from the requesting component may result in receiving just one response that includes the requested data.
  • Binary 11 may indicate 3 levels of indirection. As such, the supplied address may point to Address2, which may point to Address3, which may point to Address4, which may include the data content.
  • the memory system implementing the scalable protocol may provide the data content to the requesting component as the result of the read request.
  • the number of bits (e.g., size) used by the level of indirection field 48 may be determined based on a preference provided by the host SoC 12. For instance, upon power up, the host SoC 12 may discover the memory SoC 22 and determine that the memory SoC 22 is operating using the scalable protocol described herein. As such, the host SoC 12 may determine a maximum number of levels of indirection that it may be able to accommodate without compromising its performance. The maximum number of levels of indirection may be determined based on the write and/or read latencies of the host SoC 12 or other operating parameters of the host SoC 12.
  • the memory SoC 22 may determine the cause for the packet 30 to be transmitted. As such, the memory SoC 22 may determine what software command was used for the transfer of the packet 30.
  • the software command that generates the packet may correspond to a command to look up a pointer of a pointer, for example.
  • the memory SoC 22 may interpret this command as having two levels of indirection and thus may provide a 10 binary value in the level of indirection field 48 when preparing the packet 30 for transmission.
  • the levels of indirection may be useful for various types of operations.
  • arrays of arbitrary dimensions may use levels of indirection to assist requesting components identify the content of their respective requests without adding unnecessary traffic to the respective bus.
  • a 3-dimensional array may use three pointers to access data. Records of some defined structures may use pointers.
  • One example of such a record may include link lists that have a head and tail pointer for every structure in the list. For linked lists, the abstraction of levels of indirection may enable the parsing of the link list to occur more efficiently.
  • the memory system may retrieve the requested data or the 8th element of the list using the single request provided by the requesting component.
  • the memory system may parse each of the 8 levels of indirection to determine the location of the requested data.
  • the memory system may provide the requesting component the requested data, thus limiting the bus traffic to one request from the requesting component and one response from the location of the requested data.
  • Another technique for reducing bus traffic may include not acknowledging received packets. That is, in conventional protocols, each packet that has been received by a recipient component may send an acknowledgment packet back to the transmitting component. Since the vast majority of transmitted packets are received by the corresponding recipient component, sending acknowledgment packets may add to the traffic on the respective bus without providing much of a benefit.
  • the recipient component may transmit an acknowledge bit indicating success for 1x1010 packets and 1 packet indicating an error. Effectively, the recipient component may have sent about 1x1010 bits to indicate one error.
  • BER Bit Error Rate
  • the request bus Q upon receiving each packet of the data, the request bus Q does not send an acknowledgement packet indicating that the packet was received successfully.
  • the response bus S may include two stages for the operations. That is, the response bus S may indicate that the message is ready and then the response bus S may send the corresponding data related to the read request.
  • the recipient component may still receive packets that have errors. As such, the recipient component may notify the transmitting component that the packet has not been received or that the received packet contains an error by sending a NOT_ACKNOWLEDGE packet to the transmitting component. In addition to indicating that the sent packet has not been received, the NOT_ACKNOWLEDGE packet may indicate a most recent known-to-be-good bus transaction. As such, when an error is detected via an ECC subsystem, the packet having the error should be re-transmitted. The recipient component may identity the transmitting component of the most recent successful bus transaction as a reference to so that a retransmission can occur.
  • the scalable protocol may use 4 relevant fields to indicate to a transmitting component the identity of the last known-to-be-good bus transaction.
  • the relevant fields include a window, an address, a transaction, and an optional data sequence number. These four fields may identify any request/response in the system.
  • an additional ECC field may be used to detect an error in the transmission (e.g., a code which is guaranteed to detect the presence of 1, 2, 3, 4, or 5 random errors in the transmission packet, also known as an HD6 code, as will be described in more detail below).
  • the recipient component may send a NOT_ACKNOWLEDGE message to the transmitting component.
  • the size of this packet may be many possible field sizes.
  • the NOT ACKNOWLEDGE message may be a 4-bit transaction type, a 3-bit window, a 48-bit address, a 7-bit data sequence number, and a 5-bit original transaction type for a sum of 67 bits.
  • a 15-bit ECC field may be added, thereby bringing the total to 82 bits.
  • 82 bits is significantly lower than the 1x1010 bits sent for indicating one error in 1x1010 packets, and thus is a more efficient way to indicate address error packets.
  • the data sequence number mentioned above may identify the erroneous packet. Additional details regarding the data sequence number and how it may be generated will be discussed below with reference to FIGS. 12-14 .
  • the recipient component may accurately indicate to the transmitting component the correct point at which a retransmission may occur.
  • the recipient component may incorporate one exception for the above rule when there has been no good transaction (e.g., the first transaction since power-on or reset was unsuccessful). In this case, the recipient component may populate all fields with 0's, such that all elements of the system will interpret the field of 0's as a "first transaction.”
  • the scalable protocol may include an optional data sequence number field.
  • the optional data sequence number field may include 7 bits that reference any one of these 128 data packets. In this manner, if a NOT_ACKNOWLEDGE message is issued, the NOT _ACKNOWLEDGE message may correctly identify an exact point at which the transmission became unsuccessful.
  • the minimum TransactionSize of 8B, for TransactionSize 0 through 15, may be 8 bytes, 16 bytes, 32 bytes, 48 bytes, 64 bytes, 80 bytes, 96 bytes, 112 bytes, and 128 bytes, as opposed to 2 N bytes to conserve bits on the lower end.
  • the scalable protocol may employ data packing techniques when transmitting packets using any type of bus communication.
  • packet sizes are determined based on the type of request or response being sent, the data being sent, the operations being requested, etc., it may be difficult to anticipate what type of data channels to use before knowing more details regarding the packet.
  • the scalable protocol may be designed to maximize the use of the available channels by packing the data packets being transmitted together without padding each individual packet with zeros, as done with conventional protocols.
  • the term "without padding" means that between the transmission of data packets, zeros (i.e., bits having the value of zero) are not transmitted across a respective channel. Instead, the next scheduled packet ready to be transmitted will be transmitted on the clock cycle immediately after the previous packet is transmitted.
  • a request bus Q that includes 10 signal lanes and a response bus S that includes 8 signal lanes.
  • the present example assumes that there is no data encoding and that the transactions include only simple bit transmissions (i.e., no symbol transmissions). If the sizes of occupancy on the Q bus are: 4.3, 7.3, 9.7, 13.5, 14.3, 14.9, 20.0, 20.1, 21.6, 33.0, 36.2, 58.8, 65.2, 105.4, 110.5, and 123.0, a conventional protocol may pad the values having fractional components associated with them.
  • the conventional protocol may add zeros to the remaining portion of each fractional value such that the sizes of occupancy on the Q bus become 5, 8, 10, 14, 15, 15, 20, 21, 22, 33, 37, 59, 66, 106, 111, and 123, respectively.
  • zeros may be added to the transmission, which may adversely impact an overall bus utilization efficiency because the transmitted zeros are not truly representative of data being transmitted. In this manner, these zeros utilize the bus without conveying information, thereby reducing the bus utilization efficiency.
  • the scalable protocol may allow requests to be packed together.
  • the bus signal is thus left without padded zeros.
  • FIG. 8 illustrates a lane packing example 61 in which the scalable protocol packs two 18-bit requests together.
  • the scalable protocol may regard transmissions as symbols instead of bits. In the example of FIG. 8 , one bit may represent one symbol. Since the bus 62 in FIG. 8 includes 12 lanes (i.e. may transmit 12 bits in one flit), the scalable protocol may transmit the two 18-bit requests by packing the requests together. That is, a second 18-bit request 66 may be transmitted immediately after a first 18-bit request 64. As such, the transmission bus includes no wasted bits (e.g., padded zeros).
  • the transmitting component may start each new packet 30 with a start bit, which may be specified in the start bit field 46, as mentioned above.
  • a start bit e.g., value of 1
  • a receiving component when it receives the packets packed together, it may identify the beginning of each new packet, determine the transaction type of the packet based on the transaction type field 32, the transaction window based on the transaction window field 42, the address for the operation based on the address field 44, the number of levels of indirection based on the level of indirection field 48, and the error checking code based on the ECC field 36.
  • FIG. 9 illustrates a flow chart of a method 70 for generating a packet for transmission, such that the packet can be transmitted using the lane-packing scheme described above.
  • the following description of the method 70 will be discussed as being performed by the memory SoC 22 (i.e., transmitting/requesting component), but it should be understood that any processor that is part of the memory device 14 may perform the operations described in the method 70.
  • the memory SoC 22 may determine a transaction window based on the memory type associated with the requested data operation. That is, the memory SoC 22 may determine what type of memory will be accessed when performing the data operation and determine a corresponding transaction window based on the type of memory using a look-up table or the like. In addition to the transaction window, the memory SoC 22 may determine a memory address that refers to a location of data related to the data operation and the transaction window. For example, for a read operation, the address may refer to the location of the data that is to be read from a specified memory.
  • the memory SoC 22 may generate an error control code (ECC) value for the packet 30.
  • ECC error control code
  • the ECC value may be used by the receiving component to ensure that the packet 30 is received without error.
  • the memory SoC 22 may first determine an appropriate error control code (ECC) algorithm to use to encode the packet 30.
  • the software application requesting the transmission may specify the ECC to algorithm use.
  • the host SoC 12 or the memory SoC 22 may specify a particular ECC algorithm to use to encode and decode all of the transmitted and received packets.
  • the ECC value for the packet 30 may be determined based on the bits provided in the transaction type field 32 and the payload field 34.
  • the memory SoC 22 may, at block 82, generate the packet 30 according to the values determined at blocks 72, 74, 76, and 80.
  • the memory SoC 22 may initially provide a 1 for the start bit field 46 to indicate to a receiving component that a new packet is being transmitted. After inserting the 1 in the start bit field 46, the memory SoC 22 may provide a value that represents the transaction type identified at 74 in the transaction type field 32.
  • the memory SoC 22 may then generate the payload field 34 of the packet 30 using the transaction window and address determined at block 76 and the number of levels of indirection determined at block 78. That is, the memory SoC 22 may enter the transaction window value after the transaction type field 32 and into the transaction window field 42. The memory SoC 22 may then enter the address for the data operation into the address field 44 and the number of levels of indirection into the level of indirection field 48.
  • the memory SoC 22 may, at block 84, transmit the packet 30 via the channels 16, the channels 29, or the like depending on the destination of the packet 30. After the generated packet 30 is transmitted, the memory SoC 22 may proceed to block 86 and determine whether the next packet to be transmitted is ready for transmission. Generally, the next packet for transmission may be generated according to the process described above with regard to blocks 72-82. If the next packet is ready for transmission, the memory SoC 22 may proceed to block 84 again and transmit the next packet immediately after the previous packet is transmitted. By transmitting each subsequent packet immediately after another packet is transmitted, the memory SoC 22 may transmit packets according to a packed lane scheme, which does not involve padding zeros on a bus when all of the lanes of a bus are not utilized.
  • the number of UIs used to transmit the same packets is respectively 10 (80/8), 10.5 (84/8), 18.125 (145/8), 34.25 (274/8), 50.25 (402/8), 66.375 (531/8), 82.375 (659/8), 98.375 (787/8), 114.375 (915/8), 130.5 (1044/8), and 258.5 (2068/8).
  • the average savings for randomly selected packet sizes is 0.5 UI per transaction, hence the bit savings grows as the number of lanes is increased.
  • This example is indicative of any width of the request bus Q or the response bus S, whether they are equal or unequal widths on the two buses.
  • the host SoC 12 or any other receiver may use the following transmission/receiving scheme: receive the packet 30, parse contents of the packet 30 to identify the transaction type, size of the payload, and a location of the ECC field 36 within the packet 30, verify a correctness of the packet 30 based on the ECC, and then act upon the transmission with certitude.
  • the scalable protocol may be designed to facilitate a maximum bit efficiency.
  • the packet 30 may have an arbitrary size that does not correspond to an integer multiple of the utilized physical bus.
  • the transmission of arbitrarily sized packets maintains bit efficiency by packing the packets tightly together, such that each succeeding packet is transmitted immediately after the preceding packet without padding either packet with zeros.
  • the receiver e.g., host SoC 12
  • the receiver may implement certain techniques described herein for parsing the received packets.
  • the scalable protocol may specify a parsing method for the receiver to employ on received packets. This parsing method may include shift operations, error detection, and buffer management as pipelined operations at the head of the logical operations utilized in a system implementation.
  • one flit is considered to be one unit interval of data being present on a bus. That is, one flit may include 8 bits of data being transferred via the bus.
  • the smallest packet with Address 36b, Window 3b, and Hamming Density (HD6) error coverage of 59 bits may include a 5-bit Transaction Type, a 41-bit data payload, and a 13-bit ECC.
  • the receiver may first receive the 160-bit value immediately available from the FIFO. In the particular example described above, the entire first packet resides within that 160-bit zone.
  • the receiver may then know with certainty that the transaction type value was correct and hence the receiver may have the proper framing of the received packet.
  • the 59 known-to-be-correct bits may then be forwarded to the next pipeline stage for further packet processing (i.e., determine the exact request being made and process the request.)
  • the receiver may then barrel-shift the remaining 101 bits of the 160-bit wide FIFO to align to bit 0 and repeat the above process.
  • the receiver may have too little data available to parse (i.e., everything from transaction type field 32, through payload field 34, and ECC field 36 should be available).
  • the receiver may continue fetching information until it is all available.
  • large packets may exceed a single 160-bit section, since the receiver knows where ECC starts and ends from the transaction type, the receiver may forward the ECC bits to the appropriate ECC logical blocks.
  • the receiver since the transaction type is at the head of the packet, the receiver easily knows to look for it. Further, the receiver may determine that the payload field 34 includes everything between the transaction type field 32 and the ECC field 36. Upon identifying the payload field 34, the receiver may send the data payload to appropriate ECC logical blocks.
  • the ECC logic may be implemented in situ at register bits that temporarily store the data, depending on physical layout optimization uses.
  • FIG. 11 illustrates a flow chart of a method 100 that may be employed by a receiving component (e.g., host SoC 12) that receives packets according to the lane-packing scheme mentioned above.
  • a receiving component e.g., host SoC 12
  • the method 100 may be performed by any suitable receiving component that receives packets that have been lane packed according to the embodiments described herein.
  • the host SoC 12 may receive a stream of bits via the bus 62, the channels 16, or the like. As depicted in FIG. 10 , the host SoC 12 may receive a number of bits at a time based on the number of bit lanes available on the bus 62.
  • the host SoC 12 may identify a start bit of a new packet. As such, the host SoC 12 may monitor the stream of bits until it recieves a 1. For example, at bit time 0, the host SoC 12 may detect the start bit and begin parsing the first packet 92.
  • the host SoC 12 may determine whether the respective packet is free of errors. If the host SoC 12 verifies that the respective packet is error free, the host SoC 12 returns to block 102 and continues receiving the stream of bits. However, if the host SoC 12 determines that the respective packet is not error free, the host SoC 12 may proceed to block 114 and send a NOT_ACKNOWLEDGE packet back to the component that transmitted the respective packet. As discussed above, the NOT_ACKNOWLEDGE packet may indicate a most recent known-to-be-good bus transaction. As such, the NOT_ACKNOWLEDGE packet may indicate the transaction type and the address of the last successfully received packet. Since the transmitting component knows the order in which each packet was transmitted, the transmitting packet may then resend the packet immediately following the packet referenced in the NOT ACKNOWLEDGE packet.
  • the transmitting component may not disregard, delete, erase, or write over sent packets from its buffer until a certain amount of time has passed after a respective packet has been transmitted.
  • the transmitting component e.g., memory SoC 22
  • the transmitting component may wait a certain amount of time before it deletes the transmitted packet from its buffer component.
  • Some of the factors involved in determining the expected time for the various operations described above to be performed include the size of the packet being transmitted, the number of lanes on the request bus Q and the response bus S, an amount of time for a UI of data to be transmitted across each bus, a number of pipeline delays that are expected in the receiving component before the receiving component verifies that the received packet is error free, a maximum depth of queues in the transmitting component, information related to a policy of the transmitting component for sending urgent messages (e.g., are urgent messages placed in the front of the queue), and the like. It should be noted that the factors listed above are provided as examples and do not limit the scope of the factors that may be used to determine the expected time for the various operations to be performed.
  • the transaction windows may be used to indicate an order for a given transaction window, in some instances, performing the transaction operations according to the order of the respective transaction windows may be undesirable.
  • a DRAM might involve a refresh operation, which cannot be postponed by other DRAM operations.
  • Another example may include when a NAND memory may be shuffling data to prepare for an erase operation.
  • a range of addresses associated with the data being shuffled may be temporarily unavailable if a transaction operation is trying to access the same range of addresses.
  • the receiving component may send a data reorder message when it is desirable to depart from the natural response sequence.
  • the receiving component may determine that reordering may be preferred based on the transaction type indicated in the transaction type field 32. That is, the transaction type field 32 may inherently indicate that a reordering is preferred.
  • the transaction type field 32 may be a 64 bit message that includes 16 x 4-bit order identifiers. These identifiers may indicate the order of the next 16 responses, if there are 16 responses pending.
  • the reorder message may be sent any time that a new ordering is preferred.
  • a new reorder message may be sent.
  • the very next response would be response 0, not response 8, because an order counter is reset to zero any time a reorder message is sent.
  • the new relative order of 0 through 15 may be determined according to the most advantageous ordering.
  • all data may be in a "natural" order of the requests received per window.
  • the scalable protocol may save a large amount of overhead that is otherwise used in conventional protocols.
  • the host SoC 12 may receive a number of packets from the transmitting component (e.g., memory SoC 22).
  • the received packets may generally include operations requested to be performed by the host SoC 12 in a preferred order.
  • the transmitting component e.g., memory SoC 22
  • the transmitting component may send packets that correspond to data operations in a particular order, which may reflect a preferred order of operations.
  • the diagram 140 of FIG. 13 illustrates an example original order of packets received by the host SoC 12 in row 142. As shown in FIG. 13 , ten packets transmitted by the transmitting component may be initially numbered 1-10.
  • the host SoC 12 may determine whether the operations indicated in the received packets should be performed in a different order. That is, for example, if the host SoC 12 is unable to perform a particular operation for some reason (e.g., requested memory address is busy, unavailable, etc.), the host SoC 12 may instead perform a later operation before performing the previously requested operation. If the host SoC 12 determines that the operations should not be performed in a different order, the host SoC 12 may proceed to block 126 and perform the operations of the received packets in the preferred order (e.g., as transmitted by the transmitting component).
  • the preferred order e.g., as transmitted by the transmitting component
  • the host SoC 22 may determine a new order to perform the requested operations. To perform operations in a different order, the host SoC 12 may identify a particular packet that corresponds to an operation that may not be performed in the requested order. The host SoC 12 may then determine whether any subsequent operation is dependent on the results of the identified operation. That is, the host SoC 12 may determine whether performing the identified operation at a later time may cause an error in any remaining operations to be performed. In certain embodiments, the host SoC 12 may evaluate the transaction windows of each packet to determine whether operations may be reordered.
  • the host SoC 12 may delay the third Win2 request to perform the first Win3 request because they refer to different transaction windows and thus likely operate on different memory types. Using the transaction windows of each packet, the host SoC 12 may then determine a new order to perform the requested operations.
  • the host SoC 12 may rename a number of packets that are received after a packet immediately preceding the packet that corresponds with the identified operation. In one embodiment, the host SoC 12 may rename the packets according to their current position in the queue. For instance, referring again to FIG. 13 , if the host SoC 12 identifies original packet 5 as a packet containing an operation that should be performed at a later time, the host SoC 12 may rename the packets after packet 4 according to their current position in the queue. As such, packets 5-10 may be renamed to packets 0-5 as illustrated in row 144 of the diagram 140. In this manner, the remaining packets may be renamed according to their relative position in the queue.
  • the host SoC 12 may generate a reorder message that indicates a new order in which the remaining packets will be addressed by the host SoC 12 or according to the order of corresponding operations that will be performed by the host SoC 12.
  • the reorder message may be determined based on the new order determined at block 128 and according to the renamed packets, as provided in block 130. For instance, referring to the example in FIG. 13 again, if the host SoC 12 determined that the original 5 th packet operation should be performed after the original 7 th packet operation, the reorder message may be presented as 1, 2, 3, 0, 4, 5, as shown in row 146. Row 146 indicates the new order of operation according to the renamed packets. For illustrative purposes, row 148 indicates the order in which the reorder message specifies that the remaining packet operations will be according to their original packet numbers.
  • the host SoC 12 may transmit the reorder message to the transmitting component.
  • the transmitting component may use the reorder message to adjust the order in which the response packets transmitted from the host SoC 12 are associated with a respective request packet. That is, the transmitting component may associate each response packet received after the reorder message according to the renamed relative order indicated in the reorder message.
  • the host SoC 12 may provide a reference order to the transmitting component that is relative to the remaining response packets that are to be received by the transmitting component. As such, since the host SoC 12 and the transmitting component may know the order in which packets have already been sent, the packets renamed according to their relative order enables the host SoC 12 to associate the response packets without having to send a packet identification number with each packet, thereby providing a more bit-efficient communication scheme.
  • the scalable protocol may determine the order in which transaction operations are performed, as follows. If there are 4 request buses associated with 4 respective response buses, an associated pair of request and response buses may be named by the scalable protocol as a channel. As such, in one embodiment, a transaction operation may be defined as "channel.window.address.” Here, the ordering may then be defined as "channel.window.dataSequenceNumber.” Often times, just one datum may be part of the transaction operation, such that the data sequence number is often unimportant to save for transaction requests larger than a largest supported packet size. Otherwise, the scalable protocol may follow an ordering within the channel.window. Even when two channels are using the same window, the scalable protocol may not incorporate any ordering between them.
  • the scalable protocol may provide an order within each channel.window combination.
  • the scalable protocol may greatly simplify the operation of the system because channels have the possibility of asynchronous timing inter-relationships.
  • the scalable protocol keeps the ordering simple and also reduces a number of times arbitration may be performed.
  • this ordering technique may also reduce a number of reorder messages that have otherwise been sent.
  • scalable protocol has been described as being capable of providing a new relative order for transaction operations being sent, it may be difficult to incorporate this type of reordering scheme in large systems that may have a high frequency of reordering requests. That is, if reorder messages are sent at some high frequency (i.e., above a certain threshold), it may no longer be an efficient use of time and resources to send reorder messages and reorder the transaction operations. In other words, for some types of systems the frequency of data reordering could become so high that the amount of communications between the transmitting component and the receiving component may become inefficient. For such systems, the scalable protocol may reduce bit traffic of transaction identifications even when large numbers of reorder events are preferred.
  • the request bus Q sequence number may be denoted as "channel.window.Qseq,” such that Qseq may be assigned in round robin order for each respective channel and respective window, thereby preserving bandwidth by not transmitting known data. For instance, if an order of requests (all on channel 0) is as follows: Win2, Win2, Win2, Win3, Win3, Win2, and Win3 and these are the first transactions, the assigned Qseq numbers appended by the receiver would be: 0, 1, 2, 0, 1, 3, and 2 respectively. That is, each window may be associated with a round robin Qseq sequence based on the receipt of each type (i.e., channel/window) of request.
  • the host SoC 12 may determine whether a number of reordering messages transmitted to the transmitting component over some period of time exceeds some threshold.
  • the threshold may be related to a declining performance of the memory device 14, an average number of cycles involved when performing an operation, an average queue depth for each requested operation, or the like.
  • the host SoC 12 may continue sending reorder messages according to the method 120 described above. However, if the host SoC 12 determines that the number of reordering requests is greater than the threshold, the host SoC 12 may proceed to block 164. At block 164, the host SoC 12 may add a sequence value to each received packet in a round robin fashion according to the transaction window of each packet.
  • the transmitting component may store an order in which each packet has been transmitted, such that the order of transmission may correspond to the order in which each packet was received.
  • the receiving component may use a request bus Q sequence number (Qseq) and a data sequence number (DataSequence) to identify each packet when an error occurred and the pipeline may be flushed and the corresponding packets within the pipeline may be resent. For instance, if the error occurred in a packet on the response bus S, a last known-to-be-good packet received by the transmitting component may include a Qseq number in it to use as reference. As a result of employing this technique, some of the messages are actually now shorter since a transaction type is not referenced to indicate a transaction.
  • Qseq request bus Q sequence number
  • DataSequence data sequence number
  • the presently disclosed technique to reorder transaction operations for transaction operations that are reordered at a high frequency, or designed as such may still be economical as compared with conventional protocols, which may add 16 bits to every response.
  • the scalable protocol since the presently disclosed technique includes a sequence number for each response, the scalable protocol may not issue reorder messages or packets. Further, since each transaction operation is associated with a particular sequence number, the transaction operation may be transmitted in a round robin order to ensure that known data is not transmitted.
  • the scalable protocol may provide a flexible programming option for ordering transaction operations or packets in a system.
  • the flexible programming option e.g., ordering effort field
  • the flexible programming option may set a degree of effort that the scalable protocol should use in maintaining the original order of transactions. That is, the flexible ordering effort field may indicate to the scalable protocol how hard it should work to ensure that the packets are transmitted in order.
  • the flexible ordering effort field may be associated with a range of values between a first value that corresponds to keeping every pack in order and a second value that corresponds to allowing anything to be reordered.
  • transaction window 0 may be used as a general purpose control area for memory SoC 22.
  • transaction window 0 may reside in registers, SRAM buffers, cache SRAM, and other addressable control features.
  • the scalable protocol may enable configurable information that can be user programmed.
  • one type of the configurable information e.g., ordering effort field
  • ordering effort field may have a large variation in implementations. For instance, in a 2-bit field, the ordering effort may be characterized as follows:
  • the ordering zone may be related to a combination of a channel, a system window, and a transaction window (e.g., channel.syswin.window).
  • Channel may be a channel number from which the request was received.
  • System window may be an optional pair of fields that, for example, specifies which SoC in the system originated the request.
  • the host SoC 12 may monitor the capacity of the buffer 23 and determine whether the capacity of the buffer 23 of the receiver is less than or equal to some threshold. If the capacity of the buffer 23 is above the threshold, the host SoC 12 may proceed to block 184 and continue receiving packets at the present transmission rate from the transmitting component.
  • the windowMax field may not be relevant or may be considered to be equal to the channelMax field.
  • different backpressure functions may be defined for each respective transaction window. For instance, consider the following 4 examples of transaction windows that use a variety of different memory types as described below.
  • the receiving component may include a system failsafe mechanism to indicate to the transmitting component that the buffer 23 is about to be overrun or exceed its capacity.
  • the receiving component may send a message similar to the not3-acknowledged message described above. This message may have the same effect as the not-acknowledged message except that it may create an entry in a data log of the transmitting component to note that a message was rejected due to the buffer 23 being unable to accept the packet.
  • the transmitting component may determine a reason for the delay in bus traffic.

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US20150347019A1 (en) 2015-12-03
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