CN106471460B - 用于在存储器系统中分割数据结构的系统及方法 - Google Patents

用于在存储器系统中分割数据结构的系统及方法 Download PDF

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CN106471460B
CN106471460B CN201580035967.6A CN201580035967A CN106471460B CN 106471460 B CN106471460 B CN 106471460B CN 201580035967 A CN201580035967 A CN 201580035967A CN 106471460 B CN106471460 B CN 106471460B
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memory
memory assembly
library
virtual library
assembly
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CN106471460A (zh
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J·托马斯·帕夫洛夫斯基
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Micron Technology Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0617—Improving the reliability of storage systems in relation to availability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1867—Arrangements specially adapted for the transmitter end
    • H04L1/189—Transmission or retransmission of more than one copy of a message
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/25—Flow control; Congestion control with rate being modified by the source upon detecting a change of network conditions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/52—Queue scheduling by attributing bandwidth to queues
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Security & Cryptography (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Dram (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)

Abstract

本发明涉及一种存储器装置(14)，其可包含存储数据的存储器组件(24、26、28)及处理器(22)。所述处理器(22)可基于与所述存储器组件(24、26、28)相关联的一或多个性质及所述存储器组件(24、26、28)的预期随机存取速率而在所述存储器组件(24、26、28)中映射一或多个库(35)或一或多个虚拟库(36)。

Description

用于在存储器系统中分割数据结构的系统及方法
相关申请案的交叉参考
本申请案是主张2014年6月2日申请的标题为“用于可扩展存储器系统协议的系统及方法(Systems and Methods for a Scalable Memory System Protocol)”的第62/006,668号美国临时专利申请案的优先权的非临时申请案，所述美国临时专利申请案以引用的方式并入本文中。
技术领域
本发明大体上涉及一种用于改进可使用存储器装置执行数据操作(例如，读取、写入)的速率的存储器系统。更具体来说，本发明涉及用于改进存储器系统响应于对存储器系统进行存取的请求的速率的系统及技术。
背景技术
本章节希望向读者介绍可能与本发明的各种方面相关的本领域的各种方面，所述方面在下文中描述及/或主张。据信，此论述有助于为读者提供背景信息以促进更好地理解本发明的各种方面。因此，应理解，这些陈述应在此背景下阅读且并非作为现有技术的认可。
通常，低能力(例如，低请求速率)存储器类型(例如动态随机存取存储器(DRAM)组件)与高能力(例如，高请求速率)存储器(例如静态随机存取存储器(SRAM)组件)相比可能相对廉价。因而，可基于存储器类型的相应能力对特定存储器类型执行特定数据操作(例如，读取、写入)。例如，对于涉及多个动作的大型复杂数据操作，使用SRAM组件来保证与在使用DRAM组件执行相同数据操作时相比，数据操作被更快速地执行可能是有利的。虽然SRAM组件可用于有效地执行所请求数据操作，但是SRAM组件通常归因于成本考虑而在存储器装置中受限。因而，使用较小能力存储器组件或其它存储器类型来按类似于或高于高能力存储器组件的速率执行操作可能是有利的。
附图说明
在阅读以下详细描述及在参考图式时可更好地理解本发明的各种方面，其中：
图1说明根据实施例的计算系统的实例的框图；
图2说明根据实施例的可作为图1的计算系统的部分的存储器装置的实例的框图；
图3说明根据实施例的可包含若干存储器层的实例三维堆叠式存储器组件的俯视图；
图4说明根据实施例的图3的存储器组件的物理层的示意图；
图5说明根据实施例的组成图3的存储器组件的一部分的物理层的实例虚拟库的示意图；
图6说明根据实施例的映射到虚拟库的四个数据结构的框图；
图7说明根据实施例的用于确定将在图3的存储器装置的存储器组件中形成的虚拟库的数目的方法的流程图；
图8说明根据实施例的存储器组件的实例数据结构的框图；
图9说明根据实施例的图4的数据结构的分割版本的框图；
图10说明根据实施例的用于基于优选队列深度确定将在图2的存储器装置的存储器组件中形成的虚拟库的数目的方法的流程图；及
图11说明根据实施例的相对于各种队列深度的虚拟库的数目的对数图。
具体实施方式
下文将描述一或多个特定实施例。为了提供这些实施例的简洁描述，本说明书中未描述实际实施方案的所有特征。应了解，在任何此实际实施方案的研发中，如在任何工程或设计项目中，必须作出许多实施方案特定决策以实现可随实施方案的变化而变化的研发者的特定目标，例如符合系统相关及业务相关的限制。此外，应了解，此研发努力可能是复杂且耗时的，但对于受益于本发明的一般技术人员来说，所述研发努力仍将是常规设计、制作及制造任务。
一般来说，不同的存储器类型具有不同能力。即，不同的存储器类型可比其它存储器类型更有效地执行某些类型的功能。例如，DRAM存储器类型可能无法像SRAM存储器一样快地执行功能。在某些实施例中，存储器系统可将DRAM的部分映射为虚拟库，且使用虚拟库同时执行多个操作。因而，可能已由SRAM个别地执行的操作现可使用DRAM执行。通过在DRAM的虚拟库中同时执行这多个操作，使用虚拟库的存储器系统可提供在使用较低请求速率存储器(DRAM)的同时，使用高请求速率存储器(如SRAM)的错觉。因此，较高能力存储器(如SRAM)可被保留用于执行其它过程。有关在各种存储器类型中映射虚拟库以执行更有效操作的额外细节将在下文更详细描述。
使用可扩展协议的计算及存储器系统
通过介绍，图1说明可包含存储器装置的计算系统10的框图，所述存储器装置可根据本文中描述的技术在存储器组件中映射虚拟库。计算系统10可为多种计算装置中的任何者，例如计算机、传呼机、蜂窝电话、个人记事簿、控制电路等等。计算系统10可包含芯片上主机系统(SoC)12，芯片上主机系统(SoC)12可耦合到若干存储器装置14。主机SoC 12可为集成电路(IC)，其将计算机或其它电子系统的所有组件集成到单个芯片中。因而，主机SoC12可包含一或多个处理器，例如微处理器，所述一或多个处理器可控制计算系统10中的系统功能及请求的处理。如本文中使用，处理器可包含能够在对应电装置上执行可执行指令的任何适当处理器。
如上所述，主机SoC 12可耦合到存储器装置14。在某些实施例中，主机SoC 12可经由通道16耦合到存储器装置14。通道16可包含总线、电布线或类似物。
图2描绘存储器装置14的实施例的框图。存储器装置14可包含经设计以留存数字数据的任何电存储装置。存储器装置14可涵盖各种各样的存储器组件，其包含易失性存储器及非易失性存储器。易失性存储器可包含动态随机存取存储器(DRAM)及/或静态随机存取存储器(SRAM)。此外，易失性存储器可包含若干存储器模块，例如单列直插存储器模块(SIMM)或双列直插存储器模块(DIMM)。
非易失性存储器可包含将结合易失性存储器使用的只读存储器(ROM)，例如EPROM及/或快闪存储器(例如，NAND)。此外，非易失性存储器可包含高容量存储器，例如磁带或磁盘驱动器存储器。如将了解，易失性存储器或非易失性存储器可被视为用于存储代码(例如，指令)的非暂时性有形机器可读媒体。
如图2中所展示，在某些实施例中，存储器装置14可包含芯片上系统(SoC)22，芯片上系统(SoC)22可为存储器中处理器(PIM)或计算机处理器(CPU)，其紧紧地耦合到存储于存储器装置14上的存储器组件。通常，存储器SoC 22可与存储器装置14的存储器组件处在相同硅芯片上。通过将处理组件及存储器组件合并到存储器装置14中，存储器SoC 22可管理在存储器组件与主机SoC 12之间传输及接收数据请求及响应的方式。在某些实施例中，存储器SoC 22可控制存储器组件之间的业务以减小延时及增大带宽。如将了解，在根据本文中描述的实施例控制存储器组件与其它装置之间的传输时，主机SoC 12及存储器SoC 22可采用可扩展存储器系统协议。因而，可扩展存储器系统协议可在存储器装置14与主机SoC12之间的通道16，以及在存储器组件与存储器SoC22之间的通道29上操作。
在某些实施例中，存储器装置14还可包含缓冲器23。缓冲器23可存储由存储器SoC22接收到的一或多个封包。举例来说，存储器装置14可包含例如NAND存储器24、减小延时动态随机存取存储器(RLDRAM)26、双倍数据速率第四代同步动态随机存取存储器(DDR4)28及类似物的存储器类型。
在某些实施例中，主机SoC 12及存储器SoC 22可基于经由存储器组件、寄存器及类似物提供的计算机可执行指令执行各种操作。存储器组件或存储装置可为可充当用于存储处理器可执行代码、数据或类似物的媒体的任何适当制品。这些制品可代表计算机可读媒体(即，任何适当形式的存储器存储装置)，所述计算机可读媒体可存储由主机SoC12或存储器SoC 22使用来执行当前揭示技术的处理器可执行代码。存储器及存储装置也可用于存储数据、数据分析及类似物。存储器及存储装置可代表非暂时性计算机可读媒体(即，任何适当形式的存储器或存储装置)，所述非暂时性计算机可读媒体可存储由主机SoC 12或存储器SoC 22用于执行本文中描述的各种技术的处理器可执行代码。应注意，非暂时性仅指示媒体是有形的且并非是信号。
数据结构的高度分割
如上所述，可通过利用某些类型的存储器的能力以执行通常在其它类型的存储器上执行的操作而更有效地使用存储器装置。例如，如DRAM的低能力存储器类型与例如SRAM的高能力存储器相比可能相对廉价。虽然DRAM可能无法像SRAM一样快地执行功能，但是DRAM的可独立操作区域(IOR)(例如库)可用于同时执行可能已由SRAM个别地执行的多个操作。因而，在某些实施例中，存储器SoC 22可在存储器装置14内分割一或多个存储器组件的数据结构。即，存储器SoC 22可决定如何使用每一存储器组件的可用数据结构分布信息。应提及，如本文中论述，分割数据结构大体上涉及根据存储器组件中已存在的库将数据结构的部分映射到现存库的虚拟库中，及类似情况。如将了解，鉴于库在存储器组件内的相应数据结构，库可独立于彼此操作。以相同方式，在每一库中映射的虚拟库可取决于其中映射每一相应虚拟库的库而独立于彼此操作。在任何情况中，在确定存储器组件中的可用数据结构后，存储器SoC 22可将作为存储器组件的部分的不同数据结构映射到存储器组件的库或虚拟库中。因此，高度分割技术可允许具有高的库计数的廉价存储器，例如DRAM(即，具有比惯用DRAM多的库及被分割以作为惯用DRAM中不存在的虚拟库操作的可能库的DRAM)取代更昂贵且高能力的存储器，例如SRAM。
记住上述内容，存储器装置14中的每一存储器组件可包含特定数目个数据结构，所述数据结构在存储器组件最初制造时可作为所述存储器组件的部分。举例来说，存储器组件可为堆叠式装置，所述堆叠式装置包含可被分布到不同部分(例如室(vault)或库)的存储器的若干层。图3说明实例三维堆叠式存储器组件30的俯视图，三维堆叠存储器组件30可包含可能在制造时形成的若干存储器层。如图3中所展示，存储器组件30可包含耦合到其的若干链路31。通常，上文论述的通道29可包含一或多个链路31，且可提供对存储器组件30的存取。在所描绘的实施例中，每一链路31可包含三个进入通道及两个外出通道。
如上所述，存储器组件30可包含若干存储器层及逻辑层。例如，图4说明存储器组件30的示意图，存储器组件30具有八个存储器层32(例如，DRAM层1到8)及一个逻辑层33(例如，逻辑层0)。每一存储器层32可包含可用于存储数据的存储器位单元。逻辑层33可包含控制电路组件，所述控制电路组件可促进对存储器层32中的一者或多者及对外部接口的存取。
如上文论述，存储器组件30可在制造时经分割以提供存储器组件30的单独片段或IOR。在一个实例中，每一存储器层32可被分为大片段(例如，室)，所述大片段可被进一步分割为较小片段(例如，库)。根据本文中描述的技术，库可被进一步分割为虚拟库。图5说明上文论述的存储器组件30的一部分27的示意图。如图5中所展示，存储器组件30的部分27中的每一存储器层32可被分割为两个室34，且每一室34可被分割为两个库35。
应注意，图5说明有关链路31中的一者的逻辑及存储器堆叠的一部分27。在一个实施例中，对于整个存储器组件30，可能存在64个此类部分(例如，切片)。由于每一存储器层32被分割成两个室34，所以逻辑层33可包含两个控制逻辑部分38，其可控制到每一相应室34的数据流量。在所描绘的实施例中，每一个外部链路31说明两个室34。此配置可提供DRAM技术的内部速度能力的优化及其如何匹配到逻辑层33的外部速度能力。然而，应注意，在某些实施例中，每一室34可包含耦合到逻辑层的其自身的个别垂直总线(未展示)。在某些实施例中，每一链路31可经由逻辑层33对室34进行存取。因而，逻辑层33可提供对存储器层32中的任何者的存取。
记住这点，存储器SoC 22或任何其它适当装置可将库35进一步分割成虚拟库36，虚拟库36可用于提供存储器组件30的改进操作。即，在某些实施例中，存储器SoC 22将存储器层32的片段(例如，库35)的不同部分分配为单独的虚拟库36，虚拟库36可用于执行各种数据操作。
举例来说，图6说明可作为存储器组件30的部分的四个实例数据结构37。如将了解，使用本文中揭示的系统及技术，存储器SoC 22可将数据结构37映射到跨越库35分布的虚拟库36中。即，存储器组件30可包含已被分割为四个虚拟库36(虚拟库0到3)的六个库36(库0到5)。如图6中所说明，数据结构A及数据结构D是读取-修改-写入(RMW)结构，其被映射到数量为只读结构两倍的物理库中。即，与可各自跨越一个库35映射的只读结构相比，RMW结构的寄存器可各自跨越两个库35被映射。通过将每一结构映射到不同库35，存储器SoC22可改进存储器组件30处置多个请求的能力。举例来说，如果第一请求涉及对数据结构A的寄存器A0进行存取且第二请求涉及对数据结构A的寄存器A5进行存取，那么存储器SoC 22可能不针对第二请求提供对数据结构A的存取，直到第一请求已被处理为止。然而，如果数据结构37被映射到图6中所说明的虚拟库36中，那么由于寄存器A0及A5被映射到作为不同库35的部分的不同虚拟库36，所以存储器SoC 22可同时处理第一请求及第二请求，这是因为其两者对不同库35进行存取。
记住存储器组件30的实例分割结构，下文将使用网络设备实例描述使用存储器组件的高度分割的技术。然而，应注意，此相同方法也可在不存在清晰的数据结构时起作用。通常，如上所述，通过将可独立操作区域(IOR)(如DRAM库(例如，库35))放入寻址结构的低阶位中，与数据结构的分割相比，可实现相同系统操作效果。例如，如果DRAM自然存取是128位(16字节)，那么紧接在16B群组之前的地址位可引向下一IOR。因而，连续的随机事务可能进入与前一事务不同的IOR。
查看网络设备实例，在可支持因特网业务的高速路由器中，当封包被路由器接收时，可参考高达40个不同数据结构。如果传入数据的聚合线速率是400Gb/s，那么最小封包大小是512个位，且围绕封包的额外时间间隙导致封包持续时间为672个位，且所有封包为相同大小，那么封包速率是1.68ns或672个位/400Gb/s。一些结构可简单以每个封包被触摸(例如，读取或写入)一次，而其它结构可被触摸两次(例如，读取及写入)。因而，为了支持此线速率，存储器可支持2次触摸的随机存取速率1.68ns/2＝0.84ns，其可能难以使任何存储器支持此类型的随机存取。此外，可能难以设计DRAM以准许0.84ns的行循环时间(tRC)或将其扩展到甚至更小的tRC值。如本文中所使用，存储器组件的tRC是指存储器组件的存储器行完成完整循环(从行激活到有源行的预充电)所花费的最小时间量(例如，时钟循环)。
为了促进此类型的随机存取，由存储器SoC 22利用的个别DRAM的库计数的数目可经增大以提供足够数目的库来涵盖随机具有0.84ns的针对2次触摸的近似存取速率的应用程序的需要。为了确定个别DRAM的库计数的数目，存储器SoC 22可确定存储器组件的数据结构可用于根据优选随机存取请求速率实现成功系统操作的程度或量。通常，分割使用的数量可依据存储器组件的tRC对优选随机存取请求速率的比率。
记住上述内容，图7说明用于确定存储器SoC 22可选择以在存储器组件(例如，DRAM)中使用的最小数目个片段的方法40。如果存储器组件包含小于此最小数目个片段，那个存储器组件的片段可开始接收随机请求，所述随机请求将偶尔占用每一片段，同时到达且导致各种延迟。因而，在实践中，在执行方法40后实施的片段的数目可包含除所计算的最小值以外的一或多个片段。如本文中使用，片段是指存储器组件30中已存在的库35。片段还指如上文描述的由处理器映射的虚拟库36。在某些实施例中，存储器SoC 22可在使用相应存储器组件的不同片段之前执行下文描述的方法40。然而，应理解，方法40可由任何适当处理器执行。为论述目的，将参考虚拟库36描述方法40的以下描述，但是应理解，方法40也可参考作为存储器组件30的部分的库35执行。
在框42处，存储器SoC 22可接收预期被传输到存储器SoC 22的封包的预期随机存取速率。重新参考上文提出的实例，如果传入数据的聚合线速率是400Gb/s，那么最小封包大小是512个位(包含封包间间隙的672位等效物)，且所有封包为最小大小，那么每一接收到的封包的预期随机存取速率是大约1.68ns。假设每一封包包含2次触摸数据操作，那么针对每一接收到的封包的预期随机存取速率是大约0.84ns。
在框44处，存储器SoC 22可接收存储器组件的行循环时间(tRC)。如上文论述，存储器组件的tRC是指存储器组件的存储器行完成完整循环(从行激活到有源行的预充电)所花费的最小时间量(例如，时钟循环)。换句话来说，存储器组件的tRC可以是指存储器组件中的数据结构(例如，库)在执行一个数据操作(例如，2次触摸操作)时可使用的时间量。
在框46处，存储器SoC 22可基于存储器组件的tRC对每一接收到的封包的预期随机存取速率的比率确定相应存储器组件中可使用的虚拟库的最小数目。如果在框44处接收的存储器组件的tRC是8.4ns，那么在上文实例中存储器组件的tRC对每一各接收到的封包的预期随机存取速率的比率是8.4:0.84或10比1。存储器组件的tRC与每一接收到的封包的预期随机存取速率之间的所得比率可对应于将在相应存储器组件中使用以适应每一接收到的封包的预期随机存取速率的最小数目个虚拟库。即，所得比率可识别相应存储器组件中在不添加封包到队列的情况下继续接收封包所需的虚拟库的数目。
如上所述，存储器组件30可在设计或制造存储器组件30时，被大体上分布到不同结构(例如，室34、库35)中。一个分布实例包含将存储器组件30划分为库35，如上文论述。库30可使用共享的独立行及列解码器、感测放大器及数据路径存取。
记住这点，在一些实施例中，存储器SoC 22可通过将库35划分为虚拟库36而使用较少资源来对存储器层35进行存取。即，存储器SoC 22可将库35的不同部分映射到若干虚拟库36中以使不同库35能独立操作。因而，逻辑层33的单独行解码器可用于对每一虚拟库36进行存取，但资源的一些共性仍可沿着相应数据路径及经由逻辑层33的列解码器存在。
与将不同库35映射到不同室34或不同存储器层32的部分中相比，通过将一个库35映射到虚拟库34中，存储器SoC 22可引致较少面积损失(例如，额外2到3％)。即，新请求可进入具有若干虚拟库36的此单个库35，且使用共享资源(例如，列解码器)对虚拟库中的每一者进行存取。因而，存储器SoC 22可按～4ns的列到列延迟时间(tCCD)的速率送达请求，所述延迟时间比整个库35的行循环时间(tRC)(例如，～35ns)快。虽然在一些情况中，tCCD速率可比数据路径能力(例如，可按1到2ns操作)慢，但是与常规系统相比，使用虚拟库36仍可在对存储器组件30进行存取时提供改进的速度。
重新参考框46，在确定将在相应存储器组件中使用的虚拟库的最小数目后，存储器SoC 22可开始将相应存储器组件中的一或多个数据结构映射到相应虚拟库36。应注意，通过将存储器组件30设计为具有更多库35，或将虚拟库36添加到库35，存储器组件30可使用额外硅区域，其可关联于更高成本及因此更高的每位成本。因此，如果存储器组件30的裸片大小恒定，那么较少位可在存储器组件30中可用。然而，本文中描述的映射过程不会实际导致任何存储器容量(例如，存储器位计数)损失减小。而是，本文中描述的映射技术可导致数据围绕存储器组件30散布。因而，额外逻辑可用于保持追踪使用中的存储器及空闲的存储器。
为了更好地说明分割存储器组件的益处，图8说明尚未被分割成虚拟库36的存储器组件的实例数据结构60。如图8中所展示，数据结构60包含16个存储器地址62。当封包请求被具有数据结构60的相应存储器组件接收时，封包请求的对应数据操作可能导致数据结构无法被存储器组件30的tRC获得。即，举例来说，如果第一封包请求包含针对数据结构60的元素3的请求，且第二封包请求包含针对元素16的请求，那么第二封包请求无法被执行，直到第一封包请求已被完成或直到存储器组件的tRC已通过为止。如果当第二请求封包正在试图对数据结构60进行存取时，存储器组件的tRC尚未通过，那么存储器SoC 22可被放置在针对相应数据结构60的队列中。
图9说明具有虚拟库72、74、76及78的分割数据结构70。在一个实施例中，数据结构70的每一输入项可基于虚拟库36的数目按循环方式编号。例如，取代如图8的数据结构60中所展示按时间顺序对每一存储器地址编号，将元素1映射到虚拟库72、将元素2映射到虚拟库74、将元素3映射到虚拟库76、将元素4映射到虚拟库78、将元素5映射到虚拟库72，且以此类推。
记住上述内容，当将上文提出的实例应用于图9的分割数据结构70时，分割数据结构70的值将变得明显。即，如果第一封包请求包含针对分割数据结构70的元素3的请求，那么存储器SoC 22可提供对分割数据结构70的虚拟库76的存取。由于每一分割数据结构是相同存储器组件的部分，所以每一虚拟库的tRC对应于存储器组件的tRC。然而，与数据结构60不同，如果第二封包请求包含针对元素16的请求，那么存储器SoC22可提供对虚拟库78的存取，而不管第一封包请求是否已停止对虚拟库76进行存取。如将了解，由于虚拟库76及虚拟库78是独立于彼此，所以即使当虚拟库76忙于执行另一操作时，存储器SoC 22仍可提供对虚拟库78的存取。因而，与数据结构60相比，存储器组件使用分割数据结构70有效执行数据操作的能力随更多虚拟库产生而增大。
虽然图7的方法40可提供将在存储器组件30中形成的最小数目个虚拟库，但是在存储器组件30中增加额外虚拟库以补偿各种错误、非预期延迟、在队列中等待对存储器组件30进行存取的封包及类似物可能是有利的。举例来说，考虑针对1011个随机请求循环的上文描述的网络系统的模拟及假设每1.68ns可接收到请求的基线SRAM及无数据结构分割，队列深度(即，新请求在全管线化系统中等待答案的时间)针对仅具有1次触摸的操作可为1个封包。另一方面，针对具有2次触摸的操作，队列时间倾向于无限。即，当每一请求执行触摸两次时，SRAM无法跟上。由于每1.68ns，存储器组件可接收两次触摸请求(即使其在所述时间跨度内只能处理一次触摸操作)，所以队列深度在每一接收到的封包后增大，且倾向于无限。因而，此模拟系统无法如设计那样起作用。
现参考来自使用4向数据结构分割的上述实例的模拟的一些数据点，具有相对tRC＝2*请求速率的装置的最大队列延迟被模拟为12。对于相对tRC＝3x，最大队列延迟被模拟为31。基于相应存储器组件的各种性质，可能期望良好系统操作的最大队列延迟不大于大约15。因而，tRC＝2x是每个封包1次触摸结构的合理解决方案。对于2次触摸，tRC被有效翻番，这是因为需要2个操作，因此tRC＝2x将表现为tRC＝4x，其在此实例中将具有不可接受的长队列时间。
在64向分割中且假设tRC＝8.4ns(即，5x封包速率)，队列深度可被模拟为6，其对于每个封包1次触摸而言是可接受的。然而，在模拟每个封包2次触摸的tRC＝10x，队列深度可被模拟为9，其也可能是可接受的。因此，通过采用相应存储器组件的64个库(其可以5x封包速率循环)，即使在每个输入封包2次触摸存储器的情况下，存储器系统仍可跟上全线速率。
在tRC＝6x(即，在此实例中的10.08ns)的64向分割中，DRAM的对应类别可使用快速库循环技术，同时仍使用常规1T-1C DRAM单元及常规感测放大器建立。在此，队列针对1次触摸可为7，且针对2次触摸可为10，两者再次是可接受的。举例来说，如果40个数据结构的系统具有1次触摸(即，只读)结构的14个结构，且具有2次触摸(即，读取-修改-写入)结构的24个结构，那么针对14个只读结构中的每一者的16向分割可能涉及总共224个库。因而，在此实例中，队列将为13。其余26个结构可被赋予30向分割，由此消耗780个库35。在此，2次触摸队列可为14个。在此实例中涉及的库35的总数目接着可为224+780＝1,004。如果可用的库35的总数目是1,024，那么20个库35仍可用于其它功能。记住这点，如果系统使用8个DRAM来实现期望存储器容量及带宽，那么每一DRAM可使用128个库35，其可能比产业标准DRAM高，但按合理成本设计及建立仍可行。
虽然在此参考网络路由器描述数据结构的分割，但是应理解，本文中描述的技术也可用于其它类型的系统中。因而，上述实例不希望将当前揭示技术的范围限制为网络化。
记住上述内容，图10说明用于基于优选队列深度确定将在存储器组件中形成的虚拟库的数目的方法90。如上文参考图7所提及，为论述目的，将参考虚拟库36描述方法90的以下描述，但是应理解，方法90也可参考作为存储器组件30的部分的库35执行。
在一个实施例中，方法90可在根据方法40确定将在存储器组件中形成的虚拟库36的数目后执行。即，方法40可用于确定将在存储器组件30中映射的虚拟库36的最小数目，且接着方法90可用于微调或识别将在存储器组件30中映射的虚拟库36的数目以有效执行各种数据请求。
如同方法40，方法90的以下描述将被描述为由存储器组件SoC 22执行，但是应理解，任何适当处理器可执行方法90。此外，虽然方法90按特定顺序提出，但是应注意，方法90可按任何适当顺序执行。
现参考图10，在框92处，存储器SoC 22可接收优选队列深度。优选队列深度可基于在存储器组件被分割后可用的存储器量确定。通常，每一队列深度增量涉及在存储器组件中使用额外寄存器或额外存储器以存储排队的对应数据。因而，优选队列深度可与存储器组件中可用的存储器量相关。
应注意，存储器成本涉及增大存储器组件30可支持的队列深度的量。即增大存储器组件30的可用队列深度，涉及使用存储器组件30的更多寄存器来增大队列深度。然而，为了减小队列深度，存储器SoC 22可在存储器组件30内映射虚拟库36。然而，虚拟库36的映射仍增大存储器成本，且增加有关逻辑层33的控制逻辑成本以适应针对不同虚拟库36的不同队列。然而，与分割存储器组件30相比的未分割存储器组件30的相对较长队列深度对应于与使用具有虚拟库36所涉及的多个队列相比的较低系统性能。
在框94处，存储器SoC 22可基于针对存储器组件30的虚拟库36具有一定预期触摸率的随机业务确定在达到优选队列深度前执行的循环数目。在某些实施例中，虚拟库36的预期量可对应于方法40的结果。
使用针对使用方法40确定的最小数目个虚拟库36具有预期触摸率的随机业务，存储器SoC 22可执行存储器组件30从而接收特定数目个随机请求的模拟。在一个实施例中，存储器SoC 22可执行模拟，直到已达到优选队列深度。
举例来说，图11说明对数图110，其说明关于存储器组件30中存在的虚拟库36的数目，各种队列深度值在若干循环内发生时的情况。如对数图110中所展示，当存储器组件30被分割为4个虚拟库36时，在10,000个循环后达到2的最大队列深度。记住这点，在框94处，存储器SoC 22可使用模拟来确定预期在达到优选队列深度之前执行的循环的数目。
再次参考图10，在框96处，存储器SoC 22可确定循环数目是否大于某一阈值。在一个实施例中，阈值可与被模拟为业务的封包的预期封包错误率相关联。即，虽然由上文描述的方法40确定的虚拟库36的数目可提供足够数目的虚拟库36来执行与接收到的封包相关联的数据操作，但是所确定数目不考虑接收到的封包的封包错误率。任何封包可具有反映在错误可能发生之前执行的预期数目个循环的封包错误率。举例来说，封包错误率可为每109个循环1个错误。当封包发生错误时，封包被重新传输且存储器组件30的队列(例如，队列深度)可增大。
记住这点，且考虑作为模拟的部分的封包的随机业务，请求封包可在先前请求封包完成处理前重复到达相同虚拟库36。因而，请求封包可作为队列的部分被备份或存储于寄存器中。在某些实施例中，请求封包的积存可存储于存储器组件30前方的队列中。然而，队列的大小受限，这是因为用于在队列中保存封包的每一寄存器耗用存储器空间。某时，存储器空间将不再可用。如果队列资源被剔除的频率归因于封包错误而小于正常封包丢弃率，那么存储器组件30的操作中可能不存在任何可观测的损失。例如，如果封包在109次中丢弃1个，那么存储器组件30可被选择以包含足够的寄存器来支持在1012个请求中丢弃1个的队列或0.1％的正常封包丢弃率。因而，重新参考框96，在一些实施例中，阈值可比封包错误率大一定倍数。举例来说，如果1010个封包的一个封包丢弃，那么阈值可被设置为1012。
如果存储器SoC 22确定循环数目不大于阈值，那么存储器SoC 22可结束方法90，且用在框94处使用的虚拟库的数目继续进行。但是，如果存储器SoC 22确定循环数目大于阈值，那么存储器SoC 22可增大在存储器组件30中映射的虚拟库36的量，且在框98处，重复框94到98，直到达到优选队列深度的循环数目小于阈值。
虽然上文描述的方法90被描述为由存储器SoC 22执行，但是应注意，在某些实施例中，方法90可由独立于存储器装置14操作的处理器执行。即，与典型存储器SoC相比，执行方法90的处理器可具有额外处理力，以确定虚拟库36的量以更快地使用。然而，如果方法90由存储器SoC 22执行，那么应注意，存储器SoC 22可包含额外控制逻辑、计数器及随机数目产生器以有效执行方法90。
虽然本文中描述的实施例可具有各种修改及替代形式，但是特定实施例已在图式中通过实例展示且已在本文中予以详细描述。然而，应了解，本发明并不希望限于所揭示的特定形式。而是，本发明涵盖落于如由以下所附权利要求书定义的本发明的精神及范围内的所有修改、等效物及替代。

Claims (18)

1.一种存储器装置，其包括：
存储器组件，其经配置以存储数据；及
处理器，其经配置以基于与所述存储器组件相关联的一个或多个性质及所述存储器组件的预期随机存取速率而在所述存储器组件中映射一个或多个库或一个或多个虚拟库，其中基于所述一个或多个性质及所述预期随机存取速率确定所述一个或多个库的第一数目或所述虚拟库的第二数目，以及经由所述处理器，基于所述存储器组件的优选队列深度微调或识别将在所述存储器组件中产生的虚拟库的第三数目；其中经由所述处理器，基于所述优选队列深度微调或识别将在所述存储器组件中产生的虚拟库的所述第三数目包括：执行对所述存储器组件进行存取的多个随机请求的模拟及确定由所述处理器执行以达到所述优选队列深度的循环的数目。
2.根据权利要求1所述的存储器装置，其中所述存储器组件包括动态随机存取存储器或NAND存储器。
3.根据权利要求1所述的存储器装置，其中所述处理器经配置以经由所述虚拟库的两个不同虚拟库对所述存储器组件执行至少两个数据操作，其中所述至少两个数据操作的一部分被同时执行。
4.根据权利要求1所述的存储器装置，其中与所述存储器组件相关联的所述性质包括所述存储器组件的行循环时间。
5.根据权利要求1所述的存储器装置，其中所述预期随机存取速率是基于由所述处理器接收的请求的聚合线速率、所述请求中的每一请求的最小大小及由所述请求中的每一请求执行的触摸操作的类型而确定。
6.一种方法，其包括：
经由处理器，接收与对存储器组件进行存取相关联的预期随机存取速率；
经由所述处理器，接收与所述存储器组件相关联的行循环时间；
经由所述处理器，基于所述预期随机存取速率及所述行循环时间确定将在所述存储器组件中产生的库的第一数目或虚拟库的第二数目，以及基于所述存储器组件的优选队列深度微调或识别将在所述存储器组件中产生的虚拟库的第三数目；
其中经由所述处理器，基于所述优选队列深度微调或识别将在所述存储器组件中产生的虚拟库的所述第三数目包括：执行对所述存储器组件进行存取的多个随机请求的模拟及确定由所述处理器执行以达到所述优选队列深度的循环的数目；及
经由所述处理器，分别基于所述第一数目的库或所述第二数目的虚拟库在所述存储器组件中映射一个或多个库或一个或多个虚拟库，其中所述存储器组件中的所述一个或多个虚拟库中的每一虚拟库可基于所述存储器组件中的所述一个或多个虚拟库的位置独立存取。
7.根据权利要求6所述的方法，其中所述行循环时间包括所述存储器组件的存储器行完成完整循环的时间量。
8.根据权利要求6所述的方法，其中所述预期随机存取速率是基于与对所述存储器组件进行存取中的每一请求相关联的触摸的数目确定。
9.根据权利要求6所述的方法，其中确定将在所述存储器组件中产生的虚拟库的所述数目包括确定所述行循环时间对所述预期随机存取速率的比率。
10.根据权利要求6所述的方法，其包括经由所述处理器对所述一个或多个虚拟库的第一虚拟库进行存取，同时所述一个或多个虚拟库的第二虚拟库也被存取。
11.根据权利要求6所述的方法，其包括经由所述处理器将所述存储器组件的多个元素映射到所述存储器组件的所述一个或多个库或所述一个或多个虚拟库中的一个或多个元素。
12.一种有形的非暂时性机器可读媒体，其包括指令，所述指令经配置以：
接收与对存储器组件进行存取相关联的预期随机存取速率；
接收与所述存储器组件相关联的行循环时间；
基于所述预期随机存取速率及所述行循环时间确定将在所述存储器组件中产生的库的第一数目或虚拟库的第二数目；
接收所述存储器组件的优选队列深度，其中所述优选队列深度包括在队列中等待对所述存储器组件进行存取的包的数目；
基于将由所述存储器组件接收的多个随机包的预期触摸速率及所述存储器组件中的库的所述第一数目或虚拟库的所述第二数目确定达到所述优选队列深度的循环的数目，其中所述存储器组件中的所述第二数目的虚拟库中的每一虚拟库可基于所述存储器组件中的所述第二数目的虚拟库中的每一虚拟库的位置独立存取；及
基于循环的所述数目确定所述存储器组件中的库的第三数目或虚拟库的第四数目。
13.根据权利要求12所述的有形的非暂时性机器可读媒体，其中用于确定循环的所述数目的所述指令包括用于执行以下操作的指令：
执行由所述存储器组件针对所述第一数目的库或所述第二数目的虚拟库接收所述多个随机包的模拟；及
基于所述模拟确定循环的所述数目。
14.根据权利要求12所述的有形的非暂时性机器可读媒体，其中用于确定虚拟库的所述第四数目的所述指令包括用于执行以下操作的指令：
确定循环的所述数目是否超过阈值；及
当循环的所述数目超过所述阈值时，增加虚拟库的所述第二数目。
15.根据权利要求14所述的有形的非暂时性机器可读媒体，其中所述阈值与包错误率相关联。
16.根据权利要求15所述的有形的非暂时性机器可读媒体，其中所述包错误率包括在由所述存储器组件接收所述多个随机包的模拟期间在错误发生前执行的预期数目个循环。
17.根据权利要求14所述的有形的非暂时性机器可读媒体，其中所述阈值是包错误率的倍数。
18.根据权利要求12所述的有形的非暂时性机器可读媒体，其中所述存储器组件包括动态随机存取存储器或NAND存储器。
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Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9606928B2 (en) * 2014-08-26 2017-03-28 Kabushiki Kaisha Toshiba Memory system
US10127383B2 (en) * 2014-11-06 2018-11-13 International Business Machines Corporation Resource usage optimized auditing of database shared memory
US9817602B2 (en) * 2014-11-13 2017-11-14 Violin Systems Llc Non-volatile buffering for deduplication
GB2539443B (en) * 2015-06-16 2020-02-12 Advanced Risc Mach Ltd A transmitter, a receiver, a data transfer system and a method of data transfer
EP3417583B1 (en) * 2016-02-19 2020-12-30 Viasat, Inc. Methods and systems for multi-level network capacity allocation
US9997232B2 (en) * 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
TWI587133B (zh) * 2016-05-20 2017-06-11 慧榮科技股份有限公司 資料儲存裝置之資料頁對齊方法及其查找表的製作方法
JP2018049387A (ja) * 2016-09-20 2018-03-29 東芝メモリ株式会社 メモリシステム及びプロセッサシステム
US11314648B2 (en) 2017-02-08 2022-04-26 Arm Limited Data processing
US10216671B2 (en) 2017-02-27 2019-02-26 Qualcomm Incorporated Power aware arbitration for bus access
US10784986B2 (en) 2017-02-28 2020-09-22 Intel Corporation Forward error correction mechanism for peripheral component interconnect-express (PCI-e)
US10318381B2 (en) * 2017-03-29 2019-06-11 Micron Technology, Inc. Selective error rate information for multidimensional memory
CN109478168B (zh) 2017-06-23 2020-12-04 华为技术有限公司 内存访问技术及计算机系统
US10713189B2 (en) * 2017-06-27 2020-07-14 Qualcomm Incorporated System and method for dynamic buffer sizing in a computing device
US10387242B2 (en) 2017-08-21 2019-08-20 Qualcomm Incorporated Dynamic link error protection in memory systems
US10908820B2 (en) * 2017-09-14 2021-02-02 Samsung Electronics Co., Ltd. Host-based and client-based command scheduling in large bandwidth memory systems
GB2569275B (en) * 2017-10-20 2020-06-03 Graphcore Ltd Time deterministic exchange
US10963003B2 (en) 2017-10-20 2021-03-30 Graphcore Limited Synchronization in a multi-tile processing array
GB201717295D0 (en) 2017-10-20 2017-12-06 Graphcore Ltd Synchronization in a multi-tile processing array
GB2569276B (en) 2017-10-20 2020-10-14 Graphcore Ltd Compiler method
CN107943611B (zh) * 2017-11-08 2021-04-13 天津国芯科技有限公司 一种快速产生crc的控制装置
US10824376B2 (en) 2017-12-08 2020-11-03 Sandisk Technologies Llc Microcontroller architecture for non-volatile memory
US10622075B2 (en) 2017-12-12 2020-04-14 Sandisk Technologies Llc Hybrid microcontroller architecture for non-volatile memory
CN110022268B (zh) * 2018-01-09 2022-05-03 腾讯科技（深圳）有限公司 一种数据传输控制方法、装置及存储介质
CN108388690B (zh) * 2018-01-16 2021-04-30 电子科技大学 元胞自动机实验平台
KR20190099879A (ko) * 2018-02-20 2019-08-28 에스케이하이닉스 주식회사 메모리 컨트롤러 및 그 동작 방법
US10810304B2 (en) 2018-04-16 2020-10-20 International Business Machines Corporation Injecting trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code
US11003777B2 (en) 2018-04-16 2021-05-11 International Business Machines Corporation Determining a frequency at which to execute trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code
US10831653B2 (en) * 2018-05-15 2020-11-10 Micron Technology, Inc. Forwarding code word address
US11003375B2 (en) 2018-05-15 2021-05-11 Micron Technology, Inc. Code word format and structure
US10496478B1 (en) * 2018-05-24 2019-12-03 Micron Technology, Inc. Progressive length error control code
US10409680B1 (en) * 2018-05-24 2019-09-10 Micron Technology, Inc. Progressive length error control code
US10969994B2 (en) * 2018-08-08 2021-04-06 Micron Technology, Inc. Throttle response signals from a memory system
US11074007B2 (en) 2018-08-08 2021-07-27 Micron Technology, Inc. Optimize information requests to a memory system
TWI819072B (zh) * 2018-08-23 2023-10-21 美商阿爾克斯股份有限公司 在網路運算環境中用於避免環路衝突的系統、非暫態電腦可讀取儲存媒體及電腦實現方法
KR102541897B1 (ko) 2018-08-27 2023-06-12 에스케이하이닉스 주식회사 메모리 시스템
US11080210B2 (en) 2018-09-06 2021-08-03 Micron Technology, Inc. Memory sub-system including an in package sequencer separate from a controller
US11061751B2 (en) 2018-09-06 2021-07-13 Micron Technology, Inc. Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller
US10838909B2 (en) 2018-09-24 2020-11-17 Hewlett Packard Enterprise Development Lp Methods and systems for computing in memory
US10771189B2 (en) 2018-12-18 2020-09-08 Intel Corporation Forward error correction mechanism for data transmission across multi-lane links
WO2020135385A1 (zh) * 2018-12-29 2020-07-02 上海寒武纪信息科技有限公司 通用机器学习模型、模型文件的生成和解析方法
CN109815043B (zh) * 2019-01-25 2022-04-05 华为云计算技术有限公司 故障处理方法、相关设备及计算机存储介质
US11637657B2 (en) 2019-02-15 2023-04-25 Intel Corporation Low-latency forward error correction for high-speed serial links
US10997111B2 (en) 2019-03-01 2021-05-04 Intel Corporation Flit-based packetization
US11249837B2 (en) * 2019-03-01 2022-02-15 Intel Corporation Flit-based parallel-forward error correction and parity
US10777240B1 (en) 2019-03-07 2020-09-15 Sandisk Technologies Llc Efficient control of memory core circuits
TWI810262B (zh) * 2019-03-22 2023-08-01 美商高通公司 用於計算機器的可變位元寬資料格式的單打包和拆包網路及方法
US10983795B2 (en) * 2019-03-27 2021-04-20 Micron Technology, Inc. Extended memory operations
US11296994B2 (en) 2019-05-13 2022-04-05 Intel Corporation Ordered sets for high-speed interconnects
US10877889B2 (en) * 2019-05-16 2020-12-29 Micron Technology, Inc. Processor-side transaction context memory interface systems and methods
US10971199B2 (en) 2019-06-20 2021-04-06 Sandisk Technologies Llc Microcontroller for non-volatile memory with combinational logic
US11740958B2 (en) 2019-11-27 2023-08-29 Intel Corporation Multi-protocol support on common physical layer
EP4082012A4 (en) 2019-12-26 2024-01-10 Micron Technology, Inc. METHOD FOR NON-DETERMINISTIC OPERATION OF A STACKED MEMORY SYSTEM
WO2021133692A1 (en) 2019-12-26 2021-07-01 Micron Technology, Inc. Truth table extension for stacked memory systems
WO2021133690A1 (en) 2019-12-26 2021-07-01 Micron Technology, Inc. Host techniques for stacked memory systems
KR20210091404A (ko) 2020-01-13 2021-07-22 삼성전자주식회사 메모리 장치, 메모리 모듈 및 메모리 장치의 동작 방법
US11507498B2 (en) 2020-03-05 2022-11-22 Sandisk Technologies Llc Pre-computation of memory core control signals
EP4133048A1 (en) 2020-04-10 2023-02-15 The Procter & Gamble Company Cleaning implement with a rheological solid composition
US12004009B2 (en) * 2020-05-04 2024-06-04 Qualcomm Incorporated Methods and apparatus for managing compressor memory
US11979330B2 (en) * 2020-06-22 2024-05-07 Google Llc Rate update engine for reliable transport protocol
US11474743B2 (en) * 2020-08-13 2022-10-18 Micron Technology, Inc. Data modification
US11494120B2 (en) * 2020-10-02 2022-11-08 Qualcomm Incorporated Adaptive memory transaction scheduling
TWI763131B (zh) * 2020-11-18 2022-05-01 瑞昱半導體股份有限公司 網路介面裝置、包含該網路介面裝置之電子裝置，及網路介面裝置的操作方法
US11409608B2 (en) * 2020-12-29 2022-08-09 Advanced Micro Devices, Inc. Providing host-based error detection capabilities in a remote execution device
US11481270B1 (en) * 2021-06-16 2022-10-25 Ampere Computing Llc Method and system for sequencing data checks in a packet
CN113840272B (zh) * 2021-10-12 2024-05-14 北京奕斯伟计算技术股份有限公司 数据传输方法、数据传输装置以及电子装置
US11886367B2 (en) * 2021-12-08 2024-01-30 Ati Technologies Ulc Arbitration allocating requests during backpressure
CN114301995B (zh) * 2021-12-30 2023-07-18 上海交通大学 实时工业以太网协议的转换切换与互通融合系统及其方法
US20230236992A1 (en) * 2022-01-21 2023-07-27 Arm Limited Data elision
US11922026B2 (en) 2022-02-16 2024-03-05 T-Mobile Usa, Inc. Preventing data loss in a filesystem by creating duplicates of data in parallel, such as charging data in a wireless telecommunications network
US11914473B1 (en) * 2022-10-20 2024-02-27 Micron Technology, Inc. Data recovery using ordered data requests

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102754088A (zh) * 2009-12-07 2012-10-24 桑迪士克科技股份有限公司 用于在非易失性存储器阵列中的同时后台和前台操作的方法和系统

Family Cites Families (215)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7380092B2 (en) 2002-06-28 2008-05-27 Rambus Inc. Memory device and system having a variable depth write buffer and preload method
USRE36751E (en) * 1987-07-15 2000-06-27 Hitachi, Ltd. ATM switching system connectable to I/O links having different transmission rates
EP0453863A2 (en) 1990-04-27 1991-10-30 National Semiconductor Corporation Methods and apparatus for implementing a media access control/host system interface
US5379297A (en) * 1992-04-09 1995-01-03 Network Equipment Technologies, Inc. Concurrent multi-channel segmentation and reassembly processors for asynchronous transfer mode
JPH05308373A (ja) * 1992-04-28 1993-11-19 Matsushita Electric Ind Co Ltd スター型分散制御ネットワークおよびそれに用いる端末装置
US5771247A (en) * 1994-10-03 1998-06-23 International Business Machines Corporation Low latency error reporting for high performance bus
US6725349B2 (en) 1994-12-23 2004-04-20 Intel Corporation Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory
US5781449A (en) * 1995-08-10 1998-07-14 Advanced System Technologies, Inc. Response time measurement apparatus and method
US5978874A (en) * 1996-07-01 1999-11-02 Sun Microsystems, Inc. Implementing snooping on a split-transaction computer system bus
US5935213A (en) * 1996-05-02 1999-08-10 Fore Systems, Inc. System and method for generating explicit rate value information for flow control in ATAM network
US5918182A (en) * 1996-08-30 1999-06-29 Motorola, Inc. Method and apparatus for mitigating data congestion in an integrated voice/data radio communications system
US5754567A (en) 1996-10-15 1998-05-19 Micron Quantum Devices, Inc. Write reduction in flash memory systems through ECC usage
US6272600B1 (en) 1996-11-15 2001-08-07 Hyundai Electronics America Memory request reordering in a data processing system
US6208655B1 (en) * 1996-11-27 2001-03-27 Sony Europa, B.V., Method and apparatus for serving data
US6292834B1 (en) * 1997-03-14 2001-09-18 Microsoft Corporation Dynamic bandwidth selection for efficient transmission of multimedia streams in a computer network
KR100247022B1 (ko) * 1997-06-11 2000-04-01 윤종용 Atm 스위칭 시스템의 단일 스위치 소자 및 버퍼 문턱값 결정 방법
US6021124A (en) * 1997-08-19 2000-02-01 Telefonaktiebolaget Lm Ericsson Multi-channel automatic retransmission query (ARQ) method
US6516442B1 (en) * 1997-12-07 2003-02-04 Conexant Systems, Inc. Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system
JP2881418B1 (ja) * 1998-02-20 1999-04-12 一男 佐藤 識別データー記載シリコン基板およびその製造方法
JP3650262B2 (ja) * 1998-03-20 2005-05-18 富士通株式会社 セルの転送レート制御装置およびその方法
US6782490B2 (en) * 1999-03-17 2004-08-24 At&T Corp. Network-based service for the repair of IP multicast sessions
US6952401B1 (en) * 1999-03-17 2005-10-04 Broadcom Corporation Method for load balancing in a network switch
US7668189B1 (en) * 1999-07-08 2010-02-23 Thomson Licensing Adaptive transport protocol
US6751698B1 (en) * 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
DE60036453T2 (de) * 1999-11-22 2008-06-19 Sony Corp. Videobandaufzeichnungs- und wiedergabegerät und videobandabspielgerät
US6799220B1 (en) * 2000-04-13 2004-09-28 Intel Corporation Tunneling management messages over a channel architecture network
US6715007B1 (en) * 2000-07-13 2004-03-30 General Dynamics Decision Systems, Inc. Method of regulating a flow of data in a communication system and apparatus therefor
CN1276372C (zh) * 2000-09-29 2006-09-20 艾拉克瑞技术公司 智能网络存储接口系统和装置
US20020159552A1 (en) 2000-11-22 2002-10-31 Yeshik Shin Method and system for plesiosynchronous communications with null insertion and removal
US20020069317A1 (en) 2000-12-01 2002-06-06 Chow Yan Chiew E-RAID system and method of operating the same
GB0031535D0 (en) * 2000-12-22 2001-02-07 Nokia Networks Oy Traffic congestion
US7469341B2 (en) * 2001-04-18 2008-12-23 Ipass Inc. Method and system for associating a plurality of transaction data records generated in a service access system
US7287649B2 (en) 2001-05-18 2007-10-30 Broadcom Corporation System on a chip for packet processing
US7006438B2 (en) * 2001-05-31 2006-02-28 Turin Networks Distributed control of data flow in a network switch
US20030033421A1 (en) * 2001-08-02 2003-02-13 Amplify.Net, Inc. Method for ascertaining network bandwidth allocation policy associated with application port numbers
US20030031178A1 (en) * 2001-08-07 2003-02-13 Amplify.Net, Inc. Method for ascertaining network bandwidth allocation policy associated with network address
US7072299B2 (en) * 2001-08-20 2006-07-04 International Business Machines Corporation Credit-based receiver using selected transmit rates and storage thresholds for preventing under flow and over flow-methods, apparatus and program products
KR100790131B1 (ko) * 2001-08-24 2008-01-02 삼성전자주식회사 패킷 통신시스템에서 매체 접속 제어 계층 엔터티들 간의 시그널링 방법
DE60213616T2 (de) * 2001-08-24 2007-08-09 Intel Corporation, Santa Clara Eine allgemeine eingabe-/ausgabearchitektur, protokoll und entsprechende verfahren zur umsetzung der flusssteuerung
US7062609B1 (en) * 2001-09-19 2006-06-13 Cisco Technology, Inc. Method and apparatus for selecting transfer types
US20030093632A1 (en) * 2001-11-12 2003-05-15 Intel Corporation Method and apparatus for sideband read return header in memory interconnect
KR100415115B1 (ko) * 2001-11-29 2004-01-13 삼성전자주식회사 통신시스템의 데이터 혼잡 통보 방법 및 장치
JP3912091B2 (ja) * 2001-12-04 2007-05-09 ソニー株式会社 データ通信システム、データ送信装置、データ受信装置、および方法、並びにコンピュータ・プログラム
WO2003063423A1 (en) * 2002-01-24 2003-07-31 University Of Southern California Pseudorandom data storage
US20030152096A1 (en) * 2002-02-13 2003-08-14 Korey Chapman Intelligent no packet loss networking
DE60205014T2 (de) * 2002-02-14 2005-12-29 Matsushita Electric Industrial Co., Ltd., Kadoma Verfahren zum Steuern der Datenrate in einem drahtlosen Paketdatenkommunikationssystem, Sender und Empfänger zu seiner Verwendung
US6970978B1 (en) * 2002-04-03 2005-11-29 Advanced Micro Devices, Inc. System and method for providing a pre-fetch memory controller
KR100429904B1 (ko) * 2002-05-18 2004-05-03 한국전자통신연구원 차등화된 ＱｏＳ 서비스를 제공하는 라우터 및 그것의고속 ＩＰ 패킷 분류 방법
US6963868B2 (en) * 2002-06-03 2005-11-08 International Business Machines Corporation Multi-bit Patricia trees
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7043599B1 (en) 2002-06-20 2006-05-09 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
US7408876B1 (en) * 2002-07-02 2008-08-05 Extreme Networks Method and apparatus for providing quality of service across a switched backplane between egress queue managers
US7051150B2 (en) * 2002-07-29 2006-05-23 Freescale Semiconductor, Inc. Scalable on chip network
US7124260B2 (en) 2002-08-26 2006-10-17 Micron Technology, Inc. Modified persistent auto precharge command protocol system and method for memory devices
US7143264B2 (en) * 2002-10-10 2006-11-28 Intel Corporation Apparatus and method for performing data access in accordance with memory access patterns
US7372814B1 (en) * 2003-02-27 2008-05-13 Alcatel-Lucent Network system with color-aware upstream switch transmission rate control in response to downstream switch traffic buffering
US7080217B2 (en) 2003-03-31 2006-07-18 Intel Corporation Cycle type based throttling
US6988173B2 (en) 2003-05-12 2006-01-17 International Business Machines Corporation Bus protocol for a switchless distributed shared memory computer system
US7167942B1 (en) 2003-06-09 2007-01-23 Marvell International Ltd. Dynamic random access memory controller
KR100807446B1 (ko) * 2003-06-18 2008-02-25 니폰덴신뎅와 가부시키가이샤 무선 패킷 통신방법 및 통신장치
US7342881B2 (en) * 2003-06-20 2008-03-11 Alcatel Backpressure history mechanism in flow control
US7277978B2 (en) * 2003-09-16 2007-10-02 Micron Technology, Inc. Runtime flash device detection and configuration for flash data management software
US7174441B2 (en) * 2003-10-17 2007-02-06 Raza Microelectronics, Inc. Method and apparatus for providing internal table extensibility with external interface
KR100526187B1 (ko) * 2003-10-18 2005-11-03 삼성전자주식회사 모바일 애드 혹 네트워크 환경에서 최적의 전송율을 찾기위한 조절 방법
US20050108501A1 (en) * 2003-11-03 2005-05-19 Smith Zachary S. Systems and methods for identifying unending transactions
US7420919B1 (en) * 2003-11-10 2008-09-02 Cisco Technology, Inc. Self converging communication fair rate control system and method
KR100560748B1 (ko) * 2003-11-11 2006-03-13 삼성전자주식회사 알피알 공평 메카니즘을 이용한 대역폭 할당 방법
US7451381B2 (en) * 2004-02-03 2008-11-11 Phonex Broadband Corporation Reliable method and system for efficiently transporting dynamic data across a network
JP4521206B2 (ja) * 2004-03-01 2010-08-11 株式会社日立製作所 ネットワークストレージシステム、コマンドコントローラ、及びネットワークストレージシステムにおけるコマンド制御方法
US7475174B2 (en) * 2004-03-17 2009-01-06 Super Talent Electronics, Inc. Flash / phase-change memory in multi-ring topology using serial-link packet interface
US20050210185A1 (en) * 2004-03-18 2005-09-22 Kirsten Renick System and method for organizing data transfers with memory hub memory modules
US20050223141A1 (en) * 2004-03-31 2005-10-06 Pak-Lung Seto Data flow control in a data storage system
JP2005318429A (ja) * 2004-04-30 2005-11-10 Sony Ericsson Mobilecommunications Japan Inc 再送制御方法及び無線通信端末
US20060056308A1 (en) * 2004-05-28 2006-03-16 International Business Machines Corporation Method of switching fabric for counteracting a saturation tree occurring in a network with nodes
US7984179B1 (en) * 2004-06-29 2011-07-19 Sextant Navigation, Inc. Adaptive media transport management for continuous media stream over LAN/WAN environment
CN100502531C (zh) * 2004-07-13 2009-06-17 Ut斯达康通讯有限公司 无线基站系统中无线信号的分组传输方法
US7441087B2 (en) * 2004-08-17 2008-10-21 Nvidia Corporation System, apparatus and method for issuing predictions from an inventory to access a memory
US7433363B2 (en) 2004-08-23 2008-10-07 The United States Of America As Represented By The Secretary Of The Navy Low latency switch architecture for high-performance packet-switched networks
US7660245B1 (en) * 2004-09-16 2010-02-09 Qualcomm Incorporated FEC architecture for streaming services including symbol-based operations and packet tagging
US7340582B2 (en) * 2004-09-30 2008-03-04 Intel Corporation Fault processing for direct memory access address translation
TWI254849B (en) * 2004-10-13 2006-05-11 Via Tech Inc Method and related apparatus for data error checking
US7830801B2 (en) * 2004-10-29 2010-11-09 Broadcom Corporation Intelligent fabric congestion detection apparatus and method
US7859996B2 (en) * 2004-10-29 2010-12-28 Broadcom Corporation Intelligent congestion feedback apparatus and method
US20060143678A1 (en) * 2004-12-10 2006-06-29 Microsoft Corporation System and process for controlling the coding bit rate of streaming media data employing a linear quadratic control technique and leaky bucket model
US7702742B2 (en) * 2005-01-18 2010-04-20 Fortinet, Inc. Mechanism for enabling memory transactions to be conducted across a lossy network
US7877566B2 (en) 2005-01-25 2011-01-25 Atmel Corporation Simultaneous pipelined read with multiple level cache for improved system performance using flash technology
US8085755B2 (en) * 2005-04-01 2011-12-27 Cisco Technology, Inc. Data driven route advertisement
US7987306B2 (en) * 2005-04-04 2011-07-26 Oracle America, Inc. Hiding system latencies in a throughput networking system
US7743183B2 (en) * 2005-05-23 2010-06-22 Microsoft Corporation Flow control for media streaming
TWI305890B (en) 2005-05-27 2009-02-01 Darfon Electronics Corp Button mechanism
US8027256B1 (en) * 2005-06-02 2011-09-27 Force 10 Networks, Inc. Multi-port network device using lookup cost backpressure
DE102005035207A1 (de) * 2005-07-27 2007-02-01 Siemens Ag Verfahren und Vorrichtung zur Datenübertragung zwischen zwei relativ zueinander bewegten Komponenten
JP2009503743A (ja) * 2005-08-03 2009-01-29 サンディスク コーポレイション データファイルを直接記憶するメモリブロックの管理
US7630307B1 (en) * 2005-08-18 2009-12-08 At&T Intellectual Property Ii, Lp Arrangement for minimizing data overflow by managing data buffer occupancy, especially suitable for fibre channel environments
US8291295B2 (en) 2005-09-26 2012-10-16 Sandisk Il Ltd. NAND flash memory controller exporting a NAND interface
US7652922B2 (en) * 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US7961621B2 (en) * 2005-10-11 2011-06-14 Cisco Technology, Inc. Methods and devices for backward congestion notification
US8149846B2 (en) * 2005-11-10 2012-04-03 Hewlett-Packard Development Company, L.P. Data processing system and method
US7698498B2 (en) 2005-12-29 2010-04-13 Intel Corporation Memory controller with bank sorting and scheduling
WO2007095551A2 (en) * 2006-02-13 2007-08-23 Digital Fountain, Inc. Fec streaming with aggregation of concurrent streams for fec computation
US7617437B2 (en) * 2006-02-21 2009-11-10 Freescale Semiconductor, Inc. Error correction device and method thereof
KR100695435B1 (ko) 2006-04-13 2007-03-16 주식회사 하이닉스반도체 반도체 메모리 소자
US7756028B2 (en) * 2006-04-27 2010-07-13 Alcatel Lucent Pulsed backpressure mechanism for reduced FIFO utilization
WO2008013528A1 (en) * 2006-07-25 2008-01-31 Thomson Licensing Recovery from burst packet loss in internet protocol based wireless networks using staggercasting and cross-packet forward error correction
US8407395B2 (en) * 2006-08-22 2013-03-26 Mosaid Technologies Incorporated Scalable memory system
US7739576B2 (en) * 2006-08-31 2010-06-15 Micron Technology, Inc. Variable strength ECC
EP2084864A1 (en) * 2006-10-24 2009-08-05 Medianet Innovations A/S Method and system for firewall friendly real-time communication
US7818489B2 (en) 2006-11-04 2010-10-19 Virident Systems Inc. Integrating data from symmetric and asymmetric memory
JP2008123330A (ja) * 2006-11-14 2008-05-29 Toshiba Corp 不揮発性半導体記憶装置
US7818389B1 (en) * 2006-12-01 2010-10-19 Marvell International Ltd. Packet buffer apparatus and method
US9116823B2 (en) * 2006-12-06 2015-08-25 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for adaptive error-correction coding
KR101364443B1 (ko) 2007-01-31 2014-02-17 삼성전자주식회사 메모리 시스템, 이 시스템을 위한 메모리 제어기와 메모리,이 시스템의 신호 구성 방법
US7596643B2 (en) * 2007-02-07 2009-09-29 Siliconsystems, Inc. Storage subsystem with configurable buffer
US8693406B2 (en) * 2007-08-09 2014-04-08 Intel Corporation Multi-user resource allocation and medium access control (MAC) overhead reduction for mobile worldwide interoperability for microwave access (WiMAX) systems
US7937631B2 (en) * 2007-08-28 2011-05-03 Qimonda Ag Method for self-test and self-repair in a multi-chip package environment
JP4564520B2 (ja) * 2007-08-31 2010-10-20 株式会社東芝 半導体記憶装置およびその制御方法
US7769015B2 (en) 2007-09-11 2010-08-03 Liquid Computing Corporation High performance network adapter (HPNA)
US7821939B2 (en) * 2007-09-26 2010-10-26 International Business Machines Corporation Method, system, and computer program product for adaptive congestion control on virtual lanes for data center ethernet architecture
US8130649B2 (en) * 2007-10-18 2012-03-06 Alcatel Lucent Ingress traffic flow control in a data communications system
US8305991B1 (en) * 2007-11-14 2012-11-06 Sprint Spectrum L.P. Method and system for sector switching during packet transmission
US7870351B2 (en) * 2007-11-15 2011-01-11 Micron Technology, Inc. System, apparatus, and method for modifying the order of memory accesses
US8762620B2 (en) * 2007-12-27 2014-06-24 Sandisk Enterprise Ip Llc Multiprocessor storage controller
US8120990B2 (en) 2008-02-04 2012-02-21 Mosaid Technologies Incorporated Flexible memory operations in NAND flash devices
US8355336B2 (en) * 2008-02-13 2013-01-15 Qualcomm Incorporated Methods and apparatus for formatting headers in a communication frame
JP5141606B2 (ja) * 2008-03-26 2013-02-13 セイコーエプソン株式会社 印刷装置
US8724636B2 (en) * 2008-03-31 2014-05-13 Qualcomm Incorporated Methods of reliably sending control signal
EP2279576A4 (en) * 2008-04-24 2012-02-01 Ericsson Telefon Ab L M ERROR RATE MANAGEMENT
US8374986B2 (en) * 2008-05-15 2013-02-12 Exegy Incorporated Method and system for accelerated stream processing
US8223796B2 (en) * 2008-06-18 2012-07-17 Ati Technologies Ulc Graphics multi-media IC and method of its operation
US8542588B2 (en) * 2008-06-25 2013-09-24 Qualcomm Incorporated Invoking different wireless link rate selection operations for different traffic classes
KR101431760B1 (ko) * 2008-06-25 2014-08-20 삼성전자주식회사 Ｅｃｃ 알고리즘을 이용한 플래시 메모리 장치 및 그구동방법
US7937419B2 (en) * 2008-06-26 2011-05-03 Tatu Ylonen Oy Garbage collection via multiobjects
US8547846B1 (en) * 2008-08-28 2013-10-01 Raytheon Bbn Technologies Corp. Method and apparatus providing precedence drop quality of service (PDQoS) with class-based latency differentiation
KR101003102B1 (ko) * 2008-09-24 2010-12-21 한국전자통신연구원 멀티 프로세싱 유닛에 대한 메모리 매핑방법, 및 장치
JP5659791B2 (ja) * 2008-10-09 2015-01-28 日本電気株式会社 コンテンツ配信システム、コンテンツ配信方法及びプログラム
US8402190B2 (en) * 2008-12-02 2013-03-19 International Business Machines Corporation Network adaptor optimization and interrupt reduction
US20100161938A1 (en) * 2008-12-23 2010-06-24 Marco Heddes System-On-A-Chip Supporting A Networked Array Of Configurable Symmetric Multiprocessing Nodes
US8737374B2 (en) * 2009-01-06 2014-05-27 Qualcomm Incorporated System and method for packet acknowledgment
JP5168166B2 (ja) * 2009-01-21 2013-03-21 富士通株式会社 通信装置および通信制御方法
EP2214100A1 (en) * 2009-01-30 2010-08-04 BRITISH TELECOMMUNICATIONS public limited company Allocation of processing tasks
JP5342658B2 (ja) * 2009-03-06 2013-11-13 アスペラ，インク． Ｉ／ｏ駆動の速度適応のための方法およびシステム
TWI384810B (zh) 2009-05-07 2013-02-01 Etron Technology Inc 可節省通用串列匯流排協定中用來儲存封包之記憶體之資料傳輸方法及其裝置
US8880716B2 (en) * 2009-05-08 2014-11-04 Canon Kabushiki Kaisha Network streaming of a single data stream simultaneously over multiple physical interfaces
CN101924603B (zh) * 2009-06-09 2014-08-20 华为技术有限公司 数据传输速率的自适应调整方法、装置及系统
US20110035540A1 (en) * 2009-08-10 2011-02-10 Adtron, Inc. Flash blade system architecture and method
US8238244B2 (en) * 2009-08-10 2012-08-07 Micron Technology, Inc. Packet deconstruction/reconstruction and link-control
US8281065B2 (en) * 2009-09-01 2012-10-02 Apple Inc. Systems and methods for determining the status of memory locations in a non-volatile memory
US8543893B2 (en) * 2009-09-02 2013-09-24 Agere Systems Llc Receiver for error-protected packet-based frame
FR2949931B1 (fr) * 2009-09-10 2011-08-26 Canon Kk Procedes et dispositifs de transmission d'un flux de donnees, produit programme d'ordinateur et moyen de stockage correspondants.
US8966110B2 (en) 2009-09-14 2015-02-24 International Business Machines Corporation Dynamic bandwidth throttling
US8312187B2 (en) * 2009-09-18 2012-11-13 Oracle America, Inc. Input/output device including a mechanism for transaction layer packet processing in multiple processor systems
JP5404798B2 (ja) * 2009-09-21 2014-02-05 株式会社東芝 仮想記憶管理装置及び記憶管理装置
JP2013506917A (ja) * 2009-09-30 2013-02-28 サンプリファイ システムズ インコーポレイテッド 圧縮及び復元を用いたマルチ・プロセッサの波形データ交換の改善
US9477636B2 (en) 2009-10-21 2016-10-25 Micron Technology, Inc. Memory having internal processors and data communication methods in memory
US8719516B2 (en) * 2009-10-21 2014-05-06 Micron Technology, Inc. Memory having internal processors and methods of controlling memory access
US8281218B1 (en) * 2009-11-02 2012-10-02 Western Digital Technologies, Inc. Data manipulation engine
US9081501B2 (en) * 2010-01-08 2015-07-14 International Business Machines Corporation Multi-petascale highly efficient parallel supercomputer
US8183452B2 (en) * 2010-03-23 2012-05-22 Yamaha Corporation Tone generation apparatus
US8321753B2 (en) 2010-04-13 2012-11-27 Juniper Networks, Inc. Optimization of packet buffer memory utilization
CN101883446B (zh) * 2010-06-28 2014-03-26 华为终端有限公司 一种sd控制芯片及数据通信方法
US8680886B1 (en) * 2010-05-13 2014-03-25 Altera Corporation Apparatus for configurable electronic circuitry and associated methods
US8295292B2 (en) * 2010-05-19 2012-10-23 Telefonaktiebolaget L M Ericsson (Publ) High performance hardware linked list processors
US20110299589A1 (en) * 2010-06-04 2011-12-08 Apple Inc. Rate control in video communication via virtual transmission buffer
US8539311B2 (en) * 2010-07-01 2013-09-17 Densbits Technologies Ltd. System and method for data recovery in multi-level cell memories
KR101719395B1 (ko) * 2010-07-13 2017-03-23 샌디스크 테크놀로지스 엘엘씨 백-엔드 메모리 시스템 인터페이스를 동적으로 최적화하는 방법
US20120192026A1 (en) * 2010-07-16 2012-07-26 Industrial Technology Research Institute Methods and Systems for Data Transmission Management Using HARQ Mechanism for Concatenated Coded System
US8751903B2 (en) 2010-07-26 2014-06-10 Apple Inc. Methods and systems for monitoring write operations of non-volatile memory
CN103229155B (zh) 2010-09-24 2016-11-09 德克萨斯存储系统股份有限公司 高速内存系统
US10397823B2 (en) * 2010-10-01 2019-08-27 Signify Holding B.V. Device and method for scheduling data packet transmission in wireless networks
EP2447842A1 (en) * 2010-10-28 2012-05-02 Thomson Licensing Method and system for error correction in a memory array
US8842536B2 (en) * 2010-12-23 2014-09-23 Brocade Communications Systems, Inc. Ingress rate limiting
JP2012150152A (ja) * 2011-01-17 2012-08-09 Renesas Electronics Corp データ処理装置及び半導体装置
WO2012129191A2 (en) * 2011-03-18 2012-09-27 Fusion-Io, Inc. Logical interfaces for contextual storage
JP5800565B2 (ja) 2011-05-11 2015-10-28 キヤノン株式会社 データ転送装置及びデータ転送方法
KR20130021865A (ko) * 2011-08-24 2013-03-06 삼성전자주식회사 이동통신 시스템의 고정자원 할당 방법 및 장치
US8832331B2 (en) * 2011-08-29 2014-09-09 Ati Technologies Ulc Data modification for device communication channel packets
WO2013048493A1 (en) * 2011-09-30 2013-04-04 Intel Corporation Memory channel that supports near memory and far memory access
US8588221B2 (en) * 2011-10-07 2013-11-19 Intel Mobile Communications GmbH Method and interface for interfacing a radio frequency transceiver with a baseband processor
US20130094472A1 (en) * 2011-10-14 2013-04-18 Qualcomm Incorporated Methods and apparatuses for reducing voice/data interruption during a mobility procedure
US8793543B2 (en) * 2011-11-07 2014-07-29 Sandisk Enterprise Ip Llc Adaptive read comparison signal generation for memory systems
US8954822B2 (en) * 2011-11-18 2015-02-10 Sandisk Enterprise Ip Llc Data encoder and decoder using memory-specific parity-check matrix
US9048876B2 (en) * 2011-11-18 2015-06-02 Sandisk Enterprise Ip Llc Systems, methods and devices for multi-tiered error correction
US9740484B2 (en) * 2011-12-22 2017-08-22 Intel Corporation Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage
TW201346572A (zh) 2012-01-27 2013-11-16 Marvell World Trade Ltd 發送器設備及發送器系統
EP2815529B1 (en) * 2012-02-17 2019-12-11 Samsung Electronics Co., Ltd. Data packet transmission/reception apparatus and method
US9135192B2 (en) 2012-03-30 2015-09-15 Sandisk Technologies Inc. Memory system with command queue reordering
US8694698B2 (en) * 2012-04-12 2014-04-08 Hitachi, Ltd. Storage system and method for prioritizing data transfer access
US9436625B2 (en) * 2012-06-13 2016-09-06 Nvidia Corporation Approach for allocating virtual bank managers within a dynamic random access memory (DRAM) controller to physical banks within a DRAM
WO2014000172A1 (en) * 2012-06-27 2014-01-03 Qualcomm Incorporated Low overhead and highly robust flow control apparatus and method
US10034023B1 (en) * 2012-07-30 2018-07-24 Google Llc Extended protection of digital video streams
US9444751B1 (en) * 2012-08-03 2016-09-13 University Of Southern California Backpressure with adaptive redundancy
GB2505956B (en) * 2012-09-18 2015-08-05 Canon Kk Method and apparatus for controlling the data rate of a data transmission between an emitter and a receiver
US9215174B2 (en) * 2012-10-18 2015-12-15 Broadcom Corporation Oversubscription buffer management
US9418035B2 (en) * 2012-10-22 2016-08-16 Intel Corporation High performance interconnect physical layer
US9424228B2 (en) 2012-11-01 2016-08-23 Ezchip Technologies Ltd. High performance, scalable multi chip interconnect
US8713311B1 (en) 2012-11-07 2014-04-29 Google Inc. Encryption using alternate authentication key
US9438511B2 (en) * 2012-12-11 2016-09-06 Hewlett Packard Enterprise Development Lp Identifying a label-switched path (LSP) associated with a multi protocol label switching (MPLS) service and diagnosing a LSP related fault
US9229854B1 (en) * 2013-01-28 2016-01-05 Radian Memory Systems, LLC Multi-array operation support and related devices, systems and software
US9652376B2 (en) * 2013-01-28 2017-05-16 Radian Memory Systems, Inc. Cooperative flash memory control
KR20140100008A (ko) * 2013-02-05 2014-08-14 삼성전자주식회사 휘발성 메모리 장치의 구동 방법 및 휘발성 메모리 장치의 테스트 방법
US9569612B2 (en) * 2013-03-14 2017-02-14 Daniel Shawcross Wilkerson Hard object: lightweight hardware enforcement of encapsulation, unforgeability, and transactionality
US9030771B2 (en) * 2013-04-26 2015-05-12 Oracle International Corporation Compressed data verification
WO2014205119A1 (en) * 2013-06-18 2014-12-24 The Regents Of The University Of Colorado, A Body Corporate Software-defined energy communication networks
US9967778B2 (en) * 2013-06-19 2018-05-08 Lg Electronics Inc. Reception method of MTC device
KR102123439B1 (ko) * 2013-11-20 2020-06-16 삼성전자 주식회사 이동 망에서 비디오 트래픽의 사용자 만족도 최적화를 고려한 혼잡 완화 방법 및 그 장치
GB2520724A (en) * 2013-11-29 2015-06-03 St Microelectronics Res & Dev Debug circuitry
US9699079B2 (en) * 2013-12-30 2017-07-04 Netspeed Systems Streaming bridge design with host interfaces and network on chip (NoC) layers
JP6249403B2 (ja) * 2014-02-27 2017-12-20 国立研究開発法人情報通信研究機構 光遅延線及び電子バッファ融合型光パケットバッファ制御装置
US9813815B2 (en) * 2014-05-20 2017-11-07 Gn Hearing A/S Method of wireless transmission of digital audio
KR102310580B1 (ko) * 2014-10-24 2021-10-13 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US9740646B2 (en) * 2014-12-20 2017-08-22 Intel Corporation Early identification in transactional buffered memory
US9185045B1 (en) * 2015-05-01 2015-11-10 Ubitus, Inc. Transport protocol for interactive real-time media
US10003529B2 (en) * 2015-08-04 2018-06-19 Telefonaktiebolaget Lm Ericsson (Publ) Method and system for memory allocation in a software-defined networking (SDN) system
KR102525295B1 (ko) * 2016-01-06 2023-04-25 삼성전자주식회사 데이터 관리 방법 및 장치
KR102589410B1 (ko) * 2017-11-10 2023-10-13 삼성전자주식회사 메모리 장치 및 그의 파워 제어 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102754088A (zh) * 2009-12-07 2012-10-24 桑迪士克科技股份有限公司 用于在非易失性存储器阵列中的同时后台和前台操作的方法和系统

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