CN106471460B - 用于在存储器系统中分割数据结构的系统及方法 - Google Patents

用于在存储器系统中分割数据结构的系统及方法 Download PDF

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CN106471460B
CN106471460B CN201580035967.6A CN201580035967A CN106471460B CN 106471460 B CN106471460 B CN 106471460B CN 201580035967 A CN201580035967 A CN 201580035967A CN 106471460 B CN106471460 B CN 106471460B
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memory
memory assembly
library
virtual library
assembly
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CN106471460A (zh
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J·托马斯·帕夫洛夫斯基
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Micron Technology Inc
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Abstract

本发明涉及一种存储器装置(14)，其可包含存储数据的存储器组件(24、26、28)及处理器(22)。所述处理器(22)可基于与所述存储器组件(24、26、28)相关联的一或多个性质及所述存储器组件(24、26、28)的预期随机存取速率而在所述存储器组件(24、26、28)中映射一或多个库(35)或一或多个虚拟库(36)。

Description

用于在存储器系统中分割数据结构的系统及方法
相关申请案的交叉参考
本申请案是主张2014年6月2日申请的标题为“用于可扩展存储器系统协议的系统及方法(Systems and Methods for a Scalable Memory System Protocol)”的第62/006,668号美国临时专利申请案的优先权的非临时申请案，所述美国临时专利申请案以引用的方式并入本文中。
技术领域
本发明大体上涉及一种用于改进可使用存储器装置执行数据操作(例如，读取、写入)的速率的存储器系统。更具体来说，本发明涉及用于改进存储器系统响应于对存储器系统进行存取的请求的速率的系统及技术。
背景技术
本章节希望向读者介绍可能与本发明的各种方面相关的本领域的各种方面，所述方面在下文中描述及/或主张。据信，此论述有助于为读者提供背景信息以促进更好地理解本发明的各种方面。因此，应理解，这些陈述应在此背景下阅读且并非作为现有技术的认可。
通常，低能力(例如，低请求速率)存储器类型(例如动态随机存取存储器(DRAM)组件)与高能力(例如，高请求速率)存储器(例如静态随机存取存储器(SRAM)组件)相比可能相对廉价。因而，可基于存储器类型的相应能力对特定存储器类型执行特定数据操作(例如，读取、写入)。例如，对于涉及多个动作的大型复杂数据操作，使用SRAM组件来保证与在使用DRAM组件执行相同数据操作时相比，数据操作被更快速地执行可能是有利的。虽然SRAM组件可用于有效地执行所请求数据操作，但是SRAM组件通常归因于成本考虑而在存储器装置中受限。因而，使用较小能力存储器组件或其它存储器类型来按类似于或高于高能力存储器组件的速率执行操作可能是有利的。
附图说明
在阅读以下详细描述及在参考图式时可更好地理解本发明的各种方面，其中：
图1说明根据实施例的计算系统的实例的框图；
图2说明根据实施例的可作为图1的计算系统的部分的存储器装置的实例的框图；
图3说明根据实施例的可包含若干存储器层的实例三维堆叠式存储器组件的俯视图；
图4说明根据实施例的图3的存储器组件的物理层的示意图；
图5说明根据实施例的组成图3的存储器组件的一部分的物理层的实例虚拟库的示意图；
图6说明根据实施例的映射到虚拟库的四个数据结构的框图；
图7说明根据实施例的用于确定将在图3的存储器装置的存储器组件中形成的虚拟库的数目的方法的流程图；
图8说明根据实施例的存储器组件的实例数据结构的框图；
图9说明根据实施例的图4的数据结构的分割版本的框图；
图10说明根据实施例的用于基于优选队列深度确定将在图2的存储器装置的存储器组件中形成的虚拟库的数目的方法的流程图；及
图11说明根据实施例的相对于各种队列深度的虚拟库的数目的对数图。
具体实施方式
下文将描述一或多个特定实施例。为了提供这些实施例的简洁描述，本说明书中未描述实际实施方案的所有特征。应了解，在任何此实际实施方案的研发中，如在任何工程或设计项目中，必须作出许多实施方案特定决策以实现可随实施方案的变化而变化的研发者的特定目标，例如符合系统相关及业务相关的限制。此外，应了解，此研发努力可能是复杂且耗时的，但对于受益于本发明的一般技术人员来说，所述研发努力仍将是常规设计、制作及制造任务。
一般来说，不同的存储器类型具有不同能力。即，不同的存储器类型可比其它存储器类型更有效地执行某些类型的功能。例如，DRAM存储器类型可能无法像SRAM存储器一样快地执行功能。在某些实施例中，存储器系统可将DRAM的部分映射为虚拟库，且使用虚拟库同时执行多个操作。因而，可能已由SRAM个别地执行的操作现可使用DRAM执行。通过在DRAM的虚拟库中同时执行这多个操作，使用虚拟库的存储器系统可提供在使用较低请求速率存储器(DRAM)的同时，使用高请求速率存储器(如SRAM)的错觉。因此，较高能力存储器(如SRAM)可被保留用于执行其它过程。有关在各种存储器类型中映射虚拟库以执行更有效操作的额外细节将在下文更详细描述。
使用可扩展协议的计算及存储器系统
通过介绍，图1说明可包含存储器装置的计算系统10的框图，所述存储器装置可根据本文中描述的技术在存储器组件中映射虚拟库。计算系统10可为多种计算装置中的任何者，例如计算机、传呼机、蜂窝电话、个人记事簿、控制电路等等。计算系统10可包含芯片上主机系统(SoC)12，芯片上主机系统(SoC)12可耦合到若干存储器装置14。主机SoC 12可为集成电路(IC)，其将计算机或其它电子系统的所有组件集成到单个芯片中。因而，主机SoC12可包含一或多个处理器，例如微处理器，所述一或多个处理器可控制计算系统10中的系统功能及请求的处理。如本文中使用，处理器可包含能够在对应电装置上执行可执行指令的任何适当处理器。
如上所述，主机SoC 12可耦合到存储器装置14。在某些实施例中，主机SoC 12可经由通道16耦合到存储器装置14。通道16可包含总线、电布线或类似物。
图2描绘存储器装置14的实施例的框图。存储器装置14可包含经设计以留存数字数据的任何电存储装置。存储器装置14可涵盖各种各样的存储器组件，其包含易失性存储器及非易失性存储器。易失性存储器可包含动态随机存取存储器(DRAM)及/或静态随机存取存储器(SRAM)。此外，易失性存储器可包含若干存储器模块，例如单列直插存储器模块(SIMM)或双列直插存储器模块(DIMM)。
非易失性存储器可包含将结合易失性存储器使用的只读存储器(ROM)，例如EPROM及/或快闪存储器(例如，NAND)。此外，非易失性存储器可包含高容量存储器，例如磁带或磁盘驱动器存储器。如将了解，易失性存储器或非易失性存储器可被视为用于存储代码(例如，指令)的非暂时性有形机器可读媒体。
如图2中所展示，在某些实施例中，存储器装置14可包含芯片上系统(SoC)22，芯片上系统(SoC)22可为存储器中处理器(PIM)或计算机处理器(CPU)，其紧紧地耦合到存储于存储器装置14上的存储器组件。通常，存储器SoC 22可与存储器装置14的存储器组件处在相同硅芯片上。通过将处理组件及存储器组件合并到存储器装置14中，存储器SoC 22可管理在存储器组件与主机SoC 12之间传输及接收数据请求及响应的方式。在某些实施例中，存储器SoC 22可控制存储器组件之间的业务以减小延时及增大带宽。如将了解，在根据本文中描述的实施例控制存储器组件与其它装置之间的传输时，主机SoC 12及存储器SoC 22可采用可扩展存储器系统协议。因而，可扩展存储器系统协议可在存储器装置14与主机SoC12之间的通道16，以及在存储器组件与存储器SoC22之间的通道29上操作。
在某些实施例中，存储器装置14还可包含缓冲器23。缓冲器23可存储由存储器SoC22接收到的一或多个封包。举例来说，存储器装置14可包含例如NAND存储器24、减小延时动态随机存取存储器(RLDRAM)26、双倍数据速率第四代同步动态随机存取存储器(DDR4)28及类似物的存储器类型。
在某些实施例中，主机SoC 12及存储器SoC 22可基于经由存储器组件、寄存器及类似物提供的计算机可执行指令执行各种操作。存储器组件或存储装置可为可充当用于存储处理器可执行代码、数据或类似物的媒体的任何适当制品。这些制品可代表计算机可读媒体(即，任何适当形式的存储器存储装置)，所述计算机可读媒体可存储由主机SoC12或存储器SoC 22使用来执行当前揭示技术的处理器可执行代码。存储器及存储装置也可用于存储数据、数据分析及类似物。存储器及存储装置可代表非暂时性计算机可读媒体(即，任何适当形式的存储器或存储装置)，所述非暂时性计算机可读媒体可存储由主机SoC 12或存储器SoC 22用于执行本文中描述的各种技术的处理器可执行代码。应注意，非暂时性仅指示媒体是有形的且并非是信号。
数据结构的高度分割
如上所述，可通过利用某些类型的存储器的能力以执行通常在其它类型的存储器上执行的操作而更有效地使用存储器装置。例如，如DRAM的低能力存储器类型与例如SRAM的高能力存储器相比可能相对廉价。虽然DRAM可能无法像SRAM一样快地执行功能，但是DRAM的可独立操作区域(IOR)(例如库)可用于同时执行可能已由SRAM个别地执行的多个操作。因而，在某些实施例中，存储器SoC 22可在存储器装置14内分割一或多个存储器组件的数据结构。即，存储器SoC 22可决定如何使用每一存储器组件的可用数据结构分布信息。应提及，如本文中论述，分割数据结构大体上涉及根据存储器组件中已存在的库将数据结构的部分映射到现存库的虚拟库中，及类似情况。如将了解，鉴于库在存储器组件内的相应数据结构，库可独立于彼此操作。以相同方式，在每一库中映射的虚拟库可取决于其中映射每一相应虚拟库的库而独立于彼此操作。在任何情况中，在确定存储器组件中的可用数据结构后，存储器SoC 22可将作为存储器组件的部分的不同数据结构映射到存储器组件的库或虚拟库中。因此，高度分割技术可允许具有高的库计数的廉价存储器，例如DRAM(即，具有比惯用DRAM多的库及被分割以作为惯用DRAM中不存在的虚拟库操作的可能库的DRAM)取代更昂贵且高能力的存储器，例如SRAM。
记住上述内容，存储器装置14中的每一存储器组件可包含特定数目个数据结构，所述数据结构在存储器组件最初制造时可作为所述存储器组件的部分。举例来说，存储器组件可为堆叠式装置，所述堆叠式装置包含可被分布到不同部分(例如室(vault)或库)的存储器的若干层。图3说明实例三维堆叠式存储器组件30的俯视图，三维堆叠存储器组件30可包含可能在制造时形成的若干存储器层。如图3中所展示，存储器组件30可包含耦合到其的若干链路31。通常，上文论述的通道29可包含一或多个链路31，且可提供对存储器组件30的存取。在所描绘的实施例中，每一链路31可包含三个进入通道及两个外出通道。
如上所述，存储器组件30可包含若干存储器层及逻辑层。例如，图4说明存储器组件30的示意图，存储器组件30具有八个存储器层32(例如，DRAM层1到8)及一个逻辑层33(例如，逻辑层0)。每一存储器层32可包含可用于存储数据的存储器位单元。逻辑层33可包含控制电路组件，所述控制电路组件可促进对存储器层32中的一者或多者及对外部接口的存取。
如上文论述，存储器组件30可在制造时经分割以提供存储器组件30的单独片段或IOR。在一个实例中，每一存储器层32可被分为大片段(例如，室)，所述大片段可被进一步分割为较小片段(例如，库)。根据本文中描述的技术，库可被进一步分割为虚拟库。图5说明上文论述的存储器组件30的一部分27的示意图。如图5中所展示，存储器组件30的部分27中的每一存储器层32可被分割为两个室34，且每一室34可被分割为两个库35。
应注意，图5说明有关链路31中的一者的逻辑及存储器堆叠的一部分27。在一个实施例中，对于整个存储器组件30，可能存在64个此类部分(例如，切片)。由于每一存储器层32被分割成两个室34，所以逻辑层33可包含两个控制逻辑部分38，其可控制到每一相应室34的数据流量。在所描绘的实施例中，每一个外部链路31说明两个室34。此配置可提供DRAM技术的内部速度能力的优化及其如何匹配到逻辑层33的外部速度能力。然而，应注意，在某些实施例中，每一室34可包含耦合到逻辑层的其自身的个别垂直总线(未展示)。在某些实施例中，每一链路31可经由逻辑层33对室34进行存取。因而，逻辑层33可提供对存储器层32中的任何者的存取。
记住这点，存储器SoC 22或任何其它适当装置可将库35进一步分割成虚拟库36，虚拟库36可用于提供存储器组件30的改进操作。即，在某些实施例中，存储器SoC 22将存储器层32的片段(例如，库35)的不同部分分配为单独的虚拟库36，虚拟库36可用于执行各种数据操作。
举例来说，图6说明可作为存储器组件30的部分的四个实例数据结构37。如将了解，使用本文中揭示的系统及技术，存储器SoC 22可将数据结构37映射到跨越库35分布的虚拟库36中。即，存储器组件30可包含已被分割为四个虚拟库36(虚拟库0到3)的六个库36(库0到5)。如图6中所说明，数据结构A及数据结构D是读取-修改-写入(RMW)结构，其被映射到数量为只读结构两倍的物理库中。即，与可各自跨越一个库35映射的只读结构相比，RMW结构的寄存器可各自跨越两个库35被映射。通过将每一结构映射到不同库35，存储器SoC22可改进存储器组件30处置多个请求的能力。举例来说，如果第一请求涉及对数据结构A的寄存器A0进行存取且第二请求涉及对数据结构A的寄存器A5进行存取，那么存储器SoC 22可能不针对第二请求提供对数据结构A的存取，直到第一请求已被处理为止。然而，如果数据结构37被映射到图6中所说明的虚拟库36中，那么由于寄存器A0及A5被映射到作为不同库35的部分的不同虚拟库36，所以存储器SoC 22可同时处理第一请求及第二请求，这是因为其两者对不同库35进行存取。
记住存储器组件30的实例分割结构，下文将使用网络设备实例描述使用存储器组件的高度分割的技术。然而，应注意，此相同方法也可在不存在清晰的数据结构时起作用。通常，如上所述，通过将可独立操作区域(IOR)(如DRAM库(例如，库35))放入寻址结构的低阶位中，与数据结构的分割相比，可实现相同系统操作效果。例如，如果DRAM自然存取是128位(16字节)，那么紧接在16B群组之前的地址位可引向下一IOR。因而，连续的随机事务可能进入与前一事务不同的IOR。
查看网络设备实例，在可支持因特网业务的高速路由器中，当封包被路由器接收时，可参考高达40个不同数据结构。如果传入数据的聚合线速率是400Gb/s，那么最小封包大小是512个位，且围绕封包的额外时间间隙导致封包持续时间为672个位，且所有封包为相同大小，那么封包速率是1.68ns或672个位/400Gb/s。一些结构可简单以每个封包被触摸(例如，读取或写入)一次，而其它结构可被触摸两次(例如，读取及写入)。因而，为了支持此线速率，存储器可支持2次触摸的随机存取速率1.68ns/2＝0.84ns，其可能难以使任何存储器支持此类型的随机存取。此外，可能难以设计DRAM以准许0.84ns的行循环时间(tRC)或将其扩展到甚至更小的tRC值。如本文中所使用，存储器组件的tRC是指存储器组件的存储器行完成完整循环(从行激活到有源行的预充电)所花费的最小时间量(例如，时钟循环)。
为了促进此类型的随机存取，由存储器SoC 22利用的个别DRAM的库计数的数目可经增大以提供足够数目的库来涵盖随机具有0.84ns的针对2次触摸的近似存取速率的应用程序的需要。为了确定个别DRAM的库计数的数目，存储器SoC 22可确定存储器组件的数据结构可用于根据优选随机存取请求速率实现成功系统操作的程度或量。通常，分割使用的数量可依据存储器组件的tRC对优选随机存取请求速率的比率。
记住上述内容，图7说明用于确定存储器SoC 22可选择以在存储器组件(例如，DRAM)中使用的最小数目个片段的方法40。如果存储器组件包含小于此最小数目个片段，那个存储器组件的片段可开始接收随机请求，所述随机请求将偶尔占用每一片段，同时到达且导致各种延迟。因而，在实践中，在执行方法40后实施的片段的数目可包含除所计算的最小值以外的一或多个片段。如本文中使用，片段是指存储器组件30中已存在的库35。片段还指如上文描述的由处理器映射的虚拟库36。在某些实施例中，存储器SoC 22可在使用相应存储器组件的不同片段之前执行下文描述的方法40。然而，应理解，方法40可由任何适当处理器执行。为论述目的，将参考虚拟库36描述方法40的以下描述，但是应理解，方法40也可参考作为存储器组件30的部分的库35执行。
在框42处，存储器SoC 22可接收预期被传输到存储器SoC 22的封包的预期随机存取速率。重新参考上文提出的实例，如果传入数据的聚合线速率是400Gb/s，那么最小封包大小是512个位(包含封包间间隙的672位等效物)，且所有封包为最小大小，那么每一接收到的封包的预期随机存取速率是大约1.68ns。假设每一封包包含2次触摸数据操作，那么针对每一接收到的封包的预期随机存取速率是大约0.84ns。
在框44处，存储器SoC 22可接收存储器组件的行循环时间(tRC)。如上文论述，存储器组件的tRC是指存储器组件的存储器行完成完整循环(从行激活到有源行的预充电)所花费的最小时间量(例如，时钟循环)。换句话来说，存储器组件的tRC可以是指存储器组件中的数据结构(例如，库)在执行一个数据操作(例如，2次触摸操作)时可使用的时间量。
在框46处，存储器SoC 22可基于存储器组件的tRC对每一接收到的封包的预期随机存取速率的比率确定相应存储器组件中可使用的虚拟库的最小数目。如果在框44处接收的存储器组件的tRC是8.4ns，那么在上文实例中存储器组件的tRC对每一各接收到的封包的预期随机存取速率的比率是8.4:0.84或10比1。存储器组件的tRC与每一接收到的封包的预期随机存取速率之间的所得比率可对应于将在相应存储器组件中使用以适应每一接收到的封包的预期随机存取速率的最小数目个虚拟库。即，所得比率可识别相应存储器组件中在不添加封包到队列的情况下继续接收封包所需的虚拟库的数目。
如上所述，存储器组件30可在设计或制造存储器组件30时，被大体上分布到不同结构(例如，室34、库35)中。一个分布实例包含将存储器组件30划分为库35，如上文论述。库30可使用共享的独立行及列解码器、感测放大器及数据路径存取。
记住这点，在一些实施例中，存储器SoC 22可通过将库35划分为虚拟库36而使用较少资源来对存储器层35进行存取。即，存储器SoC 22可将库35的不同部分映射到若干虚拟库36中以使不同库35能独立操作。因而，逻辑层33的单独行解码器可用于对每一虚拟库36进行存取，但资源的一些共性仍可沿着相应数据路径及经由逻辑层33的列解码器存在。
与将不同库35映射到不同室34或不同存储器层32的部分中相比，通过将一个库35映射到虚拟库34中，存储器SoC 22可引致较少面积损失(例如，额外2到3％)。即，新请求可进入具有若干虚拟库36的此单个库35，且使用共享资源(例如，列解码器)对虚拟库中的每一者进行存取。因而，存储器SoC 22可按～4ns的列到列延迟时间(tCCD)的速率送达请求，所述延迟时间比整个库35的行循环时间(tRC)(例如，～35ns)快。虽然在一些情况中，tCCD速率可比数据路径能力(例如，可按1到2ns操作)慢，但是与常规系统相比，使用虚拟库36仍可在对存储器组件30进行存取时提供改进的速度。
重新参考框46，在确定将在相应存储器组件中使用的虚拟库的最小数目后，存储器SoC 22可开始将相应存储器组件中的一或多个数据结构映射到相应虚拟库36。应注意，通过将存储器组件30设计为具有更多库35，或将虚拟库36添加到库35，存储器组件30可使用额外硅区域，其可关联于更高成本及因此更高的每位成本。因此，如果存储器组件30的裸片大小恒定，那么较少位可在存储器组件30中可用。然而，本文中描述的映射过程不会实际导致任何存储器容量(例如，存储器位计数)损失减小。而是，本文中描述的映射技术可导致数据围绕存储器组件30散布。因而，额外逻辑可用于保持追踪使用中的存储器及空闲的存储器。
为了更好地说明分割存储器组件的益处，图8说明尚未被分割成虚拟库36的存储器组件的实例数据结构60。如图8中所展示，数据结构60包含16个存储器地址62。当封包请求被具有数据结构60的相应存储器组件接收时，封包请求的对应数据操作可能导致数据结构无法被存储器组件30的tRC获得。即，举例来说，如果第一封包请求包含针对数据结构60的元素3的请求，且第二封包请求包含针对元素16的请求，那么第二封包请求无法被执行，直到第一封包请求已被完成或直到存储器组件的tRC已通过为止。如果当第二请求封包正在试图对数据结构60进行存取时，存储器组件的tRC尚未通过，那么存储器SoC 22可被放置在针对相应数据结构60的队列中。
图9说明具有虚拟库72、74、76及78的分割数据结构70。在一个实施例中，数据结构70的每一输入项可基于虚拟库36的数目按循环方式编号。例如，取代如图8的数据结构60中所展示按时间顺序对每一存储器地址编号，将元素1映射到虚拟库72、将元素2映射到虚拟库74、将元素3映射到虚拟库76、将元素4映射到虚拟库78、将元素5映射到虚拟库72，且以此类推。
记住上述内容，当将上文提出的实例应用于图9的分割数据结构70时，分割数据结构70的值将变得明显。即，如果第一封包请求包含针对分割数据结构70的元素3的请求，那么存储器SoC 22可提供对分割数据结构70的虚拟库76的存取。由于每一分割数据结构是相同存储器组件的部分，所以每一虚拟库的tRC对应于存储器组件的tRC。然而，与数据结构60不同，如果第二封包请求包含针对元素16的请求，那么存储器SoC22可提供对虚拟库78的存取，而不管第一封包请求是否已停止对虚拟库76进行存取。如将了解，由于虚拟库76及虚拟库78是独立于彼此，所以即使当虚拟库76忙于执行另一操作时，存储器SoC 22仍可提供对虚拟库78的存取。因而，与数据结构60相比，存储器组件使用分割数据结构70有效执行数据操作的能力随更多虚拟库产生而增大。
虽然图7的方法40可提供将在存储器组件30中形成的最小数目个虚拟库，但是在存储器组件30中增加额外虚拟库以补偿各种错误、非预期延迟、在队列中等待对存储器组件30进行存取的封包及类似物可能是有利的。举例来说，考虑针对1011个随机请求循环的上文描述的网络系统的模拟及假设每1.68ns可接收到请求的基线SRAM及无数据结构分割，队列深度(即，新请求在全管线化系统中等待答案的时间)针对仅具有1次触摸的操作可为1个封包。另一方面，针对具有2次触摸的操作，队列时间倾向于无限。即，当每一请求执行触摸两次时，SRAM无法跟上。由于每1.68ns，存储器组件可接收两次触摸请求(即使其在所述时间跨度内只能处理一次触摸操作)，所以队列深度在每一接收到的封包后增大，且倾向于无限。因而，此模拟系统无法如设计那样起作用。
现参考来自使用4向数据结构分割的上述实例的模拟的一些数据点，具有相对tRC＝2*请求速率的装置的最大队列延迟被模拟为12。对于相对tRC＝3x，最大队列延迟被模拟为31。基于相应存储器组件的各种性质，可能期望良好系统操作的最大队列延迟不大于大约15。因而，tRC＝2x是每个封包1次触摸结构的合理解决方案。对于2次触摸，tRC被有效翻番，这是因为需要2个操作，因此tRC＝2x将表现为tRC＝4x，其在此实例中将具有不可接受的长队列时间。
在64向分割中且假设tRC＝8.4ns(即，5x封包速率)，队列深度可被模拟为6，其对于每个封包1次触摸而言是可接受的。然而，在模拟每个封包2次触摸的tRC＝10x，队列深度可被模拟为9，其也可能是可接受的。因此，通过采用相应存储器组件的64个库(其可以5x封包速率循环)，即使在每个输入封包2次触摸存储器的情况下，存储器系统仍可跟上全线速率。
在tRC＝6x(即，在此实例中的10.08ns)的64向分割中，DRAM的对应类别可使用快速库循环技术，同时仍使用常规1T-1C DRAM单元及常规感测放大器建立。在此，队列针对1次触摸可为7，且针对2次触摸可为10，两者再次是可接受的。举例来说，如果40个数据结构的系统具有1次触摸(即，只读)结构的14个结构，且具有2次触摸(即，读取-修改-写入)结构的24个结构，那么针对14个只读结构中的每一者的16向分割可能涉及总共224个库。因而，在此实例中，队列将为13。其余26个结构可被赋予30向分割，由此消耗780个库35。在此，2次触摸队列可为14个。在此实例中涉及的库35的总数目接着可为224+780＝1,004。如果可用的库35的总数目是1,024，那么20个库35仍可用于其它功能。记住这点，如果系统使用8个DRAM来实现期望存储器容量及带宽，那么每一DRAM可使用128个库35，其可能比产业标准DRAM高，但按合理成本设计及建立仍可行。
虽然在此参考网络路由器描述数据结构的分割，但是应理解，本文中描述的技术也可用于其它类型的系统中。因而，上述实例不希望将当前揭示技术的范围限制为网络化。
记住上述内容，图10说明用于基于优选队列深度确定将在存储器组件中形成的虚拟库的数目的方法90。如上文参考图7所提及，为论述目的，将参考虚拟库36描述方法90的以下描述，但是应理解，方法90也可参考作为存储器组件30的部分的库35执行。
在一个实施例中，方法90可在根据方法40确定将在存储器组件中形成的虚拟库36的数目后执行。即，方法40可用于确定将在存储器组件30中映射的虚拟库36的最小数目，且接着方法90可用于微调或识别将在存储器组件30中映射的虚拟库36的数目以有效执行各种数据请求。
如同方法40，方法90的以下描述将被描述为由存储器组件SoC 22执行，但是应理解，任何适当处理器可执行方法90。此外，虽然方法90按特定顺序提出，但是应注意，方法90可按任何适当顺序执行。
现参考图10，在框92处，存储器SoC 22可接收优选队列深度。优选队列深度可基于在存储器组件被分割后可用的存储器量确定。通常，每一队列深度增量涉及在存储器组件中使用额外寄存器或额外存储器以存储排队的对应数据。因而，优选队列深度可与存储器组件中可用的存储器量相关。
应注意，存储器成本涉及增大存储器组件30可支持的队列深度的量。即增大存储器组件30的可用队列深度，涉及使用存储器组件30的更多寄存器来增大队列深度。然而，为了减小队列深度，存储器SoC 22可在存储器组件30内映射虚拟库36。然而，虚拟库36的映射仍增大存储器成本，且增加有关逻辑层33的控制逻辑成本以适应针对不同虚拟库36的不同队列。然而，与分割存储器组件30相比的未分割存储器组件30的相对较长队列深度对应于与使用具有虚拟库36所涉及的多个队列相比的较低系统性能。
在框94处，存储器SoC 22可基于针对存储器组件30的虚拟库36具有一定预期触摸率的随机业务确定在达到优选队列深度前执行的循环数目。在某些实施例中，虚拟库36的预期量可对应于方法40的结果。
使用针对使用方法40确定的最小数目个虚拟库36具有预期触摸率的随机业务，存储器SoC 22可执行存储器组件30从而接收特定数目个随机请求的模拟。在一个实施例中，存储器SoC 22可执行模拟，直到已达到优选队列深度。
举例来说，图11说明对数图110，其说明关于存储器组件30中存在的虚拟库36的数目，各种队列深度值在若干循环内发生时的情况。如对数图110中所展示，当存储器组件30被分割为4个虚拟库36时，在10,000个循环后达到2的最大队列深度。记住这点，在框94处，存储器SoC 22可使用模拟来确定预期在达到优选队列深度之前执行的循环的数目。
再次参考图10，在框96处，存储器SoC 22可确定循环数目是否大于某一阈值。在一个实施例中，阈值可与被模拟为业务的封包的预期封包错误率相关联。即，虽然由上文描述的方法40确定的虚拟库36的数目可提供足够数目的虚拟库36来执行与接收到的封包相关联的数据操作，但是所确定数目不考虑接收到的封包的封包错误率。任何封包可具有反映在错误可能发生之前执行的预期数目个循环的封包错误率。举例来说，封包错误率可为每109个循环1个错误。当封包发生错误时，封包被重新传输且存储器组件30的队列(例如，队列深度)可增大。
记住这点，且考虑作为模拟的部分的封包的随机业务，请求封包可在先前请求封包完成处理前重复到达相同虚拟库36。因而，请求封包可作为队列的部分被备份或存储于寄存器中。在某些实施例中，请求封包的积存可存储于存储器组件30前方的队列中。然而，队列的大小受限，这是因为用于在队列中保存封包的每一寄存器耗用存储器空间。某时，存储器空间将不再可用。如果队列资源被剔除的频率归因于封包错误而小于正常封包丢弃率，那么存储器组件30的操作中可能不存在任何可观测的损失。例如，如果封包在109次中丢弃1个，那么存储器组件30可被选择以包含足够的寄存器来支持在1012个请求中丢弃1个的队列或0.1％的正常封包丢弃率。因而，重新参考框96，在一些实施例中，阈值可比封包错误率大一定倍数。举例来说，如果1010个封包的一个封包丢弃，那么阈值可被设置为1012。
如果存储器SoC 22确定循环数目不大于阈值，那么存储器SoC 22可结束方法90，且用在框94处使用的虚拟库的数目继续进行。但是，如果存储器SoC 22确定循环数目大于阈值，那么存储器SoC 22可增大在存储器组件30中映射的虚拟库36的量，且在框98处，重复框94到98，直到达到优选队列深度的循环数目小于阈值。
虽然上文描述的方法90被描述为由存储器SoC 22执行，但是应注意，在某些实施例中，方法90可由独立于存储器装置14操作的处理器执行。即，与典型存储器SoC相比，执行方法90的处理器可具有额外处理力，以确定虚拟库36的量以更快地使用。然而，如果方法90由存储器SoC 22执行，那么应注意，存储器SoC 22可包含额外控制逻辑、计数器及随机数目产生器以有效执行方法90。
虽然本文中描述的实施例可具有各种修改及替代形式，但是特定实施例已在图式中通过实例展示且已在本文中予以详细描述。然而，应了解，本发明并不希望限于所揭示的特定形式。而是，本发明涵盖落于如由以下所附权利要求书定义的本发明的精神及范围内的所有修改、等效物及替代。

Claims (18)

1.一种存储器装置，其包括：
存储器组件，其经配置以存储数据；及
处理器，其经配置以基于与所述存储器组件相关联的一个或多个性质及所述存储器组件的预期随机存取速率而在所述存储器组件中映射一个或多个库或一个或多个虚拟库，其中基于所述一个或多个性质及所述预期随机存取速率确定所述一个或多个库的第一数目或所述虚拟库的第二数目，以及经由所述处理器，基于所述存储器组件的优选队列深度微调或识别将在所述存储器组件中产生的虚拟库的第三数目；其中经由所述处理器，基于所述优选队列深度微调或识别将在所述存储器组件中产生的虚拟库的所述第三数目包括：执行对所述存储器组件进行存取的多个随机请求的模拟及确定由所述处理器执行以达到所述优选队列深度的循环的数目。
2.根据权利要求1所述的存储器装置，其中所述存储器组件包括动态随机存取存储器或NAND存储器。
3.根据权利要求1所述的存储器装置，其中所述处理器经配置以经由所述虚拟库的两个不同虚拟库对所述存储器组件执行至少两个数据操作，其中所述至少两个数据操作的一部分被同时执行。
4.根据权利要求1所述的存储器装置，其中与所述存储器组件相关联的所述性质包括所述存储器组件的行循环时间。
5.根据权利要求1所述的存储器装置，其中所述预期随机存取速率是基于由所述处理器接收的请求的聚合线速率、所述请求中的每一请求的最小大小及由所述请求中的每一请求执行的触摸操作的类型而确定。
6.一种方法，其包括：
经由处理器，接收与对存储器组件进行存取相关联的预期随机存取速率；
经由所述处理器，接收与所述存储器组件相关联的行循环时间；
经由所述处理器，基于所述预期随机存取速率及所述行循环时间确定将在所述存储器组件中产生的库的第一数目或虚拟库的第二数目，以及基于所述存储器组件的优选队列深度微调或识别将在所述存储器组件中产生的虚拟库的第三数目；
其中经由所述处理器，基于所述优选队列深度微调或识别将在所述存储器组件中产生的虚拟库的所述第三数目包括：执行对所述存储器组件进行存取的多个随机请求的模拟及确定由所述处理器执行以达到所述优选队列深度的循环的数目；及
经由所述处理器，分别基于所述第一数目的库或所述第二数目的虚拟库在所述存储器组件中映射一个或多个库或一个或多个虚拟库，其中所述存储器组件中的所述一个或多个虚拟库中的每一虚拟库可基于所述存储器组件中的所述一个或多个虚拟库的位置独立存取。
7.根据权利要求6所述的方法，其中所述行循环时间包括所述存储器组件的存储器行完成完整循环的时间量。
8.根据权利要求6所述的方法，其中所述预期随机存取速率是基于与对所述存储器组件进行存取中的每一请求相关联的触摸的数目确定。
9.根据权利要求6所述的方法，其中确定将在所述存储器组件中产生的虚拟库的所述数目包括确定所述行循环时间对所述预期随机存取速率的比率。
10.根据权利要求6所述的方法，其包括经由所述处理器对所述一个或多个虚拟库的第一虚拟库进行存取，同时所述一个或多个虚拟库的第二虚拟库也被存取。
11.根据权利要求6所述的方法，其包括经由所述处理器将所述存储器组件的多个元素映射到所述存储器组件的所述一个或多个库或所述一个或多个虚拟库中的一个或多个元素。
12.一种有形的非暂时性机器可读媒体，其包括指令，所述指令经配置以：
接收与对存储器组件进行存取相关联的预期随机存取速率；
接收与所述存储器组件相关联的行循环时间；
基于所述预期随机存取速率及所述行循环时间确定将在所述存储器组件中产生的库的第一数目或虚拟库的第二数目；
接收所述存储器组件的优选队列深度，其中所述优选队列深度包括在队列中等待对所述存储器组件进行存取的包的数目；
基于将由所述存储器组件接收的多个随机包的预期触摸速率及所述存储器组件中的库的所述第一数目或虚拟库的所述第二数目确定达到所述优选队列深度的循环的数目，其中所述存储器组件中的所述第二数目的虚拟库中的每一虚拟库可基于所述存储器组件中的所述第二数目的虚拟库中的每一虚拟库的位置独立存取；及
基于循环的所述数目确定所述存储器组件中的库的第三数目或虚拟库的第四数目。
13.根据权利要求12所述的有形的非暂时性机器可读媒体，其中用于确定循环的所述数目的所述指令包括用于执行以下操作的指令：
执行由所述存储器组件针对所述第一数目的库或所述第二数目的虚拟库接收所述多个随机包的模拟；及
基于所述模拟确定循环的所述数目。
14.根据权利要求12所述的有形的非暂时性机器可读媒体，其中用于确定虚拟库的所述第四数目的所述指令包括用于执行以下操作的指令：
确定循环的所述数目是否超过阈值；及
当循环的所述数目超过所述阈值时，增加虚拟库的所述第二数目。
15.根据权利要求14所述的有形的非暂时性机器可读媒体，其中所述阈值与包错误率相关联。
16.根据权利要求15所述的有形的非暂时性机器可读媒体，其中所述包错误率包括在由所述存储器组件接收所述多个随机包的模拟期间在错误发生前执行的预期数目个循环。
17.根据权利要求14所述的有形的非暂时性机器可读媒体，其中所述阈值是包错误率的倍数。
18.根据权利要求12所述的有形的非暂时性机器可读媒体，其中所述存储器组件包括动态随机存取存储器或NAND存储器。
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