EP3064041B1 - Interface à branche d'émission améliorée - Google Patents

Interface à branche d'émission améliorée Download PDF

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Publication number
EP3064041B1
EP3064041B1 EP14783603.5A EP14783603A EP3064041B1 EP 3064041 B1 EP3064041 B1 EP 3064041B1 EP 14783603 A EP14783603 A EP 14783603A EP 3064041 B1 EP3064041 B1 EP 3064041B1
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EP
European Patent Office
Prior art keywords
optocoupler
bus
branch
interface according
transistor
Prior art date
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Active
Application number
EP14783603.5A
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German (de)
English (en)
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EP3064041A1 (fr
Inventor
Frank Lochmann
Markus SCHERTLER
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Tridonic GmbH and Co KG
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Tridonic GmbH and Co KG
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Publication of EP3064041A1 publication Critical patent/EP3064041A1/fr
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/20—Responsive to malfunctions or to light source life; for protection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/175—Controlling the light source by remote control
    • H05B47/18—Controlling the light source by remote control via data-bus transmission
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B44/00—Circuit arrangements for operating electroluminescent light sources
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/20—Controlling the colour of the light
    • H05B45/22—Controlling the colour of the light using optical feedback

Definitions

  • the present invention relates to an interface for bidirectional communication with an electronic operating device for at least one light source and a ballast with such an interface.
  • pamphlets show WO 2011/135098 A1 , WO 2013/153510 A1 and DE 101 13 367 C1 further examples for BUS interfaces.
  • Appropriate optocouplers U2, U1 are provided in the known circuit both for receiving DALI signals and for sending DALI signals, each forming part of a branch for sending or receiving. Both branches are fed from the common current source Q2, Q3, R3, R4. The circuit also has an energy store that 1 is shown as capacitor C2.
  • the well-known interface is designed for communication according to the DALI standard, in which a predetermined DC voltage is applied to the lines when the bus is inactive. This predetermined DC voltage is reduced only in the case of a signal transmission, while the constant DC voltage is applied when no signals are transmitted.
  • the capacitor C2 is charged by the DC voltage present on the bus. This makes sense here because when a signal is transmitted according to the DALI standard, the voltage present on the bus drops to (logical) zero or to the voltage that is defined for the low-level voltage. This can in Return channel (transmission branch) of the circuit can be recognized immediately.
  • Back channel refers to the channel away from the interface, other than the channel for the interface's transmit operation.
  • the “send branch” is the signal path of the interface used for sending signals.
  • DALI signals signals are to be received by the interface according to a protocol in which the voltage is zero (or very low compared to the DALI standard) when the bus is idle, it turns out that the known interface is not suitable for this is.
  • a protocol in which the voltage is zero (or very low compared to the DALI standard) when the bus is idle it turns out that the known interface is not suitable for this is.
  • An example of such a standard is the so-called DSI standard.
  • the reason for this is that, in contrast to the DALI standard, according to the DSI standard there is no voltage or low voltage when the bus is inactive (the "low level", i.e. the low value for the transmission of a first logical state, e.g. 0 , is specified to ⁇ 6.5 volts).
  • the voltage on the bus is only increased when a DSI signal is transmitted.
  • a DSI signal arrives at the connection for the control gear, i.e. on the secondary side, of the known interface, the voltage rises suddenly from the value for the first logic state, e.g. ⁇ 6.5 volts, to a predetermined DC voltage, e.g 10 - 15 volts (high level, i.e. the voltage value that is interpreted as the second logical value, eg 1). It is now necessary that the incoming signal is detected immediately to ensure reliable detection of the DSI signal. With DSI, transmission is Manchester-coded, ie a data bit is transmitted by changing from low level to high level (logical 0) or by changing from high level to low level (logical 1).
  • the capacitor C2 from the known circuit has a disruptive effect here, however, since the falling edge (logical 1) or the first bit of the DSI signal cannot be reliably recognized by the known interface.
  • capacitor C2 is partially charged as a result of the 2 mA input current source. If the bus voltage drops below 6.5 volts, capacitor C2 continues to be charged. As a result, current also flows in the optocoupler U2 of the receiving branch, so that the first logical state (e.g. 1) at the optocoupler output of optocoupler U2 cannot be recognized immediately after the voltage falls below 6.5 volts. The capacitor C2 is still partially charged even after falling below the low level and bridges the zener diode Z1 in the non- or partially charged state, which otherwise immediately interrupts the current flow in the optocoupler U2 if the zener voltage (low level) is fallen below.
  • the first logical state e.g. 1
  • the resistor can be connected between the energy store and the optocoupler.
  • the energy store and the resistor can be dimensioned in such a way that a discharge current flows during the transmission period of a digital bit, during which a connectable bus is short-circuited.
  • the edge duration of a digital bit that short-circuits a connectable bus can be less than 25 mS, preferably less than 15 ⁇ S.
  • the energy store can be charged from the current source without a charging current control element or via a charging current control transistor.
  • FIG. 2 shows a circuit arrangement.
  • a field effect transistor (FET, JFET) J1 and a resistor R7 form a current source J1, R7, which provides a charging current of a predetermined level to an energy store, which is referred to as capacitor C1 in the following by way of example.
  • FET field effect transistor
  • JFET field effect transistor
  • the current split is such that the charging current for the capacitor is less than the current through the optocoupler, preferably in a range from 30% to 70% of the optocoupler current.
  • the charging current for capacitor C1 is now picked up at the input of optocoupler Q3 of the receiving branch (see measuring point I between diode D6 and optocoupler Q3). So the capacitor is part of a path that is connected in parallel with a path that includes the primary side of the receive optocoupler Q3.
  • a falling edge of a DSI signal ie in particular the first bit of the DSI command (start bit, logical 1, coded with a falling edge)
  • start bit logical 1, coded with a falling edge
  • the capacitor C1 is not first discharged after the high level has been applied, it can be detected directly when the voltage drops to the low level.
  • a common power source can be used in the circuit according to the invention for the reverse channel and forward channel (receive/transmit branch).
  • the interface can also be used for signal reception according to the DALI standard. It is essential that the arrangement according to the invention enables incoming signals to be detected very quickly, even if the idle state of the bus voltage is close to 0 volts or 0 volts.
  • the circuit arrangement shown is designed in such a way that it counteracts the negative influence of a current source by using a large-sized capacitor (with a capacity of e.g. 1-6 ⁇ F), which is reduced from the current source with the FET J1 and the resistor R7 to approx .5 volts or more is charged.
  • a large-sized capacitor with a capacity of e.g. 1-6 ⁇ F
  • the drain-source capacitance of the FET J1 which, however, can be reduced by suitably dimensioning the capacitance at the gate.
  • FIG. 2 shows a schematic representation of the interface with a first primary-side control connection and a second primary-side control connection.
  • a DALI control device SDALI on the one hand and a mains button (not shown) on the other hand are coupled to the primary-side control input.
  • a resistor R1 is arranged in series with the first primary-side control connection.
  • a rectifier which includes four diodes D1 to D4, is coupled between the resistor R1 and the second primary-side control connection.
  • a switch X1 is coupled between a first and a second rectifier output connection, in particular its working electrode-reference electrode path.
  • a current source which includes two bipolar transistors Q1, Q2 and two ohmic resistors R2, R3, is also coupled to the rectifier output connection.
  • a first optocoupler Q3 is coupled to the output of the current source and is coupled in series with a zener diode D9.
  • a series circuit comprising a diode D6, the current source J1, R7 consisting of FET J1 and resistor R7, and a capacitor C1 is coupled in parallel with the zener diode D9.
  • a second optocoupler Q5 is supplied via the current source R7, J1.
  • the optocoupler Q3 in the reception branch can transfer signals via an output of the interface with a first and a second output connection, while the second optocoupler Q5 in the transmission branch is provided via a signal input with a first and a second signal connection for sending signals.
  • optocoupler Q5 is connected to the control electrode of switch X1, with a diode D13 and resistor R9 connected in series along this path.
  • a parallel connection of a capacitor C3 and a resistor R11 is coupled in parallel with the control electrode of the switch X1 and act as a noise filter.
  • Another bipolar transistor Q4 is coupled between the capacitor C3 and the resistor R11, the base of which is coupled to the higher-potential side of the resistor R11.
  • Capacitor C1 By using the current source J1, R7 to charge the capacitor C1 (this is essentially the same as Capacitor C2 of the known circuit) is then given full functionality even when transmitting signals according to the DSI standard, since charging of the capacitor C1 no longer takes place with a falling edge, but also according to the DALI standard.
  • the capacitor C1 is consequently always charged, which means that the zener diode D9 does not have to be bypassed by a non-charged or partially charged state with a falling edge.
  • the capacitor C1 After switching on the mains voltage and thus applying a direct voltage at a predetermined level according to the DALI standard (DALI On ), the capacitor C1 is charged to approx. 5.5 volts or more in around 400 milliseconds, so that after 600 milliseconds (this corresponds to the DALI standard) a response to a DALI signal can be sent from the time it is switched on.
  • the charging current is limited to 100 ⁇ A, for example, by the current source consisting of FET J1 and resistor R7. However, this value can also be higher or lower depending on the components used.
  • the optocoupler Q5 is always driven with a defined current, with the current through FET J1 being selected in such a way that in the event of a DSI signal being transmitted, it has an influence on the bit time, i.e. the time in which a bit is sent from the transmitter to the Receiver can be sent is small.
  • the circuits shown can be modified as follows. For example, if the control voltage for FET X1, i.e. the voltage at C1, is to be increased, an optocoupler Q5 with a control current of approx. 1 milliamps instead of eg 5 milliamps (mA) can be used. This can be, for example, an optocoupler of the type TLP621 or TLP624 from Toshiba.
  • the optocoupler current By reducing the optocoupler current to 1 milliamp, more current (e.g. 600 microamps) can be allowed to charge capacitor C1, allowing the voltage across C1 to reach its setpoint more quickly, and thus an even higher value at the time of transmit after 600 milliseconds Has.
  • the diodes D6 and D13 can be replaced by Schottky diodes, whereby the control voltage at the gate of the switch X1 can be increased by about 0.5 volts if necessary. This then makes it possible to use a smaller-sized FET X1.
  • the invention relates in particular to the improvement in terms of the signal shape and the signal repetition for digital bits to be transmitted in the transmission branch.
  • edges shown can be reduced edge sides (thus steeper edges) achieve. For example, edges with a duration of less than 25 ms, preferably even less than 15 ms, can be achieved.
  • these periods of time refer to the period of time until the edge of a transmission bit has pulled the bus potential to the lower potential, or the trailing edge of a transmission bit in turn allows the bus potential to rise from the low potential to the quiescent potential.
  • An optocoupler labeled 'DALIin' is shown on the right-hand side.
  • U90 left side of the optocoupler in figures
  • incoming signals are fed from the bus by means of a current source (the Darlington circuit Q90, Q95), which are then then transmitted by the optocoupler in an electrically isolated manner.
  • Q90, Q95 the Darlington circuit
  • further evaluation then follows by a control circuit in the operating device for lamps and the activation of the lamps according to the information received via the bus.
  • the digital signals to be transmitted by the control circuit of the operating device for lamps are applied to the primary side of the further (transmission-side) optocoupler DALIout, U91, and transmitted to the secondary side in an electrically isolated manner.
  • the secondary side then has a circuit that can selectively short-circuit the bus.
  • the portion of the circuit between the secondary side of the optocoupler U91 and the bus is powered by the bus voltage and the regulated current source Q90, Q95.
  • the current source Q90, Q95 fed from the bus voltage charges an electrical energy store, in the example shown the capacitor C94.
  • this charging occurs without a current regulator between the current source Q90, Q95 and the capacitor C94.
  • the transistor linear regulator shown above in the exemplary embodiments can also be present here.
  • the energy storage capacitor C94 and the ohmic resistor R100, which defines the discharge current, are tuned in such a way that the energy storage capacitor C94 is not yet fully discharged during the transmission period, i.e. during the short-circuiting of the bus voltage, and is therefore safe for the entire duration of the transmission bit (short-circuiting of the bus ) a constant discharge current flows through resistor R100 and the secondary side of optocoupler U91.
  • a switch Q96 is now provided in the receive branch which includes the receive optocoupler U90.
  • This switch Q96 can be, for example, a transistor, such as a bipolar transistor, in particular, as shown in the present example, a PNP bipolar transistor.
  • the transistor Q96 is connected at its base to a zener diode Z95.
  • the switch (transistor) Q96 When the voltage across the zener diode Z95 has reached the zener voltage (e.g. in 5.7V), the switch (transistor) Q96 is turned on (switched on) and thus allows current to flow on the primary side of the receiving-side optocoupler U90. As already described in connection with the previous exemplary embodiments, this current flow is fed by the current source R90, R91, Q90, Q95.
  • an energy storage element in particular a capacitor C95, is also connected in the path upstream of the Zener diode Z95. More specifically, this capacitor C95 is connected between the junction of the base of transistor Q95 below the cathode of diode Z95 and the junction of the emitter of transistor Q96 and the cathode of receive optocoupler U90. This capacitor C95 now causes a short delay in turning on transistor Q96 when there is sufficient voltage on the bus side.
  • the circuit block FB in figure 5 contains a two-stage circuit for adapting the edge steepness when transmitting, i.e. when driving transistor Q92, by means of which the bus lines can be selectively short-circuited.

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  • Dc Digital Transmission (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Claims (11)

  1. Interface de bus numérique pour un appareil permettant de faire fonctionner un moyen d'éclairage, dans laquelle :
    - l'interface présente une branche d'émission et une branche de réception,
    - la branche de réception présente une source de courant (R90, R91, Q90, Q95) qui peut être alimentée par un bus conduisant une tension en mode veille,
    - la source de courant (R90, R91, Q90, Q95) alimente au moins la branche d'émission en énergie et la branche d'émission présente un coupleur optoélectronique (U91),
    - la branche de réception présente un autre coupleur optoélectronique(U90),
    - un transistor (Q96) est prévu dans la branche de réception, lequel est disposé de telle façon en série avec la face primaire du coupleur optoélectronique (U90) de la branche de réception que le transistor (Q96) est sélectivement commuté conducteur et permet ainsi une circulation de courant sortant de la source de courant (R90, R91, Q90, Q95) vers le côté primaire du coupleur optoélectronique (U90) de la branche de réception, tant que la tension à l'entrée de la branche de réception dépasse une valeur de seuil définie, caractérisée en ce que
    - un condensateur (C95) est branché entre un point de connexion d'un émetteur du transistor (Q96) et une cathode du coupleur optoélectronique (U90).
  2. Interface selon la revendication 1,
    dans laquelle le transistor (Q96) commute sélectivement le côté primaire du coupleur optoélectronique (U90) conductrice, lorsque la tension au niveau d'un élément non linéaire, en particulier d'une diode Zener (Z95), dépasse une valeur définie.
  3. Interface selon l'une quelconque des revendications précédentes,
    dans laquelle un accumulateur d'énergie (C94) électrique est prévu dans la branche de réception, lequel est chargé par le branchement en série de la source de courant (R90, R91, Q90, Q95) et du transistor (Q96), et lequel se décharge à travers une résistance (R100) en série avec le côté secondaire du coupleur optoélectronique (U91) de la branche d'émission.
  4. Interface selon la revendication 3,
    dans laquelle l'accumulateur d'énergie (C94) prévu dans la branche de réception se décharge à travers la résistance (R100) en série avec le côté secondaire du coupleur optoélectronique (U91) de la branche d'émission en cas de suppression de la tension du bus par court-circuitage sélectif d'un bus pouvant être raccordé durant la plage temporelle d'un bit d'émission.
  5. Interface selon la revendication 3 ou 4,
    dans laquelle la résistance (R100) est branchée entre l'accumulateur d'énergie (C94) et le coupleur optoélectronique (U91).
  6. Interface selon l'une quelconque des revendications 3 à 5,
    dans laquelle l'accumulateur d'énergie (C94) et la résistance (R100) sont dimensionnés de telle façon que durant la durée temporelle d'émission d'un bit numérique, durant laquelle le bus pouvant être connecté est court-circuité, un courant de décharge circule.
  7. Interface selon la revendication 6,
    dans laquelle la durée temporelle de flancs du bit numérique, lequel court-circuite le bus pouvant être connecté, est inférieure à 25 ms, de préférence inférieure à 15 µs.
  8. Interface selon l'une quelconque des revendications 3 à 7,
    dans laquelle l'accumulateur d'énergie (C94) est chargé à partir de la source de courant sans élément de régulation du courant de charge ou à travers un transistor de régulation du courant de charge.
  9. Ballast pour un moyen d'éclairage, en particulier une lampe à décharge de gaz, des DEL ou des DELO, comprenant une interface selon l'une quelconque des revendications précédentes.
  10. Lampe, présentant un moyen d'éclairage, en particulier une lampe à décharge de gaz, des DEL ou des DELO, ainsi qu'un ballast selon la revendication 9.
  11. Réseau de bus de technique de bâtiment, présentant un bus et au moins un utilisateur de bus comprenant une interface selon l'une quelconque des revendications 1 à 7.
EP14783603.5A 2013-10-28 2014-10-09 Interface à branche d'émission améliorée Active EP3064041B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102013221848.6A DE102013221848A1 (de) 2013-10-28 2013-10-28 Schnittstelle mit verbessertem Sendezweig
PCT/EP2014/071674 WO2015062837A1 (fr) 2013-10-28 2014-10-09 Interface à branche d'émission améliorée

Publications (2)

Publication Number Publication Date
EP3064041A1 EP3064041A1 (fr) 2016-09-07
EP3064041B1 true EP3064041B1 (fr) 2022-11-30

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EP14783603.5A Active EP3064041B1 (fr) 2013-10-28 2014-10-09 Interface à branche d'émission améliorée

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US (1) US9585233B2 (fr)
EP (1) EP3064041B1 (fr)
CN (1) CN105532075B (fr)
DE (1) DE102013221848A1 (fr)
WO (1) WO2015062837A1 (fr)

Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
CN107820355A (zh) * 2017-12-01 2018-03-20 赛尔富电子有限公司 一种带有自举功能的dali接口电路
WO2019144373A1 (fr) 2018-01-26 2019-08-01 Tridonic Gmbh & Co Kg Circuit de dali, procédé de commande et équipement
CN112789952B (zh) * 2018-10-02 2024-06-07 昕诺飞控股有限公司 用于通过通信总线来传输消息的数字可寻址照明接口dali使能的通信设备以及相对应的方法

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DE10113367C1 (de) * 2001-03-20 2003-01-02 Vossloh Schwabe Elektronik Interfaceschaltung

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US5146357A (en) * 1990-05-04 1992-09-08 Buffton Corporation Data communications system that prevents undesired coupling between data stations
US7764479B2 (en) * 2007-04-18 2010-07-27 Lutron Electronics Co., Inc. Communication circuit for a digital electronic dimming ballast
DE102009016904B4 (de) 2009-04-08 2012-03-01 Osram Ag Schnittstelle zum Ansteuern eines elektronischen Vorschaltgeräts
WO2011135098A1 (fr) * 2010-04-30 2011-11-03 Tridonic Gmbh & Co Kg Circuit d'interface à résistance diélectrique
US9131549B2 (en) * 2012-04-12 2015-09-08 Koninklijke Philips N.V. Digital communication interface circuit for line-pair with individually adjustable transition edges
JP6382825B2 (ja) * 2012-10-17 2018-08-29 フィリップス ライティング ホールディング ビー ヴィ デューティサイクル不均衡補償を備えた線対用のデジタル通信受信器インターフェース回路
EP2770637B1 (fr) * 2013-02-22 2015-08-19 Siemens Aktiengesellschaft Agencement d'optocoupleur et groupe d'entrée et/ou sortie

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DE10113367C1 (de) * 2001-03-20 2003-01-02 Vossloh Schwabe Elektronik Interfaceschaltung

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WO2015062837A1 (fr) 2015-05-07
CN105532075A (zh) 2016-04-27
CN105532075B (zh) 2018-09-25
EP3064041A1 (fr) 2016-09-07
US9585233B2 (en) 2017-02-28
US20160234918A1 (en) 2016-08-11
DE102013221848A1 (de) 2015-04-30

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