EP3064041B1 - Interface having an improved transmitting branch - Google Patents

Description

The present invention relates to an interface for bidirectional communication with an electronic operating device for at least one light source and a ballast with such an interface.

From the DE 10 2009 016 904 B4 an interface for DALI control signals is known, which has a transmission and a reception channel, both of which can be operated with a common power source. The prior art circuit is in 1 shown.

In addition, the pamphlets show WO 2011/135098 A1 , WO 2013/153510 A1 and DE 101 13 367 C1 further examples for BUS interfaces.

Appropriate optocouplers U2, U1 are provided in the known circuit both for receiving DALI signals and for sending DALI signals, each forming part of a branch for sending or receiving. Both branches are fed from the common current source Q2, Q3, R3, R4. The circuit also has an energy store that 1 is shown as capacitor C2.

The well-known interface is designed for communication according to the DALI standard, in which a predetermined DC voltage is applied to the lines when the bus is inactive. This predetermined DC voltage is reduced only in the case of a signal transmission, while the constant DC voltage is applied when no signals are transmitted.

According to the prior art, the capacitor C2 is charged by the DC voltage present on the bus. This makes sense here because when a signal is transmitted according to the DALI standard, the voltage present on the bus drops to (logical) zero or to the voltage that is defined for the low-level voltage. This can in Return channel (transmission branch) of the circuit can be recognized immediately.

"Back channel" refers to the channel away from the interface, other than the channel for the interface's transmit operation. The "send branch" is the signal path of the interface used for sending signals.

If, however, instead of DALI signals, signals are to be received by the interface according to a protocol in which the voltage is zero (or very low compared to the DALI standard) when the bus is idle, it turns out that the known interface is not suitable for this is. An example of such a standard is the so-called DSI standard.

The reason for this is that, in contrast to the DALI standard, according to the DSI standard there is no voltage or low voltage when the bus is inactive (the "low level", i.e. the low value for the transmission of a first logical state, e.g. 0 , is specified to < 6.5 volts). The voltage on the bus is only increased when a DSI signal is transmitted.

Consequently, if a DSI signal arrives at the connection for the control gear, i.e. on the secondary side, of the known interface, the voltage rises suddenly from the value for the first logic state, e.g. <6.5 volts, to a predetermined DC voltage, e.g 10 - 15 volts (high level, i.e. the voltage value that is interpreted as the second logical value, eg 1). It is now necessary that the incoming signal is detected immediately to ensure reliable detection of the DSI signal. With DSI, transmission is Manchester-coded, ie a data bit is transmitted by changing from low level to high level (logical 0) or by changing from high level to low level (logical 1).

The capacitor C2 from the known circuit has a disruptive effect here, however, since the falling edge (logical 1) or the first bit of the DSI signal cannot be reliably recognized by the known interface.

This is because, after going high (for about 833 µs), capacitor C2 is partially charged as a result of the 2 mA input current source. If the bus voltage drops below 6.5 volts, capacitor C2 continues to be charged. As a result, current also flows in the optocoupler U2 of the receiving branch, so that the first logical state (e.g. 1) at the optocoupler output of optocoupler U2 cannot be recognized immediately after the voltage falls below 6.5 volts. The capacitor C2 is still partially charged even after falling below the low level and bridges the zener diode Z1 in the non- or partially charged state, which otherwise immediately interrupts the current flow in the optocoupler U2 if the zener voltage (low level) is fallen below.

It is therefore the object of the invention to provide an interface which is improved in transmission mode with regard to the edge steepness of digital signals.

The invention solves this problem by providing an interface as claimed in claim 1. Advantageous developments of the invention are the subject matter of the dependent claims.

• einen Sende- und einen Empfangszweig, wobei der Empfangszweig eine Stromquelle aufweist, die von einem im Ruhezustand Spannung führenden Bus aus speisbar ist, wobei die Stromquelle wenigstens den Sendezweig mit Energie versorgt und der Sendezweig einen Optokoppler aufweist, wobei in dem Empfangszweig ein elektrischer Energiespeicher, bspw. ein oder mehrere Kondensatoren, vorgesehen ist, der durch die Stromquelle aufgeladen wird, und der sich über wenigstens einen Widerstand in Serie zu der Sekundärseite des Optokopplers des Sendezweigs entlädt.

A digital bus interface for an operating device for a lamp has:

• a transmission branch and a reception branch, the reception branch having a current source which can be fed from a bus which is live in the idle state, the current source supplying at least the transmission branch with energy and the transmission branch having an optocoupler, the reception branch having an electrical Energy storage, eg. One or more capacitors, is provided, which is charged by the power source and which discharges via at least one resistor in series with the secondary side of the optocoupler of the transmission branch.

The resistor can be connected between the energy store and the optocoupler.

The energy store and the resistor can be dimensioned in such a way that a discharge current flows during the transmission period of a digital bit, during which a connectable bus is short-circuited.

The edge duration of a digital bit that short-circuits a connectable bus can be less than 25 mS, preferably less than 15 μS.

The energy store can be charged from the current source without a charging current control element or via a charging current control transistor.

Essential aspects of the invention will now be described with a view to the drawings.

Fig. 1

eine Schnittstelle nach dem Stand der Technik.

Fig. 2

eine schematische Darstellung einer Schaltungsanordnung.

Fig. 3

eine weitere schematische Darstellung einer Schaltungsanordnung.

Fig. 4

eine weiter schematische Darstellung einer Schaltungsanordnung.

Fig. 5

eine erfindungsgemässe Ausführungsform.

show:

1

a state-of-the-art interface.

2

a schematic representation of a circuit arrangement.

3

a further schematic representation of a circuit arrangement.

4

a further schematic representation of a circuit arrangement.

figure 5

an embodiment of the invention.

2 shows a circuit arrangement. Here, in particular, a field effect transistor (FET, JFET) J1 and a resistor R7 form a current source J1, R7, which provides a charging current of a predetermined level to an energy store, which is referred to as capacitor C1 in the following by way of example.

On the one hand, this ensures that a constant current (input current minus charging current) ultimately flows through the optocoupler Q5. On the other hand, the effect of a non-linear component, in particular a zener diode D9, is not bridged by the capacitor C1. In the following, therefore, the term "Zener diode" is used to represent the non-linear component. Preferably, the current split is such that the charging current for the capacitor is less than the current through the optocoupler, preferably in a range from 30% to 70% of the optocoupler current.

The charging current for capacitor C1 is now picked up at the input of optocoupler Q3 of the receiving branch (see measuring point I between diode D6 and optocoupler Q3). So the capacitor is part of a path that is connected in parallel with a path that includes the primary side of the receive optocoupler Q3.

Using the current source J1, R7 described ensures that a falling edge of a DSI signal, ie in particular the first bit of the DSI command (start bit, logical 1, coded with a falling edge), is recognized quickly and reliably. Because the capacitor C1 is not first discharged after the high level has been applied, it can be detected directly when the voltage drops to the low level. Nevertheless, also in a common power source can be used in the circuit according to the invention for the reverse channel and forward channel (receive/transmit branch).

In addition to being used for signal reception according to the DSI standard, the interface can also be used for signal reception according to the DALI standard. It is essential that the arrangement according to the invention enables incoming signals to be detected very quickly, even if the idle state of the bus voltage is close to 0 volts or 0 volts.

In the 2 The circuit arrangement shown is designed in such a way that it counteracts the negative influence of a current source by using a large-sized capacitor (with a capacity of e.g. 1-6 µF), which is reduced from the current source with the FET J1 and the resistor R7 to approx .5 volts or more is charged. In this case, there is only a parasitic influence of the drain-source capacitance of the FET J1, which, however, can be reduced by suitably dimensioning the capacitance at the gate.

2 shows a schematic representation of the interface with a first primary-side control connection and a second primary-side control connection. A DALI control device SDALI on the one hand and a mains button (not shown) on the other hand are coupled to the primary-side control input.

In the present case, a resistor R1 is arranged in series with the first primary-side control connection. A rectifier, which includes four diodes D1 to D4, is coupled between the resistor R1 and the second primary-side control connection.

A switch X1 is coupled between a first and a second rectifier output connection, in particular its working electrode-reference electrode path. A current source, which includes two bipolar transistors Q1, Q2 and two ohmic resistors R2, R3, is also coupled to the rectifier output connection. A first optocoupler Q3 is coupled to the output of the current source and is coupled in series with a zener diode D9. A series circuit comprising a diode D6, the current source J1, R7 consisting of FET J1 and resistor R7, and a capacitor C1 is coupled in parallel with the zener diode D9. A second optocoupler Q5 is supplied via the current source R7, J1.

The optocoupler Q3 in the reception branch can transfer signals via an output of the interface with a first and a second output connection, while the second optocoupler Q5 in the transmission branch is provided via a signal input with a first and a second signal connection for sending signals.

The output of optocoupler Q5 is connected to the control electrode of switch X1, with a diode D13 and resistor R9 connected in series along this path. A parallel connection of a capacitor C3 and a resistor R11 is coupled in parallel with the control electrode of the switch X1 and act as a noise filter. Another bipolar transistor Q4 is coupled between the capacitor C3 and the resistor R11, the base of which is coupled to the higher-potential side of the resistor R11.

By using the current source J1, R7 to charge the capacitor C1 (this is essentially the same as Capacitor C2 of the known circuit) is then given full functionality even when transmitting signals according to the DSI standard, since charging of the capacitor C1 no longer takes place with a falling edge, but also according to the DALI standard. The capacitor C1 is consequently always charged, which means that the zener diode D9 does not have to be bypassed by a non-charged or partially charged state with a falling edge.

After switching on the mains voltage and thus applying a direct voltage at a predetermined level according to the DALI standard (DALI _On ), the capacitor C1 is charged to approx. 5.5 volts or more in around 400 milliseconds, so that after 600 milliseconds (this corresponds to the DALI standard) a response to a DALI signal can be sent from the time it is switched on.

The charging current is limited to 100 µA, for example, by the current source consisting of FET J1 and resistor R7. However, this value can also be higher or lower depending on the components used.

As a result, the optocoupler Q5 is always driven with a defined current, with the current through FET J1 being selected in such a way that in the event of a DSI signal being transmitted, it has an influence on the bit time, i.e. the time in which a bit is sent from the transmitter to the Receiver can be sent is small.

The circuits shown can be modified as follows. For example, if the control voltage for FET X1, i.e. the voltage at C1, is to be increased, an optocoupler Q5 with a control current of approx. 1 milliamps instead of eg 5 milliamps (mA) can be used. This can be, for example, an optocoupler of the type TLP621 or TLP624 from Toshiba.

By reducing the optocoupler current to 1 milliamp, more current (e.g. 600 microamps) can be allowed to charge capacitor C1, allowing the voltage across C1 to reach its setpoint more quickly, and thus an even higher value at the time of transmit after 600 milliseconds Has. Furthermore, the diodes D6 and D13 can be replaced by Schottky diodes, whereby the control voltage at the gate of the switch X1 can be increased by about 0.5 volts if necessary. This then makes it possible to use a smaller-sized FET X1.

Referring to figures 4 and 5 a circuit will now be explained in two variants.

The invention relates in particular to the improvement in terms of the signal shape and the signal repetition for digital bits to be transmitted in the transmission branch.

through the in 4 and figure 5 Circuits shown can be reduced edge sides (thus steeper edges) achieve. For example, edges with a duration of less than 25 ms, preferably even less than 15 ms, can be achieved. In the event that a bus that carries potential in the idle state is used (e.g. the DALI bus), these periods of time refer to the period of time until the edge of a transmission bit has pulled the bus potential to the lower potential, or the trailing edge of a transmission bit in turn allows the bus potential to rise from the low potential to the quiescent potential.

In figures 4 and 5 the two terminals for connecting two bus lines are shown on the left side, e.g. for a DALI bus.

An optocoupler labeled 'DALIin' is shown on the right-hand side. On its primary side U90 (left side of the optocoupler in figures) incoming signals are fed from the bus by means of a current source (the Darlington circuit Q90, Q95), which are then then transmitted by the optocoupler in an electrically isolated manner. On the secondary side of the DALIin optocoupler, further evaluation then follows by a control circuit in the operating device for lamps and the activation of the lamps according to the information received via the bus.

The digital signals to be transmitted by the control circuit of the operating device for lamps are applied to the primary side of the further (transmission-side) optocoupler DALIout, U91, and transmitted to the secondary side in an electrically isolated manner. The secondary side then has a circuit that can selectively short-circuit the bus.

Basically, the portion of the circuit between the secondary side of the optocoupler U91 and the bus is powered by the bus voltage and the regulated current source Q90, Q95.

However, a problem arises in that when a digital signal is sent, the leading edge of the digital bit selectively short-circuits the bus voltage and thus pulls it to a low potential. This in turn means that the energy supply for feeding the current source Q90, Q95, which was still present beforehand, is no longer necessary. The energy can only be supplied from, for example, capacitances in the interface circuit itself, which represents an uncontrolled energy supply, which leads to problems with the precise setting of the edge profile, but also to feedback effects, which in turn can lead to oscillations (ringing). In order to keep these feedback effects low in terms of their disruptive effect, filtering components must therefore be included in the interface circuit, which in turn slow down the response behavior over time. After all, this ultimately leads to a restriction with regard to the adjustable edge profiles and bit repetition rates.

According to the invention as in figures 4 and 5 shown, it is therefore provided that the current source Q90, Q95 fed from the bus voltage charges an electrical energy store, in the example shown the capacitor C94. Preferably, this charging occurs without a current regulator between the current source Q90, Q95 and the capacitor C94. However, the transistor linear regulator shown above in the exemplary embodiments can also be present here.

It is also important that the discharge of the capacitor C94 is controlled via an ohmic Resistor R100 takes place, which is connected, for example, between the energy store and the optocoupler.

This controlled discharging by means of a constant discharging current will therefore take place when the current source Q90, Q95 can not only work properly, ie selective short-circuiting in the time range of the transmission bit when the bus voltage fails. Capacitor C94 is discharged with a controlled current through resistor R100.

The energy storage capacitor C94 and the ohmic resistor R100, which defines the discharge current, are tuned in such a way that the energy storage capacitor C94 is not yet fully discharged during the transmission period, i.e. during the short-circuiting of the bus voltage, and is therefore safe for the entire duration of the transmission bit (short-circuiting of the bus ) a constant discharge current flows through resistor R100 and the secondary side of optocoupler U91.

With reference to figure 5 an embodiment of the present invention will now be explained.

According to the embodiment of figure 5 a switch Q96 is now provided in the receive branch which includes the receive optocoupler U90. This switch Q96 can be, for example, a transistor, such as a bipolar transistor, in particular, as shown in the present example, a PNP bipolar transistor.

The transistor Q96 is connected at its base to a zener diode Z95.

When the voltage across the zener diode Z95 has reached the zener voltage (e.g. in 5.7V), the switch (transistor) Q96 is turned on (switched on) and thus allows current to flow on the primary side of the receiving-side optocoupler U90. As already described in connection with the previous exemplary embodiments, this current flow is fed by the current source R90, R91, Q90, Q95.

As in figure 5 As can be seen, an energy storage element, in particular a capacitor C95, is also connected in the path upstream of the Zener diode Z95. More specifically, this capacitor C95 is connected between the junction of the base of transistor Q95 below the cathode of diode Z95 and the junction of the emitter of transistor Q96 and the cathode of receive optocoupler U90. This capacitor C95 now causes a short delay in turning on transistor Q96 when there is sufficient voltage on the bus side.

By means of this switch (transistor) Q95, a particularly advantageous interface circuit can now be made possible in which on the input side (left side "bus" in figure 5 ) both digital signals according to the DALI or the DSI standard as well as button signals can be applied in which a supply voltage is manually short-circuited.

The circuit block FB in figure 5 contains a two-stage circuit for adapting the edge steepness when transmitting, i.e. when driving transistor Q92, by means of which the bus lines can be selectively short-circuited.

Claims (11)

1. Digital bus interface for an operating device for an illuminant, wherein:

   - the interface has a transmitting branch and a receiving branch,

   - the receiving branch has a current source (R90, R91, Q90, Q95) which can be fed from a bus carrying voltage in the idle state,

   - the power source (R90, R91, Q90, Q95) supplies at least the transmitting branch with power, and the transmitting branch has an optocoupler (U91),

   - the receiving branch has a further optocoupler (U90),

   - in the receiving branch, a transistor (Q96) is provided which is arranged in series with the primary side of the optocoupler (U90) of the receiving branch in such a way that the transistor (Q96) is selectively conductively switched and thus, starting from the current source (R90, R91, Q90, Q95), enables a current flow on the primary side of the optocoupler (U90) of the receiving branch, as long as the voltage at the input of the receiving branch exceeds a defined threshold value, characterized in that

   - a capacitor (C95) is connected between a connection point of an emitter of the transistor (Q96) and a cathode of the optocoupler (U90).
2. Interface according to claim 1,
   wherein the transistor (Q96) selectively conductively connects the primary side of the optocoupler (U90) of the receiving branch when the voltage on a nonlinear element, in particular a Zener diode (Z95), exceeds a defined value.
3. Interface according to any one of the preceding claims,
   in which an electrical energy store (C94) is provided in the receiving branch, which electrical energy store (C94) is charged by the series circuit of current source (R90, R91, Q90, Q95) and transistor (Q96), and which discharges via a resistor (R100) in series with the secondary side of the optocoupler (U91) of the transmitting branch.
4. Interface according to claim 3,
   wherein the electrical energy store (C94) provided in the receiving branch discharges via the resistor (R100), in series with the secondary side of the optocoupler (U91) of the transmitting branch, if the bus voltage ceases via selective short-circuiting of a connectible bus in the time period of a transmission bit.
5. Interface according to claim 3 or 4,
   wherein the resistor (R100) is connected between the energy store (C94) and the optocoupler (U91).
6. Interface according to any one of claims 3 to 5,
   wherein the energy store (C94) and the resistor (R100) are dimensioned such that a discharge current flows during the transmission duration of a digital bit during which the connectible bus is short-circuited.
7. Interface according to claim 6,
   wherein the edge duration of the digital bit that short-circuits the connectible bus is less than 25 ms, preferably less than 15 µs.
8. Interface according to any one of claims 3 to 7,
   in which the energy store (C94) is charged without a charge-current regulating element or via a charge-current regulating transistor, starting from the current source.
9. A ballast for illuminants, in particular gas discharge lamp, LEDs, or OLEDs, having an interface according to any one of the preceding claims.
10. Luminaire having an illuminant, in particular gas discharge lamp, LEDs, or OLEDs, and a ballast according to claim 9.
11. Building engineering bus system having a bus and at least one bus subscriber with an interface according to any one of claims 1 to 7.

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