Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/36—Circuit design at the analogue level
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/20—Design optimisation, verification or simulation
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/36—Circuit design at the analogue level
  • G06F30/373—Design optimisation

Definitions

• the present invention relates to the field of systems on chips or SoC for System on Chip in English, and more specifically the structured design of the analog IP blocks integrated in a SoC, where the IP (IP) blocks ("IP" for Intellectual Property in English) are pre-characterized blocks arranged especially to perform one or more given functions.
• IP IP
• SoC Systems on chip, hereafter “SoC” by concision or indifferently “circuit”
• CMOS technology Complementary Metal Oxide Semiconductor
• Digital IP blocks are well managed today and are not developed further here.
• analog I P blocks which generally perform amplification, filtering or digital ⁇ -> conversion functions, are generally very difficult to take into account when designing a SoC.
• block means an analog IP block.
• Category A offers the advantage of using complex standard models implemented in a simulator.
• the disadvantage is to have to run the simulator many times, which implies a consequent synthesis time (several hours for a circuit of a hundred transistor).
• the present invention aims to combine the advantages of the two categories above.
• the invention relates to a method for determining the values of electrical parameters of the transistors of an analog circuit of a system-on-a-chip, comprising the steps of:
• - (1 10) establish the circuit diagram of the circuit comprising said blocks;
• - (120) define a set of electrical constraints specific to said circuit, said blocks and the transistors of each block according in particular to the circuit diagram of the circuit;
• said general structured graph comprises the set of calculation operators and constraints defined by the designer.
• step (171) of graphical representation of the alarm signal in which, in the structured graph of the circuit, at least one of the block, the operator and the electrical parameter of said operator at the origin of the conflict are represented in a predetermined color.
• the step (160) of identifying a conflict comprises a step (161) consisting of, for a given electrical parameter, counting the number of electrical parameters whose value is propagated towards said given electrical parameter, and wherein the alarm signal is transmitted (170) if said input or output parameter of an operator is defined by more than one other electrical parameter.
• the method includes a step (162) of removing in the defined electrical constraints the value of the block parameter at the origin of the conflict.
• the method includes a step (163) of replacing the selected operator whose output parameter is in contention by a replacement operator such that the output parameter of the operator causing the conflict is an input parameter of the override operator.
• An evaluation step (180) of calculating the rest point of the analog circuit can be provided.
• the invention relates to a computer program comprising program code instructions for implementing the method according to the invention when it is executed on a computer.
• the point of rest of a transistor is defined by the set of electrical quantities characterizing said transistor in the absence of signals to be amplified.
• the point of rest is the state of the operating point of the transistor in the absence of any useful signal.
• the polarization of the transistor makes it possible to place the point of rest of this one at a desired value, on the load line of this one.
• the point of polarization of a circuit is located at the intersection of the load lines during the static regime and during the dynamic regime, which make it possible to study the behavior of the circuit.
• the present invention makes it possible to automatically calculate the polarization point of an analog circuit and to calculate the dimensions of the transistors constituting the analog IP blocks of a given SoC. In addition, these calculations are performed in accordance with the assumptions and knowledge of the SoC designer.
• the present invention makes it possible to generate and test several calculation procedures for the same analog IP block that a designer can very easily debug, which also makes it possible to possibly explore several design scenarios of the same IP block.
• the present invention also makes it possible to manage the design conflicts of a given IP block, such as the design conflicts of the assembly of IP blocks with each other, which is particularly advantageous in the case of collaborative work for example.
• the present invention provides a hierarchical and standard representation for the design and verification of a SoC comprising analog IP blocks. This representation can be easily shared and reused within a group of analog IP block developers to correct, evaluate, and protect knowledge related to a given IP block.
• the invention is independent of SoC manufacturing technology. It can therefore be used to design and redesign an analog IP block for different technologies very easily.
• the present invention makes it possible to increase the design speed of analog IP blocks.
• the present invention also makes it possible to simulate the static and transient (dynamic) behavior of the IP blocks. This structured simulation makes it possible to verify the electrical behavior of an IP block designed according to the invention.
• FIG. 1 illustrates an embodiment of an electrical diagram of an analog circuit
• FIG. 2 illustrates an embodiment of a set of possible operators according to the invention for the 3 reference transistors M9AP, M1 AP and M2P of the block GMD of the circuit of FIG. 1,
• FIG. 3 illustrates an embodiment according to the invention of a structured graph for the block GMD of the circuit of FIG. 1,
• FIG. 4 illustrates an embodiment according to the invention of a truncated structured graph for the circuit of FIG. 1 presenting a conflict
• FIG. 5 is a truncated illustration of the graph of FIG. 4 generated according to a different design choice, leading to other conflicts,
• FIG. 6 is a truncated illustration of a graph according to the invention solving the conflicts of the graph of FIG. 4;
• FIG. 7 illustrates an embodiment of the method according to the invention.
• Figure 8 illustrates the results of the 3 rd filter simulation and 5 th order designed from the circuit of Figure 1 with the invention.
• the present invention is placed in the context where a designer wishes to design a SoC. From constraints particular to the circuit topology and designer design assumptions, it can automatically calculate a No. 2 umber reduced or minimum, of the electrical parameters of transistors necessary and their dimensions the computation of the circuit bias point . Electrical diagram
• step 1 of establishing the circuit diagram of the circuit for example by means of computer diagram design software on a computer.
• the establishment of the electrical circuit diagram is preceded by a step of defining the topology of the circuit, that is to say, to decompose 100 the overall circuit in hierarchical levels into a set of sub-circuits or blocks connected between them and to define the arrangement of the transistors in each sub-circuit, each block having a defined functionality.
• a plurality of transistors can be assembled into an elementary device, for example a current mirror, composed of a small number of interconnected transistors among which a reference transistor and secondary transistors are defined.
• the reference transistor controls the sizing and polarization of the other transistors within the elementary device.
• the electrical parameters of a reference transistor in fact uniquely define those of the secondary transistors by propagation of the parameters of said reference transistor towards the secondary transistors.
• the propagation property is advantageously used in the structured graphs described later where only the reference transistors are represented, which makes it possible to increase the speed of calculation.
• Each transistor or elementary device can be selected by the designer in a component library. It is possible to propagate to the set of secondary transistors the values of the electrical parameters calculated for the corresponding reference transistor.
• FIG. 1 there is illustrated a global circuit exerting a function of controlling the linear transconductance of the block GMD with the voltage Vc, by controlling the drains of the transitos M1 AP and M1 AN differentially, where the transconductance is the ratio between the variation of the output current and the variation of the input voltage of a component or a circuit.
• this circuit serves as a unique circuit example for the present invention.
• This circuit comprises 4 CMC, AMP, GMD and AMP blocks or sub-circuits represented in dotted lines. Each of these blocks performs a given function.
• the GMD block is the core of the differential transconductance
• the AMP blocks allow tuning frequencies
• CMC is a counter-reaction sub-circuit to stabilize the operating point.
• the two AMP blocks are identical and therefore bear the same reference (see the matching constraints below); they are electrically connected only to the GMD block.
• the CMC block is electrically connected only to the GMD block.
• the electrical diagram of the circuit makes it possible to define at least part of the constraints of this circuit.
• the electrical circuit diagram is completed, it is expected 120 to define a set of electrical constraints at each hierarchical level of the circuit: for the global circuit, the blocks, and the components (transistors or elementary devices) blocks.
• the constraints may depend on the intended use of the circuit. They comprise for example at least one of the following elements: the supply voltage, the electrical connections (for example the equipotentials), the pairing of certain components, and the assumptions of the designer.
• the assumptions or constraints of the designer are constraints that can not be extract from the circuit diagram of a circuit. This is for example the scheduling of transistors, linear constraints (see below), or the choice of operators (described later). At least some of the assumptions of the designer can be modified, while other constraints (typically the supply voltage) can not be modified by the designer.
• Linear constraints are inherent to the topology of the circuit, for example because of the laws of Kirchhoff (law of the nodes and law of the meshes), or inherent to the circuit, for example by equipotentials (with or without electrical connection) or by the values of reference bias current received by each transistor (each transistor receives either the value of the reference bias current, or a multiple of this value). They can therefore be defined according to the electrical diagram of the circuit or according to a choice of design.
• the matching constraints make it possible to consider that the reference transistor of a block is identical to the equivalent transistor in a paired block, ie of the same width.
• a reference transistor is defined in each paired block.
• the calculation of the dimensions of the reference transistor is applied to the paired transistor.
• the two AMP blocks are matched, the dimensions of their reference transistors are the same. Therefore, only the dimensions of the transistors of one of the blocks are calculated and only one of the AMP blocks can be used in the structured graph described later.
• the scheduling constraints are based on the circuit diagram; they make it possible to define the order in which the transistors of a block are dimensioned.
• the sizing and polarization constraints correspond to the selection by the designer of a given operator for each transistor, the operator making it possible to calculate the electrical parameters of the corresponding transistor.
• electrical parameter of a transistor is meant in particular the dimensions thereof (width and length) as well as at least some of the electrical voltages thereof (gate voltage, drain and source).
• each operator corresponds to a given transistor and makes it possible to calculate electrical parameters of said transistor as a function of the type of operator selected and of certain electrical input parameters.
• Operators are known, for example from the publication R. Iskander, M. Lou ⁇ rat, A. Kaiser “Hierarchical Sizing and Biaising of Analog Firm Intellectual Properties", Integration, VLSI Journal, March 2013 - pp. 172-188; Vol 46, issue 2 in press, DOI 10.1016 / j.vsli.2012.01 .001; or the publication F. Javid, R.
• the source voltage is connected to the supply voltage, which is known.
• the gate voltage can be determined by an operator, for example the operator OPVG which makes it possible to determine this gate voltage in addition to the width of the transistor.
• the knowledge of the gate voltage makes it possible to calculate the source voltage.
• the designer may choose to determine the source voltage by an operator, in this case OPVS, and then calculate the gate voltage according to the source voltage.
• Each operator calculates electrical output parameters based on input electrical parameters and the type of operator.
• a set of possible operators for each reference transistor of block GMD in this case M9AP, M1 AP and M2P, of FIG. They come in the form of software.
• the structured block graphs are then assembled into a general graph of the circuit, using the equipotentials of said circuit.
• FIG. 3 represents an embodiment of a hierarchical structured graph for the block GMD of the circuit of FIG.
• the GMD block is symmetrical, so that the transistors M9AP, M2P and M1 AP are defined as reference transistors for respectively calculating the parameters of the secondary transistors M9AN, M2N and M1 AN.
• the block is represented in a predetermined form, in this case a rectangle comprising in the header the identification of said block, in this case GMD.
• Each transistor is represented in a predetermined form, in this case a rectangle, comprising in the header the identification of said transistor, for example M1 AP.
• the pairing between transistors is also represented by a predetermined shape, in this case a rectangle, comprising in the header the identification of said transistors interconnected by a predetermined symbol, in this case the symbol "_".
• M9AP_M9AN the pairing between the M9AP transistor and the M9AN transistor, and similarly for M1 AP_M1 AN or M2P_M2N.
• the electrical input and output parameters of an operator for a given transistor are represented by a predetermined form, in this case the circles or ellipses, each circle or ellipse comprising a single parameter whose label illustrates said parameter, for example Vd for the drain voltage, L for the width, Vg for the gate voltage, W for the width, Id for the terminal current of drain, Vs for the source voltage, L for the length.
• the parameters representing the constraints of said block are arranged, by convention, at the top of the structured graph and arranged in a predetermined form, in this case a rectangle, and identified as block constraints, in this case by the heading " GMD Input Parameters ".
• Some electrical parameters are interconnected by arrows. For a given operator, the direction of the arrows between the parameters and said operator indicates whether the parameters are input parameters or output parameters.
• Two electrical parameters can be connected to each other via a mathematical function representing the associated constraints.
• the mathematical function is illustrated in a predetermined form, in this case a square, comprising a symbol of said mathematical function.
• Rectangles marked for example "eq1", “eq2", etc. or more generally “eqN” represent the constraints established by the designer.
• the equation “eq1” located in the rectangle “GMD Input Parameters” of Figure 3 4 or in the rectangle “AMP1 Input Parameters (Pin)" of Figure 4 is defined by:
• L_M1 AP is the length of the transistor M1 AP of Figure 1
• L and K1 are two parameters defined by the designer.
• the value of the bias current Ibias is equal to the value of the current Id of the transistor M9AP.
• This value of the current Id is an input parameter of the operator OPVG (VEG) of said transistor M9AP.
• this value of the current Id of the transistor M9AP is multiplied by the mathematical function (-1) as an input parameter value Id of the operator OPW (VG, VS) of the transistor M1 AP.
• the arrows correspond to the constraints and illustrate the propagation of the value of a parameter. They are generated automatically. They can connect the parameters of a transistor:
• the values of the input electrical parameters are known because imposed or function of a previous calculation result. For example :
• the value Vg of the transistor M1 AP is imposed; in this case it is equal to the value Vg defined by the constraints of the GMD block in the rectangle "GMD Input Parameters" which represents the constraints imposed by the designer for the GMD block;
• the value Id of the transistor M1 AP is calculated from the value Id of the transistor M9AP of which it is multiplied by (-1).
• the values of the output electrical parameters are calculated by an operator.
• the output parameters of the OPW operator (VG, VS) for the transistor M1 AP are Vb (for mass voltage or bulk by anglicism), Vth (for threshold voltage) and W (for width).
• the values of these output parameters are calculated by said operator as a function of the values of the input parameters.
• Each operator is represented in a predetermined form, in this case a rectangle, comprising in the header the identification of said operator, for example OPW (VG, VS) for the transistor M1 AP (FIG. 3). All operators are configured to calculate as output parameter at least the width W of the corresponding transistor. Preferably, all the operators are further configured to calculate as output parameter at least the threshold voltage Vth of the corresponding transistor.
• the calculation of the bulk voltage Vb, the gate voltage Vg or the source voltage Vs typically depends on the selected operator.
• the graphical arrangement of the transistors with respect to each other satisfies the scheduling constraints.
• the structured graph is read from top to bottom.
• the transistor M9AP is created before the transistor M1 AP, itself created before the M2P transistor.
• the design order of the transistors can be defined according to the electrical diagram of the circuit.
• the transistors are made by branches, where a branch is the set of transistors interconnected by their source or their drain.
• the transistors are made in a predetermined sequence.
• an embodiment sequence for the first left branch of the left AMP block is the following: the transistor M5BP then the transistor M7BP, then the transistor M4BP.
• This linear order is not mandatory, it is possible to provide more complex embodiments where the sequence is different: the M5BP transistor then the M4BP transistor, then the M7BP transistor.
• the advantage of an embodiment sequence, and therefore of a design sequence is that certain parameters of the transistors can propagate along the sequence in a given branch.
• the voltage VC makes it possible to calculate the voltage VB7, which makes it possible to calculate the voltage VB5.
• the branch of the transistors M9AP, M2P and M1 AP of the block GMD of FIG. 1 corresponds to the sequence of transistors M9AP, M1 AP and M2P of FIG.
• Constraints defined by the designer for each block can lead to design conflicts when assembling blocks together.
• the graph comprises all the hierarchical levels: the circuit, the blocks of the circuit and the transistors of each block.
• FIG. 4 illustrates, in a truncated manner for greater readability, a structured hierarchical graph of the circuit of FIG.
• the graph is structured in that each block and each transistor is clearly identified. It is hierarchical in that there exists a reading convention making it possible to order the calculations of the parameters of the block-by-block transistors. The position of the blocks is determined by the designer, it defines the order of design of the sub-circuits in the reading direction of the graph. Finally the graph is bipartite in that it contains two types of nodes: the parameters (represented by circles) and the equations (represented by rectangles). The graph makes it easy to illustrate possible conflicts in a first evaluation phase and their solution in a second phase.
• a first step is to obtain the corresponding graph of each block of the circuit and then a second step is to obtain the graph corresponding to the circuit.
• the circuit comprises three blocks (since the two AMP blocks are paired). These three blocks are illustrated in Figure 4.
• the CMC and GMD blocks are respectively identified by Transconductor.CMC and Transconductor.GMD. Since the two AMP blocks are paired, the two AMP blocks are identified by Transconductor.AMPI and Transconductor.AMP2.
• This evaluation makes it possible to generate the calculation of the dimensions of the components, the hitherto unknown voltages of the connectors, as well as all the parameters of all the transistors of the circuit, thanks to the selected operators and the defined constraints.
• the identification of a conflict may comprise a step 161 consisting of, for a given electrical parameter, counting the number of electrical parameters whose value propagates towards said given electrical parameter.
• FIG. 4 illustrates a truncated structured graph corresponding to the circuit of FIG. 1 and for which block constraints have been defined by the designer in the "Input Parameters (Pin)" rectangles for each block CMC, GMD and AMP; and operators selected for each reference transistor of each block.
• the output parameters of each operator are calculated.
• the value of an output parameter of an operator can be reused (propagated) as an input parameter for another operator in the reading direction of the structured graph.
• the first constraints defined are those of the global circuit "Transconductor Input Parameters (Pin)", then those of the CMC block (“CMC Input Parameters (Pin)”) some of which are used as input parameters of the operator OPVG (VEG) of the transistor M13.
• the value Vd propagates from the constraints of the CMC block to the transistor M13 as an input parameter of the operator OPVG (VEG). Then this value Vd propagates with an equality constraint as an output parameter Vg of the operator OPVG (VEG) of the transistor M9AP of the block GMD, etc. Since this value Vg is also defined as an output parameter calculated by the OPVG operator (VEG) of the M9AP transistor, there is therefore a conflict since this value Vg is non-unique.
• an alarm will be generated which signifies this conflict.
• the message content identifies at least the operator and the electrical parameter at the origin of the conflict.
• it is possible to provide a graphic representation of the alarm for example by a color code.
• at least one of the block, the operator and the electrical parameter of the said operator at the origin of the conflict are colored, for example in red. The designer can thus easily and very quickly identify design conflicts.
• FIG. 5 Another example of a conflict is illustrated in FIG. 5, which truncates another embodiment of a structured graph of the circuit of FIG. In this case, the design order of the sub-circuits is different compared to Figure 4, which can generate different conflicts.
• the value Vg of the input parameter of the OPVS operator (VEG, VB) of the transistor M1 1 AP of the block CMC is defined both by the value Vg of the constraints of the block "CMC Input Parameters (Pin ) Of said block and by the value Vd of the output parameter of the transistor M9AN of the block GMD. So there is a conflict.
• the value Vd of the input parameter of the operator OPVG (VEG) of the transistor M13 of the block CMC is defined both by the value Vd of the constraints of the block "CMC Input Parameters (Pin)" of said block and by the value Vg of the output parameter of the transistor M9AP of the block GMD. So there is a conflict.
• the identification of a conflict consists in detecting whether an input or output parameter of an operator is defined by more than one parameter, therefore an alarm will be generated in this case.
• a conflict may exist between a block parameter and an output parameter that both propagate their value to the same input parameter.
• the block constraints are defined by the designer and the constraints between blocks or between transistors of the same block are physical constraints.
• it is expected to remove the parameter of the block constraint at the origin of the conflict.
• a conflict may exist between a parameter whose value would be calculated by two operators or by an operator and by the propagation of a value of another electrical parameter according to certain constraints.
• the replacement operator is an operator of the same class as that of the first operator, the class of an operator defining the voltages (gate, drain or source) calculated by the latter.
• the operators OPIDS (VEG), OPIDS (VG, VS), OPIDS (VGS, VG) and OPIDS (VGS, VS) are of the same class.
• the class of OPVG operators and those of OPW operators are defined.
• the output parameter of the operator causing the conflict is an input parameter of the replacement operator.
• Vg of the output parameter of the operator OPVG (VEG) of the transistor M9AP of the block GMD is in conflict because also defined by the value Vd of the transistor M1 3 of the block CMC.
• the conflict is resolved, as illustrated in FIG. 6, by replacing the operator OPVG (VEG) of the transistor M9AP of the block GMD whose output parameter is at the origin of the conflict by a replacement operator, in the the operator OPW (VG, VS) in which the value Vg is then an input parameter, always defined by the value Vd of the transistor M13 of the CMC block.
• OPVG operator OPVG
• VS operator OPW
• a structured graph can detect and resolve conflicts. It can also be reused later for the synthesis and re-design of the circuit.
• FIG. 8 represents the evolution of the gain of the 3 th and 5 th order circuit (filter) designed from the circuit of FIG. 1 as a function of the frequency, for four control voltage values Vc.
• the invention is a tool for assisting the design of analog circuits which makes it possible to calculate the dimensions of the transistors, and which makes it possible to guide the designer in the design of an analog circuit.
• the invention is independent of the number of blocks, the number of electrical parameters. The number of operators is linear with the number of transistors, which allows very fast calculations.
• a step 180 consisting in calculating the rest point of the analog circuit is provided.
• Tests have been carried out by the applicant on the time required for sizing the circuit illustrated in FIG. According to the techniques of the prior art, this time is several hours; according to the invention, the time required for reading and evaluating the structured graph representing the circuit of FIG. 1, the identification and the resolution of the conflicts is 64 seconds, after optimization of the parameters.

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