US20170235856A1 - Formal verification driven power modeling and design verification - Google Patents
Formal verification driven power modeling and design verification Download PDFInfo
- Publication number
- US20170235856A1 US20170235856A1 US15/041,068 US201615041068A US2017235856A1 US 20170235856 A1 US20170235856 A1 US 20170235856A1 US 201615041068 A US201615041068 A US 201615041068A US 2017235856 A1 US2017235856 A1 US 2017235856A1
- Authority
- US
- United States
- Prior art keywords
- computer
- numerical sequence
- unit
- input pins
- blocks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- G06F17/5009—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
-
- G06F2217/78—
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Definitions
- the present invention relates generally to intellectual property (“IP”) power modeling and in particular to determining the simulation condition of IP designs for power model generation.
- IP intellectual property
- IP power models are created for power estimation at higher levels of design.
- An IP power model is an abstraction of the power behavior of a component that provides specification of the supported component power state and power consumption data.
- the IP power model may provide power consumption data for each enumerated power state (e.g., functional mode, test mode, etc.) in the power model which may significantly impact the overall power consumption of the component. Determining the simulation condition for the different input pins of the IP blocks is critical to generate an accurate power model. Poorly constructed power models may cause erroneous power analysis and subsequent chip or system power projections. Similarly, there may be instances in a design where the IP block input pin conditions have been violated. However, due to the rapid growth and complexity of systems, such as microprocessors, generation of IP power models and verification of IP designs have become increasingly difficult, are time consuming, and are prone to error.
- a computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks.
- the computer-implemented method further includes selecting one or more input pins for each of said one or more blocks.
- the computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence.
- the computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails.
- the computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails.
- the computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition.
- FIG. 1 is a block diagram of one embodiment of a computer system environment 100 suitable for operation in accordance with at least one embodiment of the invention.
- FIG. 2 is a flow chart diagram depicting the power model program in accordance with at least one embodiment of the invention.
- FIG. 3 is an exemplary diagram for a portion of a worked example of the power model program in accordance with at least one embodiment of the invention.
- FIG. 4 is a block diagram of a computing apparatus 400 suitable for executing the power model program in accordance with at least one embodiment of the invention.
- Irrespective of the power model type e.g., .lib, contributor-based, etc.
- the approach used for generating the power model e.g., circuit simulation, logic simulation, etc.
- determining the simulation condition for the different input pins of the IP blocks that form an integrated circuit (“IC”) is critical for generating an accurate power model of the system.
- IC integrated circuit
- an IC may generally consist of thousands of IP blocks, created by hundreds of register transfer level (“RTL”) designers, who are employed by multiple IP block vendors.
- RTL register transfer level
- the input pin conditions of the IP blocks are also dependent on the mode (e.g. functional mode, test mode, etc.) for which the power model is to be generated.
- Embodiments of the present invention recognize that it may be desirable to automatically determine the simulation condition for the different input pins of the IP blocks for power model generation. Embodiments of the present invention may further recognize that it may be desirable to simultaneously determine any design errors during power model generation.
- a design error may be understood as an error in the correct input pin conditions in the design of RTL content.
- FIG. 1 is a block diagram depicting one embodiment of a computer system environment suitable for operation in accordance with at least one embodiment of the invention.
- a power modeling program 101 may receive a unit 102 .
- a unit 102 may be understood as RTL content for a component of an IC.
- each unit may include one or more IP blocks 103 .
- an IP block 103 may be understood as a reusable unit of logic that is the intellectual property of an entity.
- the power modeling program 101 may further select one or more input pins 104 for each of the one or more IP blocks 103 .
- An input pin 104 may be understood as a pin that remains at either a logic state of 0 or a logic state of 1.
- the power modeling program 101 may further assign a numerical value 105 to each of the one or more input pins 104 to yield at least one numerical sequence 106 .
- the power modeling program 101 may further, for each numerical sequence 106 of the at least one numerical sequence 106 , perform a check 107 on the numerical sequence 106 to yield a number of fails 108 .
- a check 107 may be understood as formal verification of each of the one or more IP blocks 103 based on the numerical sequence 106 of the one or more input pins 104 .
- formal verification is the act of proving or disproving the correctness of intended behavior of a system with respect to a certain formal specification or property of one or more underlying algorithms, using formal methods of mathematics.
- formal verification may be used to verify that a design intent (i.e., specification) is preserved in its implementation (i.e., RTL content).
- a fail 108 may be understood as an error in the numerical sequence 106 for the one or more input pins 104 .
- the power modeling program 101 may further determine a simulation condition 109 for power modeling of the unit 102 based on optimizing a numerical sequence 106 with respect to the number of fails 108 .
- the power modeling program 101 may further determine a number of design errors 110 of the unit 102 based on the simulation condition 109 .
- a number of design errors 110 of the unit 102 may be determined according to the number of fails 108 present.
- the power modeling program 101 may exist in a cloud-based, virtual, or distributed environment or a remote environment on defined server hardware. Furthermore, the power modeling program 101 may implement parallel processing for one or more checks 107 for the one or more IP blocks 103 .
- the power modeling program 101 may implement the use of input/output (I/O) parallelism, which enables concurrent I/O streams to be initiated for one or more checks 107 for the one or more IP blocks 103 .
- the power modeling program 101 may implement the use of query computer processor (CP) parallelism, which enables multitasking of I/O streams and computer processing units (CPU) for one or more checks 107 for the one or more IP blocks 103 .
- CP parallelism one or more checks 107 for the one or more IP blocks 103 may be executed concurrently with one another on multiple processors.
- FIG. 2 is a flow chart diagram depicting the power modeling program in accordance with at least one embodiment of the invention.
- the power modeling program 101 may receive a unit 102 .
- the power modeling program 101 may receive a unit 102 for an analog IC (e.g., op-amps, linear regulators, phase locked loops, oscillators, and active filters).
- the power modeling program 101 may receive a unit 102 for a digital IC (e.g., microprocessor, field-programmable gate array (FPGA), memory (e.g., RAM, ROM, flash, etc.), and application specific integrated circuit (ASIC)).
- FPGA field-programmable gate array
- ASIC application specific integrated circuit
- the power modelling program may receive a unit 102 of a microprocessor.
- Units 102 of a microprocessor may include, but are not limited to the execution unit, load-store unit, instruction fetch unit, and condition register unit.
- the unit 102 may be in the form of RTL content, which is a method of abstraction for defining the analog or digital portions of a circuit design based on synchronous logic.
- RTL content may consist of registers, combinatorial logic, and clocks, which may be written in hardware description languages (HDLs) such as Verilog and Very High Speed Integrated Circuit Hardware Description Language (VHDL).
- HDLs hardware description languages
- VHDL Very High Speed Integrated Circuit Hardware Description Language
- the unit 102 may further include one or more IP blocks 103 .
- an IP block 103 may be in the form of standard cells, digital blocks, and analog blocks.
- the power modeling program 101 may select one or more input pins 104 for each of the one or more IP blocks 103 .
- the one or more input pins 104 selected by the power modeling program 101 are the input pins 104 whose condition for power modeling need to be determined.
- the power modeling program 101 may select one or more input pins 104 based on manual user input of the input pins 104 of interest in accordance with a power model guide.
- the power modeling program 101 may automatically determine the input pins 104 of interest by performing formal verification for all of the input pins 104 of each of the one or more IP blocks 103 to find those input pins 104 which do not toggle (i.e., switch).
- the power modeling program 101 may assign a numerical value 105 to each of the one or more input pins 104 to yield at least one numerical sequence 106 . More specifically, the power modeling program 101 may assign a numerical value 105 of either zero or one. Here, a numerical sequence 106 may be understood as the assignment of numerical values 105 to subsequently selected input pins 104 . For example, in step 201 , the power modeling program 101 may select input pins X, Y, and Z. In step 202 , the power modeling program 101 may assign the numerical value 1 to input pin X, the numerical value 0 to input pin Y, and the numerical value 1 to input pin Z.
- the power modeling program 101 may continue to repeat step 202 until every possible numerical sequence 106 for the one or more input pins 104 has been established.
- the power modeling program 101 may, for each numerical sequence 106 of the at least one numerical sequence 106 , perform a check 107 on the numerical sequence 106 to yield a number of fails 108 .
- the power modeling program 101 may perform a check 107 on each numerical sequence 106 established in step 202 .
- the power modeling program 101 may use formal verification to prove or disprove the correctness of the numerical sequence 106 of the one or more input pins 104 for each of the one or more IP blocks 103 .
- the power modeling program 101 may engage in the formal verification of a different numerical sequence 106 of the one or more input pins 104 to determine the correct input pin 104 settings for power model generation of the unit 102 .
- the power modeling program 101 may use model checking formal verification. Model checking may be employed using any domain-specific abstraction techniques, such as state space enumeration, symbolic state space enumeration, abstract interpretation, and symbolic simulation. In another embodiment of the invention, the power modeling program 101 may use equivalence checking formal verification. Equivalence checking may be employed using any generally known methods, including, but not limited to binary decision diagrams (BDDs) and conjunctive normal form satisfiability.
- BDDs binary decision diagrams
- the power modeling program may yield a number of fails 108 based on the numerical sequence 106 assigned to the one or more input pins 104 .
- the power modeling program 101 may yield a number of fails 108 for each check 107 performed in step 203 .
- the power modeling program 101 may further yield a fail 108 for each of the one or more IP blocks 103 for each check 107 performed in step 203 .
- a fail 108 is the result of formal verification disproving the correctness of the numerical sequence 106 of the one or more input pins 104 for the proper input pin 104 settings for power model generation of the unit 102 .
- a fail 108 is an error in the numerical sequence 106 of the one or more input pins 104 for an IP block 103 of the unit 102 .
- the power modeling program 101 may determine a simulation condition 109 for power model generation of the unit 102 based on optimizing a numerical sequence 106 with respect to the number of fails 108 .
- Optimizing may be understand as the numerical sequence 106 that yields the least number of fails 108 .
- a number of fails 108 may include a count of errors in the numerical sequence 106 of the one or more input pins 104 .
- the numerical sequence 106 that yields the least amount of fails 108 corresponds to the proper input pin 104 settings that should be used for power model generation of the unit 102 .
- the power modeling program 101 may determine a number of design errors 110 of the unit 102 based on the simulation condition 109 . More specifically, the number of design errors 110 of the unit 102 may be the number of design errors 110 of the RTL content.
- each fail 108 may correspond to a design error 110 in the RTL content for one or more IP blocks 103 . It should be appreciated that determining a number of design errors 110 at this level of design may enable an RTL designer to modify the RTL content prior to implementing the RTL content in a physical design (i.e., circuit design, physical design, etc.).
- FIG. 3 is an exemplary diagram for a portion of a worked example of the power modeling program in accordance with at least one embodiment of the invention.
- the power modeling program 101 has received a unit 102 of RTL content written in HDL code.
- the unit 102 of RTL content received by the power modeling program 101 may be for the load-store unit of a microprocessor.
- the load-store unit includes multiple IP blocks 103 , of which there are 189 instances of an LCB 1 cell.
- instances of other types of cells e.g., LCB 2 , LCB 3 , etc.
- the power modeling program 101 may select one or more input pins 104 for each LCB 1 cell incorporated in one or more IP blocks 103 .
- the power modeling program 101 has selected input pins A, B, and C for each of the 189 instances of the LCB 1 cell that are incorporated within the RTL content of the one or more IP blocks 103 of the load-store unit.
- the power modeling program 101 may further assign a numerical value 105 to input pins A, B, and C for each instance of a LCB 1 cell to yield at least one numerical sequence 106 .
- the power modeling program 101 may continue to assign a numerical value 105 to input pins A, B, and C until the possible numerical sequences 106 of input pins A, B, and C has been exhausted. As demonstrated in FIG. 3 , the power modeling program 101 has assigned the following numerical sequences 106 to input pins A, B, and C: 000, 001, 010, 011, 100, 101, 110, and 111.
- the power modelling program may further perform a check 107 for each numerical sequence 106 of input pins A, B, and C.
- the power modeling program 101 has performed eight individual checks 107 (i.e., one check 107 for each numerical sequence 106 ).
- the power modeling program 101 has yielded a number of fails 108 based on the numerical sequence 106 of input pins A, B, and C.
- the power modeling program 101 has yielded 189 fails for each of checks 1, 2, 3, 4, 5, 6, and 8 and 13 fails for check 7. More specifically, each fail 108 is representative of an error in the pin settings for input pins A, B, and C of an LCB 1 cell.
- the power modelling program may further determine a simulation condition 109 for power model generation of the load-store unit based on optimizing (i.e. the numerical sequence 106 that yields the least amount of fails 108 ) a numerical sequence 106 with respect to the number of fails 108 .
- the numerical sequence 106 that yielded the least amount of fails (13) was the numerical sequence ( 110 ) for input pins A, B, and C.
- the power modeling program 101 has determined that the numerical sequence ( 110 ) for input pins A, B, and C is the simulation condition 109 that should be used for power model generation of the LCB 1 cell.
- the power modeling program 101 may further automatically set input pins A, B, and C to the correct numerical sequence ( 110 ) for each instance of the 189 instances of the LCB 1 cell incorporated in the one or more IP blocks 103 of the load-store unit for power model generation of the LCB 1 cell.
- the power modeling program 101 may further determine a number of design errors 110 of the load-store unit RTL content based on the simulation condition 109 .
- the correct simulation condition 109 for power model generation should yield 0 fails 108 .
- the power modeling program 101 has identified 13 fails (i.e., 13 design errors) in the RTL content for the 189 instances of the LCB 1 cell incorporated in the one or more IP blocks 103 of the load-store unit.
- FIG. 4 is a block diagram depicting components of a computer 400 suitable for executing the power modeling program 101 .
- Figure displays the computer 400 , the one or more processor(s) 404 (including one or more computer processors), the communications fabric 402 , the memory 406 , the RAM 416 , the cache 418 , the persistent storage 408 , the communications unit 412 , the I/O interfaces 414 , the display 422 , and the external devices 420 .
- FIG. 4 provides only an illustration of one embodiment and does not imply any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made.
- the computer 400 operates over a communications fabric 402 , which provides communications between the computer processor(s) 404 , memory 406 , persistent storage 408 , communications unit 412 , and input/output (I/O) interface(s) 414 .
- the communications fabric 402 may be implemented with any architecture suitable for passing data or control information between the processors 404 (e.g., microprocessors, communications processors, and network processors), the memory 406 , the external devices 420 , and any other hardware components within a system.
- the communications fabric 402 may be implemented with one or more buses.
- the memory 406 and persistent storage 408 are computer readable storage media.
- the memory 406 comprises a random access memory (RAM) 416 and a cache 418 .
- the memory 406 may comprise any suitable volatile or non-volatile one or more computer readable storage media.
- Program instructions for the power modeling program 101 may be stored in the persistent storage 408 , or more generally, any computer readable storage media, for execution by one or more of the respective computer processors 404 via one or more memories of the memory 406 .
- the persistent storage 408 may be a magnetic hard disk drive, a solid state disk drive, a semiconductor storage device, read-only memory (ROM), electronically erasable programmable read-only memory (EEPROM), flash memory, or any other computer readable storage media that is capable of storing program instructions or digital information.
- the media used by the persistent storage 406 may also be removable.
- a removable hard drive may be used for persistent storage 408 .
- Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive for transfer onto another computer readable storage medium that is also part of the persistent storage 408 .
- the communications unit 412 in these examples, provides for communications with other data processing systems or devices.
- the communications unit 412 may comprise one or more network interface cards.
- the communications unit 412 may provide communications through the use of either or both physical and wireless communications links.
- the source of the various input data may be physically remote to the computer 400 such that the input data may be received and the output similarly transmitted via the communications unit 412 .
- the I/O interface(s) 414 allow for input and output of data with other devices that may operate in conjunction with the computer 400 .
- the I/O interface 414 may provide a connection to the external devices 420 , which may be as a keyboard, keypad, a touch screen, or other suitable input devices.
- External devices 420 may also include portable computer readable storage media, for example thumb drives, portable optical or magnetic disks, and memory cards.
- Software and data used to practice embodiments of the present invention may be stored on such portable computer readable storage media and may be loaded onto the persistent storage 408 via the I/O interface(s) 414 .
- the I/O interface(s) 414 may similarly connect to a display 422 .
- the display 422 provides a mechanism to display data to a user and may be, for example, a computer monitor.
- the present invention may be a system, a method, and/or a computer program product.
- the computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
- the computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device.
- the computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing.
- a non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing.
- RAM random access memory
- ROM read-only memory
- EPROM or Flash memory erasable programmable read-only memory
- SRAM static random access memory
- CD-ROM compact disc read-only memory
- DVD digital versatile disk
- memory stick a floppy disk
- a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon
- a computer readable storage medium is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
- Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network.
- the network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers.
- a network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
- Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages.
- the computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server.
- the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
- electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
- These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
- These computer readable program instructions may also be stored in a readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
- the computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
- each block in the flowchart or block diagrams may represent a module, segment, or portion of computer program instructions, which comprises one or more executable instructions for implementing the specified logical function(s).
- the functions noted in the block may occur out of the order noted in the figures.
- two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
Abstract
A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.
Description
- The present invention relates generally to intellectual property (“IP”) power modeling and in particular to determining the simulation condition of IP designs for power model generation.
- The visibility of component power behavior is provided through the use of IP power models, which are created for power estimation at higher levels of design. An IP power model is an abstraction of the power behavior of a component that provides specification of the supported component power state and power consumption data. The IP power model may provide power consumption data for each enumerated power state (e.g., functional mode, test mode, etc.) in the power model which may significantly impact the overall power consumption of the component. Determining the simulation condition for the different input pins of the IP blocks is critical to generate an accurate power model. Poorly constructed power models may cause erroneous power analysis and subsequent chip or system power projections. Similarly, there may be instances in a design where the IP block input pin conditions have been violated. However, due to the rapid growth and complexity of systems, such as microprocessors, generation of IP power models and verification of IP designs have become increasingly difficult, are time consuming, and are prone to error.
- A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.
-
FIG. 1 is a block diagram of one embodiment of acomputer system environment 100 suitable for operation in accordance with at least one embodiment of the invention. -
FIG. 2 is a flow chart diagram depicting the power model program in accordance with at least one embodiment of the invention. -
FIG. 3 is an exemplary diagram for a portion of a worked example of the power model program in accordance with at least one embodiment of the invention. -
FIG. 4 is a block diagram of acomputing apparatus 400 suitable for executing the power model program in accordance with at least one embodiment of the invention. - Irrespective of the power model type (e.g., .lib, contributor-based, etc.) or the approach used for generating the power model (e.g., circuit simulation, logic simulation, etc.) determining the simulation condition for the different input pins of the IP blocks that form an integrated circuit (“IC”) (e.g., microprocessor) is critical for generating an accurate power model of the system. However, an IC may generally consist of thousands of IP blocks, created by hundreds of register transfer level (“RTL”) designers, who are employed by multiple IP block vendors. To complicate matters further, the input pin conditions of the IP blocks are also dependent on the mode (e.g. functional mode, test mode, etc.) for which the power model is to be generated.
- Currently, the input pin conditions of the IP blocks are manually set according to IP design guides, which may take several days to weeks to complete. Consultations with IP design experts and RTL designers may further be necessary to correctly set the input pin conditions of the IP blocks for power model generation. Nonetheless, this current process remains highly prone to error and a single incorrect setting of an input pin for an IP block may result in notable error (upwards of 50%) in chip power estimates. Even when the input pins are set correctly for power model generation, there still may exist design errors which further contribute to an improper power analysis.
- Embodiments of the present invention recognize that it may be desirable to automatically determine the simulation condition for the different input pins of the IP blocks for power model generation. Embodiments of the present invention may further recognize that it may be desirable to simultaneously determine any design errors during power model generation. A design error may be understood as an error in the correct input pin conditions in the design of RTL content.
- Referring now to various embodiments of the invention in more detail,
FIG. 1 is a block diagram depicting one embodiment of a computer system environment suitable for operation in accordance with at least one embodiment of the invention. Within acomputer system 100, apower modeling program 101 may receive aunit 102. Aunit 102 may be understood as RTL content for a component of an IC. More specifically, each unit may include one ormore IP blocks 103. In digital circuit design, anIP block 103 may be understood as a reusable unit of logic that is the intellectual property of an entity. - The
power modeling program 101 may further select one ormore input pins 104 for each of the one ormore IP blocks 103. Aninput pin 104 may be understood as a pin that remains at either a logic state of 0 or a logic state of 1. Thepower modeling program 101 may further assign anumerical value 105 to each of the one ormore input pins 104 to yield at least onenumerical sequence 106. - The
power modeling program 101 may further, for eachnumerical sequence 106 of the at least onenumerical sequence 106, perform acheck 107 on thenumerical sequence 106 to yield a number offails 108. Acheck 107 may be understood as formal verification of each of the one ormore IP blocks 103 based on thenumerical sequence 106 of the one ormore input pins 104. Generally, formal verification is the act of proving or disproving the correctness of intended behavior of a system with respect to a certain formal specification or property of one or more underlying algorithms, using formal methods of mathematics. For example, formal verification may be used to verify that a design intent (i.e., specification) is preserved in its implementation (i.e., RTL content). Afail 108 may be understood as an error in thenumerical sequence 106 for the one ormore input pins 104. - The
power modeling program 101 may further determine asimulation condition 109 for power modeling of theunit 102 based on optimizing anumerical sequence 106 with respect to the number offails 108. Thepower modeling program 101 may further determine a number ofdesign errors 110 of theunit 102 based on thesimulation condition 109. Here, even under thecorrect simulation condition 109 for power modeling of theunit 102, a number ofdesign errors 110 of theunit 102 may be determined according to the number offails 108 present. - The
power modeling program 101 may exist in a cloud-based, virtual, or distributed environment or a remote environment on defined server hardware. Furthermore, thepower modeling program 101 may implement parallel processing for one ormore checks 107 for the one ormore IP blocks 103. For example, thepower modeling program 101 may implement the use of input/output (I/O) parallelism, which enables concurrent I/O streams to be initiated for one ormore checks 107 for the one ormore IP blocks 103. In another example, thepower modeling program 101 may implement the use of query computer processor (CP) parallelism, which enables multitasking of I/O streams and computer processing units (CPU) for one ormore checks 107 for the one ormore IP blocks 103. With CP parallelism, one ormore checks 107 for the one ormore IP blocks 103 may be executed concurrently with one another on multiple processors. -
FIG. 2 is a flow chart diagram depicting the power modeling program in accordance with at least one embodiment of the invention. According to the depicted embodiment, atstep 200, thepower modeling program 101 may receive aunit 102. In one embodiment of the invention, thepower modeling program 101 may receive aunit 102 for an analog IC (e.g., op-amps, linear regulators, phase locked loops, oscillators, and active filters). In another embodiment of the invention, thepower modeling program 101 may receive aunit 102 for a digital IC (e.g., microprocessor, field-programmable gate array (FPGA), memory (e.g., RAM, ROM, flash, etc.), and application specific integrated circuit (ASIC)). For example, the power modelling program may receive aunit 102 of a microprocessor.Units 102 of a microprocessor may include, but are not limited to the execution unit, load-store unit, instruction fetch unit, and condition register unit. In any embodiment, theunit 102 may be in the form of RTL content, which is a method of abstraction for defining the analog or digital portions of a circuit design based on synchronous logic. Generally, RTL content may consist of registers, combinatorial logic, and clocks, which may be written in hardware description languages (HDLs) such as Verilog and Very High Speed Integrated Circuit Hardware Description Language (VHDL). - The
unit 102 may further include one ormore IP blocks 103. Generally, anIP block 103 may be in the form of standard cells, digital blocks, and analog blocks. - At
step 201, thepower modeling program 101 may select one ormore input pins 104 for each of the one ormore IP blocks 103. Here, the one or more input pins 104 selected by thepower modeling program 101 are the input pins 104 whose condition for power modeling need to be determined. In one embodiment of the invention, thepower modeling program 101 may select one or more input pins 104 based on manual user input of the input pins 104 of interest in accordance with a power model guide. In another embodiment of the invention, thepower modeling program 101 may automatically determine the input pins 104 of interest by performing formal verification for all of the input pins 104 of each of the one or more IP blocks 103 to find those input pins 104 which do not toggle (i.e., switch). - At
step 202, thepower modeling program 101 may assign anumerical value 105 to each of the one or more input pins 104 to yield at least onenumerical sequence 106. More specifically, thepower modeling program 101 may assign anumerical value 105 of either zero or one. Here, anumerical sequence 106 may be understood as the assignment ofnumerical values 105 to subsequently selected input pins 104. For example, instep 201, thepower modeling program 101 may select input pins X, Y, and Z. Instep 202, thepower modeling program 101 may assign thenumerical value 1 to input pin X, thenumerical value 0 to input pin Y, and thenumerical value 1 to input pin Z. Thus, the assignment of anumerical value 105 to input pins X, Y, and Z would yield the numerical sequence (101). Thepower modeling program 101 may continue to repeatstep 202 until every possiblenumerical sequence 106 for the one or more input pins 104 has been established. - At
step 203, thepower modeling program 101 may, for eachnumerical sequence 106 of the at least onenumerical sequence 106, perform acheck 107 on thenumerical sequence 106 to yield a number of fails 108. Thepower modeling program 101 may perform acheck 107 on eachnumerical sequence 106 established instep 202. Here, thepower modeling program 101 may use formal verification to prove or disprove the correctness of thenumerical sequence 106 of the one or more input pins 104 for each of the one or more IP blocks 103. In other words, each time thepower modeling program 101 performs acheck 107, thepower modeling program 101 may engage in the formal verification of a differentnumerical sequence 106 of the one or more input pins 104 to determine thecorrect input pin 104 settings for power model generation of theunit 102. - In one embodiment of the invention, the
power modeling program 101 may use model checking formal verification. Model checking may be employed using any domain-specific abstraction techniques, such as state space enumeration, symbolic state space enumeration, abstract interpretation, and symbolic simulation. In another embodiment of the invention, thepower modeling program 101 may use equivalence checking formal verification. Equivalence checking may be employed using any generally known methods, including, but not limited to binary decision diagrams (BDDs) and conjunctive normal form satisfiability. - The power modeling program may yield a number of fails 108 based on the
numerical sequence 106 assigned to the one or more input pins 104. Thepower modeling program 101 may yield a number of fails 108 for each check 107 performed instep 203. Thepower modeling program 101 may further yield afail 108 for each of the one or more IP blocks 103 for each check 107 performed instep 203. Here, afail 108 is the result of formal verification disproving the correctness of thenumerical sequence 106 of the one or more input pins 104 for theproper input pin 104 settings for power model generation of theunit 102. In other words, afail 108 is an error in thenumerical sequence 106 of the one or more input pins 104 for anIP block 103 of theunit 102. - At
step 204, thepower modeling program 101 may determine asimulation condition 109 for power model generation of theunit 102 based on optimizing anumerical sequence 106 with respect to the number of fails 108. Optimizing may be understand as thenumerical sequence 106 that yields the least number of fails 108. A number of fails 108 may include a count of errors in thenumerical sequence 106 of the one or more input pins 104. Here, thenumerical sequence 106 that yields the least amount of fails 108 corresponds to theproper input pin 104 settings that should be used for power model generation of theunit 102. - At
step 205, thepower modeling program 101 may determine a number ofdesign errors 110 of theunit 102 based on thesimulation condition 109. More specifically, the number ofdesign errors 110 of theunit 102 may be the number ofdesign errors 110 of the RTL content. Here, each fail 108 may correspond to adesign error 110 in the RTL content for one or more IP blocks 103. It should be appreciated that determining a number ofdesign errors 110 at this level of design may enable an RTL designer to modify the RTL content prior to implementing the RTL content in a physical design (i.e., circuit design, physical design, etc.). -
FIG. 3 is an exemplary diagram for a portion of a worked example of the power modeling program in accordance with at least one embodiment of the invention. InFIG. 3 , thepower modeling program 101 has received aunit 102 of RTL content written in HDL code. More specifically, theunit 102 of RTL content received by thepower modeling program 101 may be for the load-store unit of a microprocessor. In this case, the load-store unit includes multiple IP blocks 103, of which there are 189 instances of an LCB1 cell. However, instances of other types of cells (e.g., LCB2, LCB3, etc.) may be present in theunit 102 of RTL code. - Upon receiving the RTL content for the load-store unit of a microprocessor, the
power modeling program 101 may select one or more input pins 104 for each LCB1 cell incorporated in one or more IP blocks 103. Here, thepower modeling program 101 has selected input pins A, B, and C for each of the 189 instances of the LCB1 cell that are incorporated within the RTL content of the one or more IP blocks 103 of the load-store unit. Thepower modeling program 101 may further assign anumerical value 105 to input pins A, B, and C for each instance of a LCB1 cell to yield at least onenumerical sequence 106. Thepower modeling program 101 may continue to assign anumerical value 105 to input pins A, B, and C until the possiblenumerical sequences 106 of input pins A, B, and C has been exhausted. As demonstrated inFIG. 3 , thepower modeling program 101 has assigned the followingnumerical sequences 106 to input pins A, B, and C: 000, 001, 010, 011, 100, 101, 110, and 111. - The power modelling program may further perform a
check 107 for eachnumerical sequence 106 of input pins A, B, and C. Here, thepower modeling program 101 has performed eight individual checks 107 (i.e., onecheck 107 for each numerical sequence 106). For each enumerated check 107 (check 1 through check 8), thepower modeling program 101 has yielded a number of fails 108 based on thenumerical sequence 106 of input pins A, B, and C. Here, thepower modeling program 101 has yielded 189 fails for each ofchecks check 7. More specifically, each fail 108 is representative of an error in the pin settings for input pins A, B, and C of an LCB1 cell. - The power modelling program may further determine a
simulation condition 109 for power model generation of the load-store unit based on optimizing (i.e. thenumerical sequence 106 that yields the least amount of fails 108) anumerical sequence 106 with respect to the number of fails 108. Here, thenumerical sequence 106 that yielded the least amount of fails (13) was the numerical sequence (110) for input pins A, B, and C. Thus, it can be said that thepower modeling program 101 has determined that the numerical sequence (110) for input pins A, B, and C is thesimulation condition 109 that should be used for power model generation of the LCB1 cell. Thepower modeling program 101 may further automatically set input pins A, B, and C to the correct numerical sequence (110) for each instance of the 189 instances of the LCB1 cell incorporated in the one or more IP blocks 103 of the load-store unit for power model generation of the LCB1 cell. - The
power modeling program 101 may further determine a number ofdesign errors 110 of the load-store unit RTL content based on thesimulation condition 109. In an error free design, thecorrect simulation condition 109 for power model generation should yield 0 fails 108. Here, thepower modeling program 101 has identified 13 fails (i.e., 13 design errors) in the RTL content for the 189 instances of the LCB1 cell incorporated in the one or more IP blocks 103 of the load-store unit. -
FIG. 4 is a block diagram depicting components of acomputer 400 suitable for executing thepower modeling program 101. Figure displays thecomputer 400, the one or more processor(s) 404 (including one or more computer processors), thecommunications fabric 402, thememory 406, theRAM 416, thecache 418, thepersistent storage 408, thecommunications unit 412, the I/O interfaces 414, the display 422, and theexternal devices 420. It should be appreciated thatFIG. 4 provides only an illustration of one embodiment and does not imply any limitations with regard to the environments in which different embodiments may be implemented. Many modifications to the depicted environment may be made. - As depicted, the
computer 400 operates over acommunications fabric 402, which provides communications between the computer processor(s) 404,memory 406,persistent storage 408,communications unit 412, and input/output (I/O) interface(s) 414. Thecommunications fabric 402 may be implemented with any architecture suitable for passing data or control information between the processors 404 (e.g., microprocessors, communications processors, and network processors), thememory 406, theexternal devices 420, and any other hardware components within a system. For example, thecommunications fabric 402 may be implemented with one or more buses. - The
memory 406 andpersistent storage 408 are computer readable storage media. In the depicted embodiment, thememory 406 comprises a random access memory (RAM) 416 and acache 418. In general, thememory 406 may comprise any suitable volatile or non-volatile one or more computer readable storage media. - Program instructions for the
power modeling program 101 may be stored in thepersistent storage 408, or more generally, any computer readable storage media, for execution by one or more of therespective computer processors 404 via one or more memories of thememory 406. Thepersistent storage 408 may be a magnetic hard disk drive, a solid state disk drive, a semiconductor storage device, read-only memory (ROM), electronically erasable programmable read-only memory (EEPROM), flash memory, or any other computer readable storage media that is capable of storing program instructions or digital information. - The media used by the
persistent storage 406 may also be removable. For example, a removable hard drive may be used forpersistent storage 408. Other examples include optical and magnetic disks, thumb drives, and smart cards that are inserted into a drive for transfer onto another computer readable storage medium that is also part of thepersistent storage 408. - The
communications unit 412, in these examples, provides for communications with other data processing systems or devices. In these examples, thecommunications unit 412 may comprise one or more network interface cards. Thecommunications unit 412 may provide communications through the use of either or both physical and wireless communications links. In the context of some embodiments of the present invention, the source of the various input data may be physically remote to thecomputer 400 such that the input data may be received and the output similarly transmitted via thecommunications unit 412. - The I/O interface(s) 414 allow for input and output of data with other devices that may operate in conjunction with the
computer 400. For example, the I/O interface 414 may provide a connection to theexternal devices 420, which may be as a keyboard, keypad, a touch screen, or other suitable input devices.External devices 420 may also include portable computer readable storage media, for example thumb drives, portable optical or magnetic disks, and memory cards. Software and data used to practice embodiments of the present invention may be stored on such portable computer readable storage media and may be loaded onto thepersistent storage 408 via the I/O interface(s) 414. The I/O interface(s) 414 may similarly connect to a display 422. The display 422 provides a mechanism to display data to a user and may be, for example, a computer monitor. - The present invention may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present invention.
- The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.
- Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.
- Computer readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present invention.
- Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.
- These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.
- The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
- The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of computer program instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (18)
1. A computer-implemented method comprising:
receiving a unit, said unit comprising one or more blocks;
selecting one or more input pins for each of said one or more blocks;
assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence;
for each numerical sequence of said at least one numerical sequence, performing a check on said numerical sequence to yield a number of fails;
determining a simulation condition for power modeling of said unit based on optimizing a numerical sequence with respect to said number of fails; and
determining a number of design errors of said unit based on said simulation condition.
2. The computer-implemented method of claim 1 , wherein said unit comprises register transfer level content.
3. The computer-implemented method of claim 2 , wherein said register transfer level content is expressed in a hardware description language.
4. The computer-implemented method of claim 1 , wherein said numerical value is either zero or one.
5. The computer-implemented method of claim 1 , wherein said check comprises formal verification of each of said one or more blocks based on said numerical sequence of said one or more input pins.
6. The computer-implemented method of claim 1 , wherein said number of fails comprises a count of errors in said numerical sequence of said one or more input pins.
7. A computer program product, the computer program product comprising one or more computer readable storage media and program instructions stored on said one or more computer readable storage media, said program instructions comprising instructions to:
receive a unit, said unit comprising one or more blocks;
select one or more input pins for each of said one or more blocks;
assign a numerical value to each of said one or more input pins to yield at least one numerical sequence;
for each numerical sequence of said at least one numerical sequence, perform a check on said numerical sequence to yield a number of fails;
determine a simulation condition for power modeling of said unit based on optimizing a numerical sequence with respect to said number of fails; and
determine a number of design errors of said unit based on said simulation condition.
8. The computer program product of claim 7 , wherein said unit comprises register transfer level content.
9. The computer program product of claim 8 , wherein said register transfer level content is expressed in a hardware description language.
10. The computer program product of claim 7 , wherein said numerical value is either zero or one.
11. The computer program product of claim 7 , wherein said check comprises formal verification of each of said one or more blocks based on said numerical sequence of said one or more input pins.
12. The computer program product of claim 7 , wherein said number of fails comprises a count of errors in said numerical sequence of said one or more input pins.
13. A computer system, the computer system comprising:
one or more computer processors;
one or more computer readable storage media;
computer program instructions;
said computer program instructions being stored on said one or more computer readable storage media;
said computer program instructions comprising instructions to:
receive a unit, said unit comprising one or more blocks;
select one or more input pins for each of said one or more blocks;
assign a numerical value to each of said one or more input pins to yield at least one numerical sequence;
for each numerical sequence of said at least one numerical sequence, perform a check on said numerical sequence to yield a number of fails;
determine a simulation condition for power modeling of said unit based on optimizing a numerical sequence with respect to said number of fails; and
determine a number of design errors of said unit based on said simulation condition.
14. The computer system of claim 13 , wherein said unit comprises register transfer level content.
15. The computer system of claim 14 , wherein said register transfer level content is expressed in a hardware description language.
16. The computer system of claim 13 , wherein said numerical value is either zero or one.
17. The computer system of claim 13 , wherein said check comprises formal verification of each of said one or more blocks based on said numerical sequence of said one or more input pins.
18. The computer system of claim 13 , wherein said number of fails comprises a count of errors in said numerical sequence of said one or more input pins.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/041,068 US20170235856A1 (en) | 2016-02-11 | 2016-02-11 | Formal verification driven power modeling and design verification |
US15/139,454 US9460251B1 (en) | 2016-02-11 | 2016-04-27 | Formal verification driven power modeling and design verification |
US15/207,561 US9697306B1 (en) | 2016-02-11 | 2016-07-12 | Formal verification driven power modeling and design verification |
US15/678,158 US10354028B2 (en) | 2016-02-11 | 2017-08-16 | Formal verification driven power modeling and design verification |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/041,068 US20170235856A1 (en) | 2016-02-11 | 2016-02-11 | Formal verification driven power modeling and design verification |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/139,454 Continuation US9460251B1 (en) | 2016-02-11 | 2016-04-27 | Formal verification driven power modeling and design verification |
US15/678,158 Continuation US10354028B2 (en) | 2016-02-11 | 2017-08-16 | Formal verification driven power modeling and design verification |
Publications (1)
Publication Number | Publication Date |
---|---|
US20170235856A1 true US20170235856A1 (en) | 2017-08-17 |
Family
ID=56995286
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/041,068 Abandoned US20170235856A1 (en) | 2016-02-11 | 2016-02-11 | Formal verification driven power modeling and design verification |
US15/139,454 Expired - Fee Related US9460251B1 (en) | 2016-02-11 | 2016-04-27 | Formal verification driven power modeling and design verification |
US15/207,561 Expired - Fee Related US9697306B1 (en) | 2016-02-11 | 2016-07-12 | Formal verification driven power modeling and design verification |
US15/678,158 Expired - Fee Related US10354028B2 (en) | 2016-02-11 | 2017-08-16 | Formal verification driven power modeling and design verification |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/139,454 Expired - Fee Related US9460251B1 (en) | 2016-02-11 | 2016-04-27 | Formal verification driven power modeling and design verification |
US15/207,561 Expired - Fee Related US9697306B1 (en) | 2016-02-11 | 2016-07-12 | Formal verification driven power modeling and design verification |
US15/678,158 Expired - Fee Related US10354028B2 (en) | 2016-02-11 | 2017-08-16 | Formal verification driven power modeling and design verification |
Country Status (1)
Country | Link |
---|---|
US (4) | US20170235856A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170300604A1 (en) * | 2016-04-15 | 2017-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power consumption estimation method for system on chip (soc), system for implementing the method |
US10354028B2 (en) | 2016-02-11 | 2019-07-16 | International Business Machines Corporation | Formal verification driven power modeling and design verification |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3493051A1 (en) * | 2017-11-30 | 2019-06-05 | The MathWorks, Inc. | System and methods for evaluating compliance of implementation code with a software architecture specification |
DE102018003142A1 (en) | 2017-12-13 | 2019-06-13 | The Mathworks, Inc. | Automatic setting of multitasking configurations for a code checking system |
US11609832B2 (en) | 2019-10-04 | 2023-03-21 | International Business Machines Corporation | System and method for hardware component connectivity verification |
US11036905B1 (en) | 2020-01-06 | 2021-06-15 | International Business Machines Corporation | Hierarchical power analysis using improved activity abstraction and capacitance abstraction by accounting for design heterogeneity extremities |
US11853195B2 (en) | 2021-09-13 | 2023-12-26 | International Business Machines Corporation | Methods and systems to discover special outcomes in an instruction set architecture via formal methods |
Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020188916A1 (en) * | 2001-06-06 | 2002-12-12 | Hitachi, Ltd. | Integrated circuit, integrated circuit design method and hardware description generation method to generate hardware behavior description of integrated circuit |
US6499125B1 (en) * | 1998-11-24 | 2002-12-24 | Matsushita Electric Industrial Co., Ltd. | Method for inserting test circuit and method for converting test data |
US6678873B1 (en) * | 1999-11-16 | 2004-01-13 | Matsushita Electric Industrial Co., Ltd. | Method of designing semiconductor integrated circuit device |
US20080077893A1 (en) * | 2006-09-26 | 2008-03-27 | Texas Instruments Incorporated | Method for verifying interconnected blocks of IP |
US20100070942A1 (en) * | 2008-09-14 | 2010-03-18 | Raminda Udaya Madurawe | Automated Metal Pattern Generation for Integrated Circuits |
US7747971B1 (en) * | 2007-06-30 | 2010-06-29 | Cadence Design Systems, Inc. | State retention for formal verification |
US7774728B2 (en) * | 2004-11-26 | 2010-08-10 | Apache Design Solutions, Inc. | Method that allows flexible evaluation of power-gated circuits |
US8005660B2 (en) * | 2005-12-12 | 2011-08-23 | Anova Solutions, Inc. | Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture |
US20130125097A1 (en) * | 2011-11-15 | 2013-05-16 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US8898609B1 (en) * | 2006-07-18 | 2014-11-25 | Altera Corporation | Method and apparatus for integrating signal transition time modeling during routing |
US9311444B1 (en) * | 2014-07-10 | 2016-04-12 | Sandia Corporation | Integrated circuit test-port architecture and method and apparatus of test-port generation |
US20160154902A1 (en) * | 2014-11-30 | 2016-06-02 | Synopsys, Inc. | Selective Annotation Of Circuits For Efficient Formal Verification With Low Power Design Considerations |
US20160224700A1 (en) * | 2013-09-13 | 2016-08-04 | Centre National De La Recherche Scientifique - Cnrs | Method for Determining the Sizing of the Transistors of an Analog Circuit |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6598209B1 (en) | 2001-02-28 | 2003-07-22 | Sequence Design, Inc. | RTL power analysis using gate-level cell power models |
US6957403B2 (en) | 2001-03-30 | 2005-10-18 | Syntest Technologies, Inc. | Computer-aided design system to automate scan synthesis at register-transfer level |
WO2006063359A2 (en) * | 2004-12-10 | 2006-06-15 | Anova Solutions, Inc. | Stochastic analysis process optimization for integrated circuit design and manufacture |
US9262303B2 (en) | 2008-12-05 | 2016-02-16 | Altera Corporation | Automated semiconductor design flaw detection system |
US8601414B2 (en) | 2009-11-12 | 2013-12-03 | The Regents Of The University Of Michigan | Automated scalable verification for hardware designs at the register transfer level |
US8707229B1 (en) * | 2010-07-28 | 2014-04-22 | VSYNC Circuit, Ltd. | Static analysis of VLSI reliability |
US8650513B2 (en) * | 2010-09-20 | 2014-02-11 | Synopsys, Inc. | Reducing x-pessimism in gate-level simulation and verification |
US8954904B1 (en) * | 2013-04-30 | 2015-02-10 | Jasper Design Automation, Inc. | Veryifing low power functionality through RTL transformation |
US9104824B1 (en) * | 2013-04-30 | 2015-08-11 | Jasper Design Automation, Inc. | Power aware retention flop list analysis and modification |
US20170235856A1 (en) | 2016-02-11 | 2017-08-17 | International Business Machines Corporation | Formal verification driven power modeling and design verification |
-
2016
- 2016-02-11 US US15/041,068 patent/US20170235856A1/en not_active Abandoned
- 2016-04-27 US US15/139,454 patent/US9460251B1/en not_active Expired - Fee Related
- 2016-07-12 US US15/207,561 patent/US9697306B1/en not_active Expired - Fee Related
-
2017
- 2017-08-16 US US15/678,158 patent/US10354028B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6499125B1 (en) * | 1998-11-24 | 2002-12-24 | Matsushita Electric Industrial Co., Ltd. | Method for inserting test circuit and method for converting test data |
US6678873B1 (en) * | 1999-11-16 | 2004-01-13 | Matsushita Electric Industrial Co., Ltd. | Method of designing semiconductor integrated circuit device |
US20020188916A1 (en) * | 2001-06-06 | 2002-12-12 | Hitachi, Ltd. | Integrated circuit, integrated circuit design method and hardware description generation method to generate hardware behavior description of integrated circuit |
US7774728B2 (en) * | 2004-11-26 | 2010-08-10 | Apache Design Solutions, Inc. | Method that allows flexible evaluation of power-gated circuits |
US8005660B2 (en) * | 2005-12-12 | 2011-08-23 | Anova Solutions, Inc. | Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture |
US8898609B1 (en) * | 2006-07-18 | 2014-11-25 | Altera Corporation | Method and apparatus for integrating signal transition time modeling during routing |
US20080077893A1 (en) * | 2006-09-26 | 2008-03-27 | Texas Instruments Incorporated | Method for verifying interconnected blocks of IP |
US7747971B1 (en) * | 2007-06-30 | 2010-06-29 | Cadence Design Systems, Inc. | State retention for formal verification |
US20100070942A1 (en) * | 2008-09-14 | 2010-03-18 | Raminda Udaya Madurawe | Automated Metal Pattern Generation for Integrated Circuits |
US20130125097A1 (en) * | 2011-11-15 | 2013-05-16 | Global Supercomputing Corporation | Method and system for converting a single-threaded software program into an application-specific supercomputer |
US20160224700A1 (en) * | 2013-09-13 | 2016-08-04 | Centre National De La Recherche Scientifique - Cnrs | Method for Determining the Sizing of the Transistors of an Analog Circuit |
US9311444B1 (en) * | 2014-07-10 | 2016-04-12 | Sandia Corporation | Integrated circuit test-port architecture and method and apparatus of test-port generation |
US20160154902A1 (en) * | 2014-11-30 | 2016-06-02 | Synopsys, Inc. | Selective Annotation Of Circuits For Efficient Formal Verification With Low Power Design Considerations |
Non-Patent Citations (1)
Title |
---|
CHRISTOPH KERN et al., "Formal Verification In Hardware Design: A Survey", ACM 1999. * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10354028B2 (en) | 2016-02-11 | 2019-07-16 | International Business Machines Corporation | Formal verification driven power modeling and design verification |
US20170300604A1 (en) * | 2016-04-15 | 2017-10-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power consumption estimation method for system on chip (soc), system for implementing the method |
US10108764B2 (en) * | 2016-04-15 | 2018-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Power consumption estimation method for system on chip (SOC), system for implementing the method |
Also Published As
Publication number | Publication date |
---|---|
US9460251B1 (en) | 2016-10-04 |
US9697306B1 (en) | 2017-07-04 |
US20170344678A1 (en) | 2017-11-30 |
US10354028B2 (en) | 2019-07-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10354028B2 (en) | Formal verification driven power modeling and design verification | |
KR102523518B1 (en) | Method and apparatus for verifying chip, electronic device, storage medium and program | |
US10216252B2 (en) | Voltage and frequency balancing at nominal point | |
US10354042B2 (en) | Selectively reducing graph based analysis pessimism | |
US8418093B2 (en) | Method and system for design simplification through implication-based analysis | |
US8397187B2 (en) | Verifying the error bound of numerical computation implemented in computer systems | |
GB2519181A (en) | Clock verification | |
US10606970B2 (en) | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | |
US20160171141A1 (en) | Verification environments utilzing hardware description languages | |
US20180144090A1 (en) | Ranking combinations of mutants, test cases and random seeds in mutation testing | |
US10169502B2 (en) | Addressing of process and voltage points | |
US20140195785A1 (en) | Formal verification of a logic design | |
US10394987B2 (en) | Adaptive bug-search depth for simple and deep counterexamples | |
US9715564B2 (en) | Scalable and automated identification of unobservability causality in logic optimization flows | |
US8627248B1 (en) | Verification for functional independence of logic designs that use redundant representation | |
US9495504B2 (en) | Using traces of original model to verify a modified model | |
US10657209B2 (en) | Computing system and method of performing verification of circuit design in the computing system | |
US10437716B2 (en) | Method and apparatus for coverage analysis of SRT look-up table | |
US20170192485A1 (en) | Providing a power optimized design for a device | |
US7650579B2 (en) | Model correspondence method and device | |
KR101054706B1 (en) | Methods, systems and applications for sequential common factor based analysis of netlists | |
US11361136B2 (en) | Creating multiple use test case | |
US20160328509A1 (en) | Exploiting the scan test interface for reverse engineering of a vlsi device | |
GB2572632A (en) | Verification of hardware design for data transformation pipeline |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HARIDASS, ANAND;JOSEPH, ARUN;NALLA, PRADEEP KUMAR;AND OTHERS;REEL/FRAME:037702/0568 Effective date: 20160204 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |