EP2978575A1 - Verfahren zur kantenverrundung von aus einem festkörper-ausgangsmaterial erzeugten festkörper-teilstücken und mittels dieses verfahrens hergestellte festkörperprodukte - Google Patents
Verfahren zur kantenverrundung von aus einem festkörper-ausgangsmaterial erzeugten festkörper-teilstücken und mittels dieses verfahrens hergestellte festkörperprodukteInfo
- Publication number
- EP2978575A1 EP2978575A1 EP14720906.8A EP14720906A EP2978575A1 EP 2978575 A1 EP2978575 A1 EP 2978575A1 EP 14720906 A EP14720906 A EP 14720906A EP 2978575 A1 EP2978575 A1 EP 2978575A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- solid
- wafer
- starting material
- rounding
- cylindrical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000007787 solid Substances 0.000 title claims abstract description 46
- 239000007858 starting material Substances 0.000 title claims abstract description 43
- 239000012265 solid product Substances 0.000 title description 5
- 235000012431 wafers Nutrition 0.000 claims abstract description 107
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 238000005520 cutting process Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 28
- 229910052710 silicon Inorganic materials 0.000 description 28
- 239000010703 silicon Substances 0.000 description 28
- 239000004065 semiconductor Substances 0.000 description 24
- 239000000463 material Substances 0.000 description 12
- 239000013078 crystal Substances 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 239000002994 raw material Substances 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ATUUNJCZCOMUKD-OKILXGFUSA-N MLI-2 Chemical compound C1[C@@H](C)O[C@@H](C)CN1C1=CC(C=2C3=CC(OC4(C)CC4)=CC=C3NN=2)=NC=N1 ATUUNJCZCOMUKD-OKILXGFUSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000000543 intermediate Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
Definitions
- the invention relates to a method for edge rounding of generated from a solid starting material
- cylindrical or cuboid solid-state material more cylindrical, disc-shaped or cuboid solid sections are generated.
- the invention also relates to solid products produced by this method.
- a solid-state starting material is understood as meaning both a monocrystalline and a polycrystalline block consisting of silicon (semiconductor raw material), also referred to as ingots or ingots, from which wafers are produced in subsequent production process steps which are used to manufacture semiconductor chips or semiconductor chips
- a solid starting material may also be a sapphire.
- silicon sections are produced. These silicon sections may represent a wafer. In another case, these silicon sections are further subdivided until they have the desired thickness of a wafer to be produced.
- the rounding is done with a grindstone, for example
- DE 10 2012 001 620 A1 discloses a method in which an adhesive or an adhesive layer is applied to a film for producing thin wafer wafers. Two of the slides prepared in this way are each with their
- Adhesive layer applied to the top and bottom of the processed semiconductor blank. After this
- Curing the adhesive will thermally stress the wafer. Due to different thermal properties of wafer and polymer, the wafer breaks into two thinner halves. On both thin wafers now one side still still adheres a film which must be removed from the wafer surface in a subsequent step. Also with this
- Manufacturing process produces wafer slices with very sharp rupture edges which, as described above,
- the invention is therefore based on the object
- the object is achieved in a method for edge rounding of the aforementioned type, on a lateral surface of the cylindrical solid-state starting material (1) or the side surfaces of the
- cuboid solid-state starting material (1) at least one circumferential recess (7) is generated such that it is equally spaced at all its points to a base or top surface of the solid state starting material (1).
- a prior art for example, in silicon sections divided cylindrical silicon starting material has sharp circumferential edges, which for example, by means of one additional necessary
- the starting material may also have a cuboid shape.
- cylindrical solid state starting material to be carried out in solid sections is intended to be a circumferential on the lateral surface of the solid state starting material depression
- This recess is designed such that this is both a predetermined breaking point for a
- Groove generated along the four side surfaces running and has, for example, the top surface at each point the same distance.
- the method is particularly applicable to semiconductor starting materials or silicon Si wafers.
- a cylindrical, disc-shaped or cuboid solid-state section is a wafer.
- silicon sections are produced which can subsequently be further divided or already represent a wafer suitable for subsequent method steps.
- the recess is wedge-shaped and executed with a first and a second partial rounding.
- the recess formed at the same time is a wedge-shaped depression, which is designed in such a way that it has two partial roundings which, when assembled, represent the profile of the depression.
- the partial fillets can be made with the same radius as the rounding of an adjacent edge of the wafer. For example, the radius of the upper edges with the radius of the upper
- Each of these depressions is again circumferential and runs at a constant distance from an adjacent depression around the wafer circumferential surface. With three or more recesses, these may be arranged the same or different from each other.
- Disk-shaped solid-state portion is done.
- Wafer surface and run around the wafer may be formed on a first side as well as an upper side of the wafer as well as on a second side like a lower side of the wafer.
- both the two sharp peripheral edges of the wafer or section are eliminated in a working or process step in the processing of solid-state wafers or silicon sections as well as produces a depression.
- This recess is also encircling the outer edge of the wafer and extends, for example, centrally between the two rounded edges.
- the rounding of the wafer edges can be made such that each edge a rounding with the same or
- the wells are generated with different partial rounding and / or different depths.
- Predetermined breaking points in the silicon starting material or in the Sikizium sections for dividing the silicon material into two or more sections or wafer slices can be used by introducing the wells not only the position of a Predetermined breaking point, but also an order of breakup of the
- Break breaking point with the deepest depression and so on it is provided that with the production of the depressions, orientation features of a wafer, such as a notch and / or a fiat for aligning the wafer in a production and / or recognition of a disk type, are generated.
- orientation features of a wafer such as a notch and / or a fiat for aligning the wafer in a production and / or recognition of a disk type
- Orientation features at least attach to the wafers. These are referred to as Notch and Fiat and serve as an orientation in aligning the wafers on the basis the orientation of the semiconductor crystal structure (crystal orientation).
- the method provides, with an introduction of one or more circumferential recesses and the necessary
- the cylindrical solid-state starting material in which at least one circumferential recess is introduced, has a diameter which is equal to or greater than a target diameter of the wafers to be produced and that, in the case that the diameter is greater, after generating the recess and a subsequent dicing in
- the method can also be applied to solid state starting materials having a larger cylinder diameter than that of the solid body portion or wafer to be formed. In this case, the pits become
- Solid products such as one by means of the method
- the recess lying closest to the top surface extends in such a way that it has an equal distance from the top surface in all points which are imagined on its course.
- This depression is wedge-shaped with a first and a second partial rounding.
- the partial roundings can have the same rounding radius or
- n recesses have different rounding radii. It is also possible to introduce the n recesses with one and the same depth or with a different depth.
- the imaginary base and top surface described can also be considered as an imaginary base and top surface of an ingot.
- the produced ingots have
- the depressions are distributed at the same distance from one another over the entire lateral surface or the side surfaces of the ingot. Such is the ingot for several subsequent
- Solid state product is a wafer which passes through the
- Fig. 2a a plurality of recesses produced according to the invention on the mantle surface of a cylindrical
- FIG. 2b shows an application of the method in which
- Recesses are distributed over the entire lateral surface of the cylindrical starting material
- Fig. 2c is an application of the method in which
- Fig. 3 is a known from the prior art
- Process step of rounding the edges of a wafer by means of a grindstone 4 is a representation of the edge rounding according to the invention by means of a grindstone with a changed profile profile
- Fig. 5 a wafer rounded according to the invention
- FIG. 6 shows the wafer from FIG. 3 after cutting
- Fig. 7 shows a first alternative embodiment of
- FIG. 8 shows a second alternative embodiment of
- Edge rounding according to the invention for the preparation of two predetermined breaking points of a wafer with different depths in the edge rounding and
- FIG. 9 shows a further embodiment of the edge rounding on a wafer, on the upper side of which electronic components have already been produced in different solid-state production steps.
- FIG. 1a shows a cylindrical starting material (ingot) customary in semiconductor production for the production of wafers.
- This ingot is one manufactured, for example, by means of a Czochralski crystal pulling process by means of a crucible-free zone-pulling process
- FIG. 1b cylindrical starting material shown after a generation of silicon sections.
- the different heights of the illustrated silicon sections in FIG. 1b indicate that these silicon sections can be further subdividable sections or can already have a height required for a wafer.
- Recesses placed on the lateral surface of the cylindrical circumferential recesses can be introduced, for example, using a laser or mechanically by grinding.
- Recesses 7 distributed over the entire surface of the ingot 1 with uniform or uneven intervals to each other to install, as shown in Figure 2b.
- the entire ingot can be divided into individual wafers 3.
- This process of sharing typically involves several sub-steps in which at least one wafer 3 is generated per sub-step.
- FIG. 2 c shows an embodiment in which a number n of recesses 7 are distributed over the four side surfaces of a cuboid solid starting material 1.
- FIG. 3 shows a semiconductor wafer 3 with a whetstone 4 only partially shown, which has a
- Notch 6 in the form of a semicircle, as is known in the art.
- This grindstone 4 may consist of various materials, which is no
- the wafer 3 has prior to the rounding of the edges 5 by means of the grindstone 4 sharp-edged circumferential edges 5, which is shown in the figure 3 by the dot-dot line.
- FIG. 4 shows a grindstone 4 having an edge profile 6 which has been modified according to the invention and which has it
- circumferential recess 7 has two partial rounding 8, as shown in Figure 4 in the left portion of the wafer 3, two reference numerals 8 for a first and a second partial rounding 8 is shown.
- the recess 7 is located centrally between the edges 5 of the wafer 3.
- edges 5 Spacing to the edges 5 is not mandatory and can be changed arbitrarily within the technological possibilities.
- the edge 5 of the wafer 3 before the rounding is again shown as a dot-dot line. According to the invention, both the rounding of the edges 6 and the production of the recess 7 can be realized in the same operation.
- Figure 5 shows a wafer 3 after the straight
- the generated circumferential recess 7 leads to a
- the reduced diameter may be used to specify the location or the area at which or in which the wafer 3 or the silicon wafer Section 2 is shared. In this description, this point or this area is referred to as predetermined breaking point 9.
- Wafers 3 at the predetermined breaking point 9 no as in the prior art usual, sharp edges arise.
- the edge 6 of the wafer 3 or the silicon portion 2 formed at the predetermined breaking point is no longer a sharp edge, since it already has one of the partial roundings 8.
- the partial wafers 3 or silicon sections 2 with their already rounded edges produced after the division of the wafers 3 or of the silicon section 2 at the predetermined breaking point 9 are shown in FIG.
- the method is not based on generating a
- Well 7 limited to a wafer 3.
- an embodiment with two recesses 7 is shown in FIG. At both recesses 7 arises one each
- Predetermined breaking point 9 at which the division of the wafer takes place.
- the order of division of the wafer 3 or of the silicon section 2 can be predetermined. It can be assumed that the wafer 3 or the silicon section 2 breaks first at the predetermined breaking point 9 with the smallest diameter.
- Wafer 3 or the silicon section 2 in the figure 8 first at the upper predetermined breaking point 9 and subsequent to the break lower breaking point 9, with appropriate multiple application of the method for division of a
- the production of the depression 7 according to the invention can be carried out both before and after the processing of a wafer 3.
- the wafer 3 Before processing, for example, to produce partial wafers 3, as already described, and after processing, for example, to thin the semiconductor material layer. In this case, the wafer 3 can be manufactured and processed with normal edges. After the completion of the
- the wafer edges 5 are rounded with simultaneous production of the recess 7.
- a wafer 3 produced in this way is shown in FIG. After the introduction of the recess 7, the cutting takes place at the predetermined breaking point 9. Alternatively, the wafer 3 with already rounded edges 5 and the
- the predetermined breaking point 9 can be further characterized by further crystal damaging processes, such as by a
- the wafer thickness dimensions that are present are between 200 and 1500 pm before splitting or cutting so that the partial fillets have thicknesses of 100 to 800 pm.
- the generated recess 7 preferably has an acute angle, wherein the recess 7 can be performed at different depths.
- the method is particularly advantageous for a starting material such as silicon carbide SiC.
- a starting material such as silicon carbide SiC.
- the method is also suitable for materials such as a gallium nitride GaN.
- the rounded edges of a wafer 3 produced by means of the present invention correspond in particular to the standards and guidelines of the semiconductor industry SEMI® (Semiconductor Equipment and Materials International).
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Dicing (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102013205720 | 2013-03-28 | ||
DE102013113030.5A DE102013113030A1 (de) | 2013-03-28 | 2013-11-26 | Verfahren zur Kantenverrundung von Halbleiter-Wafern |
PCT/EP2014/056279 WO2014154863A1 (de) | 2013-03-28 | 2014-03-28 | Verfahren zur kantenverrundung von aus einem festkörper-ausgangsmaterial erzeugten festkörper-teilstücken und mittels dieses verfahrens hergestellte festkörperprodukte |
Publications (1)
Publication Number | Publication Date |
---|---|
EP2978575A1 true EP2978575A1 (de) | 2016-02-03 |
Family
ID=51519684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP14720906.8A Withdrawn EP2978575A1 (de) | 2013-03-28 | 2014-03-28 | Verfahren zur kantenverrundung von aus einem festkörper-ausgangsmaterial erzeugten festkörper-teilstücken und mittels dieses verfahrens hergestellte festkörperprodukte |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP2978575A1 (de) |
DE (1) | DE102013113030A1 (de) |
TW (1) | TW201446454A (de) |
WO (1) | WO2014154863A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015006971A1 (de) | 2015-04-09 | 2016-10-13 | Siltectra Gmbh | Verfahren zum verlustarmen Herstellen von Mehrkomponentenwafern |
DE102015008037A1 (de) | 2015-06-23 | 2016-12-29 | Siltectra Gmbh | Verfahren zum Führen eines Risses im Randbereich eines Spendersubstrats |
DE102015008034A1 (de) | 2015-06-23 | 2016-12-29 | Siltectra Gmbh | Verfahren zum Führen eines Risses im Randbereich eines Spendersubstrats |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07232319A (ja) * | 1994-02-24 | 1995-09-05 | M Setetsuku Kk | インゴットのスライス方法 |
DE4414373C2 (de) | 1994-04-25 | 1998-05-20 | Siemens Ag | Halbleiter-Wafer mit bearbeiteten Kanten |
JPH09290358A (ja) * | 1996-04-25 | 1997-11-11 | Komatsu Electron Metals Co Ltd | 半導体ウェハの製造方法および半導体インゴットの面 取り加工装置 |
JP4224871B2 (ja) * | 1998-06-09 | 2009-02-18 | 株式会社Sumco | 半導体基板の製造方法 |
DE19953131A1 (de) | 1999-11-04 | 2001-08-02 | Bosch Gmbh Robert | Verfahren und Vorrichtung zum Kantenverrunden |
DE102006060195A1 (de) * | 2006-12-18 | 2008-06-26 | Jacobs University Bremen Ggmbh | Kantenverrundung von Wafern |
DE102012001620A1 (de) | 2012-01-30 | 2013-08-01 | Siltectra Gmbh | Verfahren zur Herstellung von dünnen Platten aus Werkstoffen geringer Duktilität mittels temperaturinduzierter mechanischer Spannung unter Verwendung von vorgefertigten Polymer-Folien |
-
2013
- 2013-11-26 DE DE102013113030.5A patent/DE102013113030A1/de not_active Ceased
-
2014
- 2014-03-28 TW TW103111797A patent/TW201446454A/zh unknown
- 2014-03-28 WO PCT/EP2014/056279 patent/WO2014154863A1/de active Application Filing
- 2014-03-28 EP EP14720906.8A patent/EP2978575A1/de not_active Withdrawn
Non-Patent Citations (2)
Title |
---|
None * |
See also references of WO2014154863A1 * |
Also Published As
Publication number | Publication date |
---|---|
DE102013113030A1 (de) | 2014-10-02 |
TW201446454A (zh) | 2014-12-16 |
WO2014154863A1 (de) | 2014-10-02 |
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Owner name: SILTECTRA GMBH Owner name: FREIBERGER COMPOUND MATERIALS GMBH |
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