EP2932505A1 - Appareil et procédé de lecture de dispositif de stockage - Google Patents

Appareil et procédé de lecture de dispositif de stockage

Info

Publication number
EP2932505A1
EP2932505A1 EP13880647.6A EP13880647A EP2932505A1 EP 2932505 A1 EP2932505 A1 EP 2932505A1 EP 13880647 A EP13880647 A EP 13880647A EP 2932505 A1 EP2932505 A1 EP 2932505A1
Authority
EP
European Patent Office
Prior art keywords
storage device
ring oscillator
oscillation
series
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13880647.6A
Other languages
German (de)
English (en)
Other versions
EP2932505A4 (fr
Inventor
Robert J. Brooks
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Enterprise Development LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of EP2932505A1 publication Critical patent/EP2932505A1/fr
Publication of EP2932505A4 publication Critical patent/EP2932505A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/066—Frequency reading type sense amplifier

Definitions

  • a storage device such as a memristor
  • the electrical resistance increases, and when current flows in an opposite direction, the electrical resistance decreases.
  • the last resistance in the memristor is retained. Further, when the flow of charge begins again, the resistance of the memristor reverts to a value when the memristor was last active.
  • Such storage devices can be formed in an array configuration that includes a plurality of storage devices disposed, for example, in a row and column format. Each of the storage devices in the array can be individually addressed to read or write to the storage device. For example, a row and column can be individually addressed to read or write to a corresponding storage device.
  • Figure 1 illustrates an architecture of a storage device reading apparatus, according to an example of the present disclosure
  • Figure 2 illustrates a method for storage device reading, according to an example of the present disclosure
  • Figure 3 illustrates a computer system, according to an example of the present disclosure.
  • the terms “a” and “an” are intended to denote at least one of a particular element.
  • the term “includes” means includes but not limited to, the term “including” means including but not limited to.
  • the term “based on” means based at least in part on.
  • a ring oscillator may be connected between a row and column of a storage device, such as a memristor array, to read a bit stored in a memristor addressed by the row and column.
  • the ring oscillator exhibits a characteristic period of oscillation that can be used to determine a value of the bit in the memristor addressed by the row and column.
  • One technique for measuring the period of oscillation may include using an output of the ring oscillator to clock a counter for sufficient cycles to discriminate between frequencies that may be 10% or less different. This technique can take a relatively long time to determine the period of oscillation based, for example, on the number of cycles it can take to discriminate between different frequencies.
  • Another technique for measuring the period of oscillation may include using a counter clocked by a fixed clock that is of a significantly higher frequency than the ring oscillator. Such a counter can be started on an edge of the ring oscillator output, and stopped at a fixed number of edges later. However, such a counter can add complexities and additional power consumption needs to the overall read/write process.
  • the storage device reading apparatus may include a time-to-digital circuit (i.e., of a time-to-digital module) that is used to measure the period of oscillation of a ring oscillator.
  • the measured period of oscillation may be used to determine a value of a bit in a memristor addressed by a row and column in a memory array, such as a memristor array.
  • the time-to-digital circuit may include a series of buffers and a register (for example, a set of latches or flip-flops).
  • the ring oscillator output may be fed to the series of buffers and to a clock input of the register.
  • the length of the series of buffers may be chosen such that the fastest possible propagation delay time of the series of buffers is at least one-half of the longest period that the time- to-digital circuit is designed to measure.
  • a priority encoder circuit may be applied to the register output, and the resulting binary value may represent a measurement of the ring oscillator period. The use of the time-to-digital circuit minimizes any latency in measurement of the period of oscillation of a ring oscillator.
  • the method for storage device reading may include receiving an input signal which is the output of a ring oscillator coupled to a storage device of a plurality of storage devices, and measuring the period of oscillation of the ring oscillator by a time-to-digital circuit.
  • FIG. 1 illustrates an architecture of a storage device reading apparatus 100, according to an example.
  • the apparatus 100 is depicted as including a memory array control module 101 to control a memory array 102 and various other operations of the apparatus 100.
  • the memory array 102 may include a plurality of data storage devices 103, such as memristors. Each of the data storage devices 103 may be individually addressable by row address lines 104 and column address lines 105.
  • a row switch module 106 may couple various aspects of the apparatus 100 to selected ones of the storage devices 103 by the row address lines 104.
  • a column switch module 107 may couple various aspects of the apparatus 100 to selected ones of the storage devices 103 by the column address lines 105.
  • a ring oscillator 108 has a characteristic period of oscillation that can be used to determine a value of a bit in the particular storage device 103 addressed by the row address lines 104 and the column address lines 105.
  • An output 109 of the ring oscillator 108 may be fed to a time-to-digital module 110 that includes a time-to-digital circuit.
  • the output 109 of the ring oscillator 108 may be fed to a series of buffers 111 of the time-to-digital module 110.
  • the output of each of the buffers 111 may be fed to a corresponding flip-flop of a series of flip-flops 112.
  • the flip-flops 112 may be clocked with the oscillating signal of the ring oscillator 108, which is included in the output 109.
  • a priority encoder 113 may determine a binary value corresponding to the period of the ring oscillator 108.
  • the binary value corresponding to the period of oscillation of the ring oscillator 108 may be compared using a comparator 114 to a value stored in a threshold register 115.
  • the output of the comparison by the comparator 114 may be output at 116.
  • the apparatus 100 and the various components thereof may be implemented in hardware using a variety of digital logic circuits, such as system-on- chips (SoC), application-specific integrated circuits (ASIC), etc. Additionally or alternatively, the apparatus 100 and the various components thereof that perform various other functions in the apparatus 100, may comprise machine readable instructions stored on a non-transitory computer readable medium. In addition, or alternatively, the apparatus 100 and the various components thereof may comprise hardware or a combination of machine readable instructions and hardware.
  • SoC system-on- chips
  • ASIC application-specific integrated circuits
  • the memory array control module 101 may control the memory array 102 and various other operations of the apparatus 100.
  • the memory array control module 101 may store data values within the memory array 102, read data values from the memory array 102, control operations of the row switch module 106 and the column switch module 107, receive data values from and provide data values to a source of the apparatus 100, etc.
  • the memory array control module 101 may store (i.e., write or program) data values to the data storage devices 103, for example, by direct-current (DC) pulses formatted to increase or decrease the non-volatile electrical resistance of the selected data storage device 103.
  • the memory array control module 101 may also retrieve (i.e., read) data values stored in the data storage devices 103 by the ring oscillator 108.
  • the data storage devices 103 may store at least two distinct data values based on electrical characteristics thereof.
  • the data storage devices 103 may include electrical characteristics such as resistance, capacitance, inductance, or a combination thereof.
  • Each data storage device 103 may store one bit of binary data-value (e.g., 0 or 1) based on a non-volatile adjustment in electrical resistance thereof.
  • the data storage devices 103 may also store other types of data-values (e.g., base-three, base-eight, etc.).
  • the memory array 102 may include a plurality of the data storage devices 103, such as memristors. In the example of Figure 1 , the memory array 102 is illustrated as including twelve data storage devices 103.
  • the memory array 102 may include any number of the data storage devices 103.
  • Each of the data storage devices 103 may be individually addressable by one of the row address lines 104 and the column address lines 105 to write to or read stored data values.
  • the row switch module 106 may couple various aspects of the apparatus 100 to selected ones of the storage devices 103 by the row address lines 104.
  • the column switch module 107 may couple various aspects of the apparatus 100 to selected ones of the storage devices 103 by the column address lines 105.
  • the row and column switch modules 106 and 107 may include, field-effect transistors (FETs), pass FETs, pass gates, diodes, bipolar transistors, electromechanical switches, or other devices.
  • the ring oscillator 108 exhibits a characteristic period of oscillation that can be used to determine a value of a bit stored in the particular storage device 103 addressed by the row address lines 104 and the column address lines 105.
  • the ring oscillator 108 may be defined by or include an odd-number of logical inverter gates coupled in a series-circuit arrangement.
  • the ring oscillator 108 may include an input node 117 and an output node 118.
  • the ring oscillator 108 may also include the output 109 that is fed at the output node 118 to the time-to-digital module 110 that includes the time-to-digital circuit.
  • the ring oscillator 108 may be coupled to selected ones of the storage devices 103 by the row and column switch modules 106 and 107, respectively.
  • a particular storage device 103 may define part of a feedback pathway or loop when coupled to the ring oscillator 108 by the input node 117, the output node 118, the row switch module 106 and the column switch module 107.
  • a selected storage device 103 may be disposed in a series arrangement in a feedback loop with respect to the ring oscillator 108.
  • the feedback loop may be formed upon coupling of the selected storage device 103 with the ring oscillator 108 by the row switch module 106 and the column switch module 107.
  • the ring oscillator 108 may be selectively coupled to the storage devices 103 by the by the row address lines 104 and the column address lines 105 so as to establish a feedback loop.
  • the ring oscillator 108 may include a period of oscillation that can be used to determine a value of a bit stored in the particular storage device 103 addressed by the row address lines 104 and the column address lines 105. Generally, the period of the oscillation of the ring oscillator 108 may be measured to determine whether the storage device 103 addressed by the row address lines 104 and the column address lines 105 is in a high or a low resistance state. For example, the ring oscillator 108 may include a period of oscillation corresponding to a data value (e.g., a bit) stored in one of the storage devices 103 coupled thereto.
  • a data value e.g., a bit
  • the output 109 of the ring oscillator 108 may be fed to the series of buffers 111 of the time-to-digital module 110.
  • the output of each buffer of the series of buffers 111 may be fed to a corresponding flip-flop of the series of flip- flops112.
  • Each of the flip-flops 112 may be clocked with an un-buffered oscillating signal of the output 109 of the ring oscillator 108.
  • Each buffer of the series of buffers 111 may include a propagation delay.
  • the first flip-flop of the series of flip-flops112 records the value prior to the rising edge, that is, a zero.
  • the total delay of the buffers 111 exceeds one-half of the period of the output 109. That flip-flop of the series of flip-flops112, and flip-flops 112 further down the series see a value that was present prior to the previous falling edge of the output 109, that is, a one.
  • the location of the transition of the input signal to the series of buffers 111 from 1 to 0, or from 0 to 1 may correspond to the measurement of the period of oscillation of the ring oscillator 108.
  • the flip-flops 112 may be clocked with the unbuffered oscillating signal of the output 109 of the ring oscillator 108.
  • each of the flip-flops 112 may be a positively edged triggered flip-flop (e.g., 20 bits wide). At an instance that a positive edge on the flip-flop clock occurs, the result of the transition from 0 to 1 of the ring oscillator 108 will not have been observed by any of the buffers in the series of buffers 111. At this stage, a first bit of a flip-flop will record a 0.
  • All flip-flop bits thereafter will also record 0's until the ring oscillator 108 output signal (i.e., output 109) has been sufficiently delayed to see a previous 1 to 0 transition. At this point, the flip-flops 112 will see 1"s instead of 0's. Moreover, shorter periods of the ring oscillator 108 will result in that transition being seen earlier (that is, more leftward) as a parallel output of the flip- flop bits.
  • the length of the series of the buffers 111 may be chosen such that the fastest possible propagation delay time of the series of the buffers 111 is at least one-half of the longest period that the time-to-digital module 110 is designed to measure. For example, if the length of the series of the buffers 111 is too short (e.g., less than 1 ⁇ 2 of the longest possible period of oscillation of the ring oscillator 108), then for the longest period of oscillation of the ring oscillator 108, the most delayed signal at the far end of the series of the buffers 111 would still result in a value of 0.
  • a length of the series of the buffers 111 (i.e., the number of buffers needed) may be determined by dividing the longest possible period of oscillation of the ring oscillator 108 by 2, and dividing the result by the propagation delay of each buffer of the series of buffers 111.
  • the priority encoder 113 may include a find-first-one circuit (or a find- first-zero circuit) to determine a binary value corresponding to the period of oscillation of the ring oscillator 108.
  • the priority encoder 113 may receive a series of 1's followed by 0's, or vice versa, from the flip-flops 112, and encode the received series into a binary value.
  • the priority encoder 113 may include a set of parallel inputs form the flip-flops 112 and generate a binary encoded output.
  • the priority encoder 113 includes 20 bits of input and 5 bits of output, if the last bit in the flip-flops 112 (that is, the rightmost bit) is a 1 and the remaining bits are 0, then the output of the priority encoder 113 is a binary 1 (i.e., 00001). According to another example, if the priority encoder 113 includes 20 bits of input and 5 bits of output, if the second bit (that is, second from left most bit) in the flip-flops 112 is a 1 , then the output of the priority encoder 113 is a binary 19 (i.e., 10011).
  • an output corresponding to a low number may correspond to a low frequency of the ring oscillator 108 (e.g., a first value of a bit stored in a storage device 103), and an output corresponding to a high number may correspond to a high frequency ring oscillator 108 (e.g., a second value of a bit stored in the storage device 103).
  • a threshold may be set such that a lower number on the output of the priority encoder 113 causes the comparator 114 to drive a logic zero, and a higher number then the threshold causes the comparator 114 to drive a logic one, or vice- versa. For example, if a storage device 103 stores a 1 or 0, the threshold may be set in a middle of the possible range of outputs of the priority encoder 113.
  • Figure 2 illustrates a flowchart of method 200 for storage device reading, corresponding to the example of the storage device reading apparatus 100 whose construction is described in detail above.
  • the method 200 may be implemented on the storage device reading apparatus 100 with reference to Figure 1 by way of example and not limitation. The method 200 may be practiced in other apparatus.
  • an input signal indicative of a period of oscillation of a ring oscillator coupled to a storage device of a plurality of storage devices may be received.
  • the time-to-digital module 110 of the memory array control module 101 may receive an input signal (i.e., the output 109 of the ring oscillator 108) exhibiting a characteristic period of oscillation of the ring oscillator 108 coupled to a storage device 103 of a plurality of storage devices (i.e., the memory array 102).
  • the period of oscillation of the ring oscillator may be measured by a time-to-digital circuit.
  • the period of oscillation of the ring oscillator 108 may be measured by the time-to-digital circuit
  • time-to-digital module 110 that includes a time-to-digital circuit
  • a value of data stored in the storage device may be determined based on the measurement. For example, referring to Figure 1 , a value of data stored in the storage device 103 may be determined based on the measurement.
  • Figure 3 shows a computer system 300 that may be used with the embodiments described herein.
  • the computer system 300 may represent a generic platform that may include components that may be in a server or another computer system.
  • the computer system 300 may be used as a platform for the apparatus 100.
  • the computer system 300 may execute, by a processor or other hardware processing circuit, the methods, functions and other processes described herein.
  • These methods, functions and other processes may be embodied as machine readable instructions stored on computer readable medium, which may be non-transitory, such as, for example, hardware storage devices (e.g., RAM (random access memory), ROM (read only memory), EPROM (erasable, programmable ROM), EEPROM (electrically erasable, programmable ROM), hard drives, and flash memory).
  • hardware storage devices e.g., RAM (random access memory), ROM (read only memory), EPROM (erasable, programmable ROM), EEPROM (electrically erasable, programmable ROM), hard drives, and flash memory).
  • the computer system 300 may include a processor 302 that may implement or execute machine readable instructions performing some or all of the methods, functions and other processes described herein. Commands and data from the processor 302 may be communicated over a communication bus 304.
  • the computer system 300 may also include a main memory 306, such as, for example, a random access memory (RAM), where the machine readable instructions and data for the processor 302 may reside during runtime, and a secondary data storage 308, which may be non-volatile and stores machine readable instructions and data.
  • the memory and data storage may be examples of computer readable mediums.
  • the memory 306 may include a storage device reading module 320 including machine readable instructions residing in the memory 306 during runtime and executed by the processor 302.
  • the storage device reading module 320 may include the modules of the apparatus 100 shown in Figure 1.
  • the computer system 300 may include an I/O device 310, such as, for example, a keyboard, a mouse, a display, etc.
  • the computer system 300 may include a network interface 312 for connecting to a network.
  • Other known electronic components may be added or substituted in the computer system 300.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Manipulation Of Pulses (AREA)
  • Hall/Mr Elements (AREA)

Abstract

Selon un exemple de l'invention, un procédé de lecture de dispositif de stockage peut consister à recevoir un signal d'entrée indiquant une période d'oscillation d'un oscillateur en anneau couplé à un dispositif de stockage d'une pluralité de dispositifs de stockage, et à mesurer la période d'oscillation de l'oscillateur en anneau par un circuit de conversion temps-numérique. Le procédé de lecture de dispositif de stockage peut consister en outre à déterminer une valeur de données stockées dans le dispositif de stockage sur la base de la mesure.
EP13880647.6A 2013-03-28 2013-03-28 Appareil et procédé de lecture de dispositif de stockage Withdrawn EP2932505A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2013/034409 WO2014158170A1 (fr) 2013-03-28 2013-03-28 Appareil et procédé de lecture de dispositif de stockage

Publications (2)

Publication Number Publication Date
EP2932505A1 true EP2932505A1 (fr) 2015-10-21
EP2932505A4 EP2932505A4 (fr) 2016-08-10

Family

ID=51624952

Family Applications (1)

Application Number Title Priority Date Filing Date
EP13880647.6A Withdrawn EP2932505A4 (fr) 2013-03-28 2013-03-28 Appareil et procédé de lecture de dispositif de stockage

Country Status (5)

Country Link
US (1) US9514812B2 (fr)
EP (1) EP2932505A4 (fr)
JP (1) JP2016514338A (fr)
CN (1) CN104956442A (fr)
WO (1) WO2014158170A1 (fr)

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* Cited by examiner, † Cited by third party
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US9824753B2 (en) * 2015-10-21 2017-11-21 Technische Universiteit Delft Computing device for “big data” applications using memristors
TWI730091B (zh) 2016-05-13 2021-06-11 日商半導體能源研究所股份有限公司 半導體裝置

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Also Published As

Publication number Publication date
WO2014158170A1 (fr) 2014-10-02
EP2932505A4 (fr) 2016-08-10
JP2016514338A (ja) 2016-05-19
CN104956442A (zh) 2015-09-30
US20160042787A1 (en) 2016-02-11
US9514812B2 (en) 2016-12-06

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