EP2783391A1 - Procédé pour mettre en contact un semi-conducteur et dispositif de mise en contact destiné à un semi-conducteur - Google Patents

Procédé pour mettre en contact un semi-conducteur et dispositif de mise en contact destiné à un semi-conducteur

Info

Publication number
EP2783391A1
EP2783391A1 EP12797791.6A EP12797791A EP2783391A1 EP 2783391 A1 EP2783391 A1 EP 2783391A1 EP 12797791 A EP12797791 A EP 12797791A EP 2783391 A1 EP2783391 A1 EP 2783391A1
Authority
EP
European Patent Office
Prior art keywords
semiconductor
contact
solder
layer
partner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP12797791.6A
Other languages
German (de)
English (en)
Inventor
Erik Sueske
Eckart Geinitz
Gerhard Braun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2783391A1 publication Critical patent/EP2783391A1/fr
Pending legal-status Critical Current

Links

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    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the invention is based on a method for contacting a semiconductor according to the preamble of independent claim 1 and of a contact arrangement for a semiconductor according to the preamble of independent claim 5.
  • components for producing a contact arrangement are usually used as components without housing, so-called “bare-dies", on substrates such as Direct Bonded Copper (DBC), insulated metal Solders (IMS), etc., and / or soldered to printed circuit boards and / or punched grid or the like .
  • the semiconductors are connected to at least a first surface by forming a first solder layer having a predetermined thickness, flat with at least one first contact partner Problem here is that the
  • Semiconductors can blur without lateral guidance on the solder layer, so that the semiconductor does not maintain the original position, but moves laterally on the substrate. This lateral movement can be prevented by suitable measures. These measures vary from contact partner to contact partner.
  • the semiconductor is not only soldered on the contact surface facing the first contact partner, but also contacted with a second contact partner by forming a second solder layer with a second contact surface. This will be the first
  • the bottom is usually an insulated metal block for heat storage or heat spreading, but may also be a different substrate.
  • a solder layer is provided on a solder joint of the device, wherein the solder joint is arranged on the surface facing the respective carrier. Furthermore, at least one recess of the respective carrier for receiving a Lotüberschusses and / or for a solder limit on the surface of the carrier is provided.
  • the carrier surface with the recess facing the solder joint of the device is provided.
  • a contact arrangement for a component is described.
  • the component is connected on at least one first surface by forming a first solder layer areally with at least one first contact partner, wherein the first contact partner is designed as an electrical contact clip.
  • the component is connected to a second surface by forming at least one second solder layer surface with a second contact partner.
  • solder-repellent layer is applied as a limiting means, which the dimensions and / or the shape specifies at least one soldering surface of the semiconductor and prevents blurring and / or lateral breaking of the semiconductor during the soldering process.
  • solder-repellent layer are materials that prevent wetting of the layer with the solder, such as polyimides.
  • Polyimides are high-performance plastics whose most important structural feature is the imide group.
  • purely aerodynamic matic polyimides generally not meltable and chemically very resistant, even to many solvents. Because of heat resistance, low outgassing, radiation resistance, insulating properties, and the property that common solder does not adhere to a polyimide film, polyimide solutions are very useful as a coating agent for confining one
  • Embodiments of the present invention advantageously prevent the lateral blurring and / or twisting of the semiconductor during soldering, and offer advantages over other known solutions, in particular in double-sided soldering of the semiconductor.
  • the solder-repellent layer advantageously protects the regions of the semiconductor which are not to come into contact with the solder and provides for a simple and rapid formation of the soldering surface by forming recesses in the solder-repellent layer.
  • the solder-repellent coating is already part of the semiconductor package.
  • the essential idea of the present invention is based on the fact that the applied solder can be held on the semiconductor within a certain soldering area by the solder-repellent layer.
  • solder-repellent layer for example a polyimide layer, is applied to the semiconductor as a limiting agent, which predetermines the dimensions and / or the shape of at least one soldering surface of the semiconductor.
  • a contact arrangement is proposed for a semiconductor which is connected to at least one first surface by forming a first solder layer having a predetermined thickness in a planar manner with a first contact partner.
  • a solder-repellent layer for example a polyimide layer, applied as a limiting means on the semiconductor, which dictates the dimensions and / or the shape of at least one soldering surface of the semiconductor.
  • Embodiments of the invention advantageously connect a semiconductor flat to a first contact surface of a first contact partner, so that a low electrical resistance with a homogeneous current distribution and a high power density can be realized on the semiconductor.
  • the lateral distance between at least one contact surface of the at least first contact partner and the edge of the solder-repellent layer is selected as a function of the thickness of the solder layer. Due to the distance, a maximum tolerance range can be predetermined in an advantageous manner, in which blurring of the semiconductor is possible. This is particularly advantageous if too much solder is applied during the soldering process.
  • the edges of the at least one contact surface of the first contact partner can be rounded off.
  • the rounding of the edges can preferably be achieved by introducing an impression on a side of the first contact partner opposite the contact surface.
  • the rounded geometry of the at least one first contact surface advantageously avoids the mechanical contact between an edge of the semiconductor and the first contact partner even with a strong tilt of the semiconductor and the first contact partner.
  • the critical active structures in the edge region can thus be protected in an advantageous manner.
  • the at least one contact surface of the first contact partner to be contacted can be adapted to the at least one soldering surface of the semiconductor and ideally correspond to it.
  • the contact surface of the at least one first contact partner can be designed so that the solder flows on the semiconductor to the limiting solder-repellent layer and on the contact surface of the first contact partner to the edges of the contact surface.
  • the entire contact surface available for contacting can advantageously be used, so that significant advantages in terms of current distribution, electrical resistance and thermal dissipation can result.
  • the mechanical stresses on the edges of the semiconductor can advantageously be reduced and thus damage to the semiconductor avoided.
  • the semiconductor can be connected in a flat manner to a second surface by forming at least one second solder layer with a second contact partner.
  • substrates such as rectified-bonded copper (DBC), insulated metal substrates (IMS), etc., and / or circuit boards and / or lead frames and / or heat dissipation elements ,
  • the distance between the at least one contact surface of the at least first contact partner and the edge of the solder-repellent layer corresponds to two to four times the thickness of the solder layer.
  • the thickness of the solder layer is about 50 to 100 ⁇ and the corresponding lateral distance is then preferably in the range of 100 to 400 ⁇ .
  • the semiconductor is connected in a planar manner to a second contact area by forming a second solder layer on a second surface.
  • the first contact partner can be embodied, for example, as a bracket and / or as a metal clip and / or as a bridge, wherein the semiconductor is electrically connected to at least one component via the first contact partner.
  • the second contact partner can, for example, as a substrate and / or as a printed circuit board and / or be executed as a stamped grid and / or as a heat sink.
  • the semiconductor can advantageously be connected to the other components for the purpose of transmitting high powers with a low contact resistance.
  • the semiconductor can be connected to a current source and / or voltage source and / or another semiconductor component.
  • the semiconductor can be connected to different second contact partners, which advantageously enables a situation-adapted material selection.
  • materials may be selected which may have insulating and / or cooling and / or heat-storing and / or heat-conducting properties.
  • semiconductors can advantageously be combined with first contact partners, which have a good electrical conductivity, and with second contact partners, which enable a high thermal dissipation. This advantageously increases the life and / or reliability of the semiconductor.
  • the second solder layer extends with the second contact partner substantially parallel to the first solder layer with the first contact partner.
  • the first contact partner may have a continuous contact surface or a plurality of contact surfaces.
  • additional edges can advantageously be used on the semiconductor, which ensure even less twisting and / or blurring of the semiconductor during the soldering process.
  • gate fingers are located on large semiconductors. These are metal strips which come from a gate via an emitter surface but are isolated from it. The gate fingers serve to bring a gate signal to the cells faster than would be possible via the semiconductor structure.
  • the gate fingers are like the semiconductor edge up with a solder-repellent layer, such as a polyimide layer isolated.
  • the upper semiconductor surface can be segmented into additional soldering surfaces, which can be used as additional anti-sweat protection.
  • the segmented surfaces are simulated, for example, through slots in the bracket just there in the area, so that when solder wetting additional individual solder surfaces arise.
  • the edge length at which the solder can attack can be increased and the risk that the semiconductor may be damaged during the process
  • Soldering blurs can be further reduced.
  • a metal clip can be used, which covers the entire surface of the conductor by an embossed structure.
  • the edge structures of the metal clip prevent mechanical stress on the edges of the semiconductor by being impressed.
  • solder-repellent material for example polyimide strips
  • gate fingers segment the upper semiconductor surface into additional soldering surfaces but have no electrical function.
  • These polyimide strips advantageously provide a twisting and / or Verschwimmtikes of the semiconductor during the soldering process.
  • the solder-repellent layer may generally be designed in such a way that it completely surrounds at least one soldering surface of the semiconductor, for example forming a rectangular or circular soldering surface. In this way, when adapting the contact surface of a first contact partner to the shape and size of the bordered soldering surface of the semiconductor, blurring of the semiconductor by the adhesion forces starting from the border in any direction is prevented. For the same reason twisting of the semiconductor is also not possible.
  • the solder-repellent layer presents only a part of a border of at least one soldering surface of the semiconductor.
  • the solder-repellent layer is designed in the form of two strip sections spaced parallel to one another, wherein the at least one soldering surface is provided between the two strip sections.
  • the solder-repellent Layer constitutes a limiting means at least in the area of its adjacency to the soldering surface and in this way determines the dimension and / or the shape of the at least one soldering surface.
  • Fig. 1 shows a schematic perspective view of a first embodiment of a contact arrangement according to the invention.
  • Fig. 2 shows a schematic perspective view of a second embodiment of a contact arrangement according to the invention.
  • FIG. 3 shows a schematic sectional representation of a third exemplary embodiment of a contact arrangement according to the invention.
  • FIG. 4 shows an enlarged detail which shows the lateral distance between the contact surface of the first contact element and the polyimide layer of the schematic sectional illustration from FIG. 3.
  • the illustrated embodiments of a contact arrangement 1, V, 1 "comprise a semiconductor 10, 10 ', 10" which is formed on at least one first surface by forming a first solder layer 30, 32', 34 '. , 36 ', 30 "having a predetermined thickness LD areally connected to at least one first contact partner 20, 20', 20" 60 ".
  • a polyimide layer 14, 14 ', 14 " is applied as limiting means on the semiconductor 10, 10', 10", which has the dimensions and / or the shape of at least one soldering surface 12, 12 ', 12 "of the semiconductor 10, 10'. , 10 "pretends.
  • the first solder layer 30, 32 ', 34', 36 ', 30 ", 80" is advantageously supported by the polyimide layer 14, 14', 14 ", 18 'within the predetermined area of the solder pad 12, 12', 12" the semiconductor 10, 10 ', 10 "held.
  • the illustrated embodiments are suitable for high-power applications, in particular for those applications in which high power must be switched, and the semiconductor switches, such as Power MOS FET (Power Metal Oxide Semiconductor Field Effect Transistors) and / or IGBT (Insulated Gate Bipolar Transistors).
  • the semiconductor switches such as Power MOS FET (Power Metal Oxide Semiconductor Field Effect Transistors) and / or IGBT (Insulated Gate Bipolar Transistors).
  • the polyimide layer 14, 14 ', 18' frames the at least one solder pad 12, 12 'on the semiconductor, with a lateral spacing A, which will be described in more detail below with reference to FIG in that the shortest distance between an inner edge of the polyimide layer 14, 14 ', 18' and an outer edge of the contact surface 20.2, 22.2 ', 24.2', 26.2 'of the first contact partner 20, 20' is defined.
  • Polyimide is particularly suitable as a limiting agent, since this material withstands high temperatures and can be easily applied, for example in the form of a thin film. Furthermore, conventional solders do not adhere to polyimide.
  • the semiconductor 10, 10 ', 10 "in the illustrated embodiments on a second surface by forming a second solder layer 50, 50', 50" areally with a second contact partner 40, 40 '
  • the first contact partner 20, 20 ', 20 "and / or a third contact partner 60" is designed as a metal bracket and / or as a metal clip and / or as a metal bridge
  • the first and / or third contact partner 20, 20' , 20 "electrically connect the semiconductor 10, 10 ', 10" to at least one further component 70 ", 90", wherein the first and / or third contact partners 20, 20' each have a solder layer 72 ", 92" with the components 70 3, 90.
  • the second contact partner 40, 40 ', 40 is designed as a substrate and / or as a printed circuit board and / or as a stamped grid and / or as a heat dissipation element. Furthermore, the second solder layer 50, 50 ', 50 "extends. with the second contact partner 40, 40 ', 40 "substantially parallel to the first solder layer 30, 32', 34 ', 36', 30" with the first contact partner 20, 20 ', 20 ", 60".
  • the second contact partner 40 'in the exemplary embodiment illustrated also has an insulation layer 40.1' and is designed as an insulated metal block for heat storage or spreading.
  • the first contact partner 20 has a continuous contact surface 20. 2, the edges of the at least one contact surface 20. 2 of the first contact partner 20 being rounded off.
  • the rounding off of the edges can be achieved, in particular, by the introduction of an embossing 20.4 on an opposite side of the first contact partner 20 to the contact surface 20.2.
  • the contact surface 20.2 can be easily and quickly adapted to the dimension of the solder pad 12 of the semiconductor 10, in which the impression 20.4 corresponds in shape and size of the solder pad 12 of the semiconductor.
  • the adhesion and / or slipping of the semiconductor 10 during a soldering operation can advantageously be prevented by utilizing the adhesion forces that occur. Due to the shape of the yoke support and the adhesion forces of the solder layer 30, it is not possible for the semiconductor 10 to twist or blur during the soldering process.
  • the first contact partner 20 embodied as a bracket is embodied such that the solder is distributed on the semiconductor 10 in such a way that it flows as far as the limiting polyimide layer 14 on which the solder does not adhere. On executed as a bracket first contact partner 30, the solder flows to the edges of the temple support.
  • the first contact partner 20 ' has a plurality of contact surfaces 22.2', 24.2 ', 26.2'.
  • the semiconductor 10 ' has a plurality of solder pads 12' which are separated by so-called gate fingers 16 '. These are metal strips which run from a gate over an emitter surface but are isolated from it.
  • These gate fingers 16 ' are usually insulated upwards with a polyimide cover 18' or polyimide layer.
  • the first contact partner 20 ' has corresponding conductor structures 22', 24 ', 26' with a plurality of contacts.
  • a first contact surface 26.2 'of a first conductor pattern 26' corresponding to the emitter surface can be adapted via grinding and / or etching and / or bending. Furthermore, the edge of the first conductor structure 26 'is not rounded on both sides.
  • a second conductor pattern 24 ' has the shape of a cuboid, wherein the edges of the contact surface 22.4' are not rounded.
  • a third conductor structure 22 ' has two rounded edges, which are formed by an impression 20.4' on an opposite side of the contact surface 22.2 '.
  • the described conductor structures 22 ', 24', 26 ' are possible embodiments, although other shapes and manufacturing methods for the separated conductor structures 22', 24 ', 26' are possible.
  • the contact surfaces 20.2 ', 22.4', 22.6 can be varied.
  • more or less gate fingers 16 'and correspondingly more or less corresponding conductor patterns 22', 24 ', 26' can be formed.
  • additional polyimide strips are formed on the semiconductor 10 'which, in accordance with the above-described gate fingers 16', segment the upper semiconductor surface into additional soldering surfaces but have no electrical function.
  • the first surface of the semiconductor 10 ' is segmented into additional solder pads 12'.
  • the segmented surfaces 12 ' for example, through slots in the metal bracket just there on the semiconductor 10' replicated, so that in the solder wetting individual solder surfaces 12 'arise.
  • the edge length at which the solder can attack be increased and the Verschwimmrisiko of the semiconductor 10 'can be further reduced.
  • the first surface of the semiconductor 10 is likewise segmented by polyimide layers 14", the solder surfaces 12 "of at least two contact partners 20", 60 “thus produced by solder layers 30". , 80 "with a given thickness
  • the Semiconductor 10 via the first contact partner 20" and via a fourth solder layer 72 "connected to a first component 70" and connected via the third contact partner 60 "and a fifth solder layer 92" with a second component 90 ". via the first and / or third contact partners 20 ", 60", for example, to a power source and / or voltage source and / or another semiconductor device.
  • the polyimide layer 14 " is provided such that the lateral spacing A between the at least one contact surface 20.2" of the at least one first contact partner 20 "and the edge of the polyimide layer 14" of the two- to four-fold solder layer thickness LD equivalent.
  • the thickness LD of the solder layer 30 " for example, about 50 to 100 ⁇ and the lateral distance A is then preferably in the range of 100 to 400 ⁇ .
  • the semiconductor 10, 10', 10" on at least a first surface by forming a first solder layer 30, 32 ', 34', 36 ', 30 ", 80 "with a predetermined thickness LD areally connected to at least one first contact partner 20, 20 ', 20", 60 ".
  • a polyimide layer 14, 14 ', 14 ", 18' is applied to the semiconductor 10, 10 ', 10" as limiting means, which have the dimensions and / or the shape of at least one soldering surface 12, 12', 12 "of the semiconductor 10 , 10 ', 10 "pretends.
  • the lateral spacing A between at least one contact surface 20.2, 22.2 ', 24.2', 26.2 ', 20.2 "of the at least first contact partner 20, 20', 20", 60 "and the edge of the polyimide layer 14, 14 ', 14", 18 ' is selected as a function of the thickness LD of the solder layer 30, 32', 34 ', 36', 30 ", 80".
  • edges of the at least one contact surface 20.2, 22.2 ', 24.2', 26.2 ', 20.2 "of the first contact partner 20, 20', 20", 60 " are rounded, wherein the rounding of the edges, in particular by the introduction of an impression 20.4, 20.4 ' on one of the contact surface 20.2, 22.2 ', 24.2', 26.2 ', 20.2 "opposite side of the first contact partner 20, 20', 20", 60 "is achieved.
  • the semiconductor 10, 10 ', 10 "on a second surface by forming at least one second solder layer 50, 50', 50" areally connected to a second contact partner 40, 40 ', 40 ".

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Die Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un procédé pour mettre en contact un semi-conducteur (10) ainsi qu'un dispositif de mise en contact (1) destiné à un semi-conducteur (10), le semi-conducteur (10) étant relié de manière superficielle à un premier partenaire de contact (20) au niveau d'une première surface, par formation d'une première couche de brasure (30) ayant une épaisseur prédéterminée. Selon l'invention, une couche de polyimide (14) est appliquée sur le semi-conducteur (10) en tant que moyen de délimitation, ladite couche prédéfinissant les dimensions et/ou la forme d'au moins une surface de brasure (12) du semi-conducteur (10).
EP12797791.6A 2011-11-21 2012-11-20 Procédé pour mettre en contact un semi-conducteur et dispositif de mise en contact destiné à un semi-conducteur Pending EP2783391A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011086687A DE102011086687A1 (de) 2011-11-21 2011-11-21 Verfahren zum Kontaktieren eines Halbleiters und Kontaktanordnung für einen Halbleiter
PCT/EP2012/073074 WO2013076064A1 (fr) 2011-11-21 2012-11-20 Procédé pour mettre en contact un semi-conducteur et dispositif de mise en contact destiné à un semi-conducteur

Publications (1)

Publication Number Publication Date
EP2783391A1 true EP2783391A1 (fr) 2014-10-01

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US (1) US9281270B2 (fr)
EP (1) EP2783391A1 (fr)
CN (1) CN103959449B (fr)
DE (1) DE102011086687A1 (fr)
WO (1) WO2013076064A1 (fr)

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DE102018130147A1 (de) 2018-11-28 2020-05-28 Infineon Technologies Ag Halbleitervorrichtung und verfahren zum herstellen einer halbleitervorrichtung
EP3832705A4 (fr) * 2018-11-30 2021-09-15 Hitachi Metals, Ltd. Élément de connexion électrique, structure de connexion électrique et procédé de production d'élément de connexion électrique

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US5001545A (en) 1988-09-09 1991-03-19 Motorola, Inc. Formed top contact for non-flat semiconductor devices
US4935803A (en) 1988-09-09 1990-06-19 Motorola, Inc. Self-centering electrode for power devices
US5850026A (en) 1996-07-03 1998-12-15 Cargill, Incorporated Canola oil having increased oleic acid and decreased linolenic acid content
US6677669B2 (en) * 2002-01-18 2004-01-13 International Rectifier Corporation Semiconductor package including two semiconductor die disposed within a common clip
DE10332695A1 (de) 2003-07-18 2005-02-03 Robert Bosch Gmbh Anordnung zur Befestigung eines Bauelements
TWI304234B (en) 2005-03-04 2008-12-11 Int Rectifier Corp Semiconductor package fabrication
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KR20110124993A (ko) * 2010-05-12 2011-11-18 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지 및 반도체 칩의 제조 방법

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US9281270B2 (en) 2016-03-08
CN103959449A (zh) 2014-07-30
DE102011086687A1 (de) 2013-05-23
WO2013076064A1 (fr) 2013-05-30
US20140299998A1 (en) 2014-10-09
CN103959449B (zh) 2017-06-30

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