EP2675247A1 - Dispositif de commande de source lumineuse - Google Patents

Dispositif de commande de source lumineuse Download PDF

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Publication number
EP2675247A1
EP2675247A1 EP13171471.9A EP13171471A EP2675247A1 EP 2675247 A1 EP2675247 A1 EP 2675247A1 EP 13171471 A EP13171471 A EP 13171471A EP 2675247 A1 EP2675247 A1 EP 2675247A1
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EP
European Patent Office
Prior art keywords
voltage
bypass switch
bypass
circuit
semiconductor light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP13171471.9A
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German (de)
English (en)
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EP2675247B1 (fr
Inventor
Takao Muramatsu
Hitoshi Takeda
Kentarou Murakami
Masayasu Ito
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Koito Manufacturing Co Ltd
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Koito Manufacturing Co Ltd
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Priority to EP14002488.6A priority Critical patent/EP2800457B1/fr
Publication of EP2675247A1 publication Critical patent/EP2675247A1/fr
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Publication of EP2675247B1 publication Critical patent/EP2675247B1/fr
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40—Details of LED load circuits
    • H05B45/44—Details of LED load circuits with an active control inside an LED matrix
    • H05B45/48—Details of LED load circuits with an active control inside an LED matrix having LEDs organised in strings and incorporating parallel shunting devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/50—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
    • H05B45/54—Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits in a series array of LEDs

Definitions

  • the present invention relates to a light source control device that controls a light source.
  • a semiconductor light source such as LEDs (light emitting diodes) which are longer in lifetime and lower in power consumption is used instead of a halogen lamp having a filament in a related art.
  • the degree of light emission that is, the brightness of the LED depends on the magnitude of a current that is made to flow in the LED. For that reason, when the LED is used as a light source, there is a need to provide a lighting circuit for adjusting the current flowing in the LED.
  • Patent Literature 1 a technique in which in order to conduct fine light distribution control while making the light distribution of the headlight variable, an array of the LEDs is applied as the light source, and the respective LEDs are switched on or off, individually.
  • a bypass switch is disposed in parallel to each of the LEDs, and the bypass switch is turned on/off to realize the individual switch-on/off of the LED.
  • Exemplary embodiments of the invention provide a light source control device that can appropriately cope with the poor continuity which is generated in the line around the light sources or the bypass switches.
  • a light source control device (100,700) according to an exemplary embodiment, comprises:
  • both of the first bypass switch and the second bypass switch can be forcedly turned on.
  • a light source control device (100,700) according to an exemplary embodiment, comprises:
  • the light source control device that can appropriately cope with the poor continuity which is generated in the line around the light sources or the bypass switches.
  • a state in which a member A is connected to a member B includes a case in which the member A and the member B are physically directly connected to each other, as well as a case in which the member A and the member B are connected indirectly to each other through another member that does not affect an electric connection state therebetween.
  • a state in which a member C is disposed between the member A and the member B includes a case in which the member A and the member C, or the member B and the member C are connected directly to each other, as well as a case in which those members are connected indirectly to each other through another member that does not affect an electric connection state therebetween.
  • a semiconductor light source control device generates a drive current that flows in a plurality of semiconductor light sources connected in series, that is, LEDs.
  • a bypass switch is disposed in parallel to each of the LEDs. When the bypass switch turns on (off), a corresponding LED turns on (off).
  • a bypass connection line is disposed between a connection node between two adjacent LEDs, and a connection node between two corresponding bypass switches.
  • the semiconductor light source control device is configured such that when a disconnection or contact failure is generated in the bypass connection line, the two bypass switches connected by the bypass connection line are forcedly turned on. With this configuration, when the poor continuity is thus generated, the associated LEDs can be turned off.
  • FIG. 1 is a circuit diagram illustrating a configuration of a semiconductor light source control device 100 and members connected to the semiconductor light source control device 100 according to the embodiment.
  • the semiconductor light source control device 100 supplies a drive current Iout to a plurality (N) of in-vehicle LEDs 2-1 to 2-N which is connected in series with each other, and turns on those LEDs 2-1 to 2-N.
  • N is a natural number of 2 or larger.
  • the semiconductor light source control device 100 and the N LENDS 2-1 to 2-N are mounted in a vehicle lighting device such as headlights.
  • the semiconductor light source control device 100 is connected to an in-vehicle battery 6 and a power switch 8.
  • the in-vehicle battery 6 generates a battery voltage (supply voltage) Vbat of 12V (or 24V) DC.
  • the power switch 8 is a relay switch configured to control the on/off operation of the overall N LEDs 2-1 to 2-N, and connected in series with the in-vehicle battery 6.
  • the battery voltage Vbat is applied to the semiconductor light source control device 100 from a positive terminal of the in-vehicle battery 6 as an input voltage.
  • a negative terminal of the in-vehicle battery 6 is connected to a fixed voltage terminal, that is, grounded.
  • the LEDs 2-1 to 2-N are connected in parallel to electrostatic protection zener diodes 252-1 to 252-N in an opposite direction, respectively, That is, a cathode of the first electrostatic protection zener diode 252-1 is connected to an anode of the first LEDs 2-1, and an anode of the first electrostatic protection zener diode 252-1 is connected to a cathode of the first LEDs 2-1.
  • the same is applied to the second electrostatic protection zener diodes 252-2 to the N th electrostatic protection zener diodes 252-N.
  • the electrostatic protection zener diodes 252-1 to 252-N protect the corresponding LEDs 2-1 to 2-N from being broken down by static electricity.
  • the semiconductor light source control device 100 includes a switching regulator, that is, a flyback regulator 102, a downconverter 104, a control circuit 106, a current detection resistor 108, N bypass circuits 270-1 to 270-N, and a bypass driver circuit 112,
  • the control circuit 106 controls the flyback regulator 102 and the downconverter 104, and includes a flyback driver circuit 134, a downconverter driver circuit 136, and a hysteresis width setting circuit 138.
  • the bypass driver circuit 112 is realized by a microcomputer.
  • the flyback regulator 102 is formed of a voltage regulator, and converts the input battery voltage Vbat into a target voltage Vt, and outputs the target voltage Vt. Since an output terminal on a high potential side of the flyback regulator 102 is on a ground side, the target voltage Vt is a voltage to be applied to the output terminal on a low potential side of the flyback regulator 102, and has a negative polarity.
  • the flyback regulator 102 includes an input capacitor 114, a first switching element 116, an input transformer 124, an output diode 126, an output capacitor 128, a voltage detection diode 130, and a voltage detection capacitor 132.
  • the input capacitor 114 is disposed in parallel to the in-vehicle battery 6, and smooths the battery voltage Vbat. More specifically, the input capacitor 114 is disposed in the vicinity of the input transformer 124, and performs a function of smoothing a voltage in the switching operation of the flyback regulator 102.
  • a primary winding 118 of the input transformer 124 and the first switching element 116 are connected in series, and the series circuit is connected in parallel to the input capacitor 114 with respect to the in-vehicle battery 6.
  • the first switching element 116 is formed of an N-channel MOSFET (metal oxide semiconductor field effect transistor).
  • One end of a secondary winding 120 of the input transformer 124 is connected to one end of the output capacitor 128, and the other end of the secondary winding 120 is connected to an anode of the output diode 126.
  • the other end of the output capacitor 128 is connected to a cathode of the output diode 126.
  • One end of the output capacitor 128 is connected to the output terminal on a low potential side of the flyback regulator 102, and is applied with the target voltage Vt.
  • the other end of the output capacitor 128 is connected to the output terminal on the high potential side of the flyback regulator 102,
  • a control terminal (gate) of the first switching element 116 is supplied with an upstream control signal S 1 having a rectangular waveform which is generated by the flyback driver circuit 134.
  • the first switching element 116 turns on when the upstream control signal S1 is asserted, that is, high level, and turns off when the upstream control signal S1 is negated, that is, low level.
  • a voltage detection winding 122 of the input transformer 124, the voltage detection diode 130, and the voltage detection capacitor 132 configure a positive voltage detector circuit for detecting a magnitude of the target voltage Vt as a positive voltage.
  • One end of the voltage detection winding 122 is grounded, and the other end thereof is connected to an anode of the voltage detection diode 130.
  • a cathode of the voltage detection diode 130 is connected to one end of the voltage detection capacitor 132.
  • the other end of the voltage detection capacitor 132 is grounded.
  • One end of the voltage detection capacitor 132 is applied with a positive voltage corresponding to an absolute value of the target voltage Vt. This voltage is applied to the flyback driver circuit 134 as a detected voltage Vd.
  • the flyback driver circuit 134 conducts a voltage feedback control for keeping a substantially constant target voltage Vt on the basis of the detected voltage Vd.
  • the flyback driver circuit 134 adjusts a frequency or a duty ratio of the upstream control signal S1 so that the target voltage Vt comes close to a set voltage of, for example, about -100V.
  • the downconverter 104 is disposed downstream of the flyback regulator 102, and includes a second switching element 140, a flywheel diode 142, and an inductor 144, but does not include an output voltage smoothing capacitor.
  • the second switching element 140 is formed of, for example, an N-channel MOSFET.
  • a control terminal of the second switching element 140 is supplied with a downstream control signal S2 of a rectangular waveform which is generated by the downconverter driver circuit 136.
  • the second switching element 140 turns on when the downstream control signal S2 is high level, and turns off when the downstream control signal S2 is low level.
  • a drain of the second switching element 140 is connected to the output terminal on a high potential side of the output capacitor 128, that is, the high potential side of the flyback regulator 102.
  • a source of the second switching element 140 is connected to a cathode of the flywheel diode 142.
  • An anode of the flywheel diode 142 is connected to one end of the inductor 144.
  • a connection node between the anode of the flywheel diode 142 and one end of the inductor 144 is connected to the output terminal on the low potential side of the output capacitor 128, that is, on the low potential side of the flyback regulator 102.
  • the other end of the inductor 144 is connected to the cathode sides of the N LEDs 2-1 to 2-N.
  • the current detection resistor 108 is disposed on a route of the drive current lout. One end of the current detection resistor 108 is connected to a connection node between the source of the second switching element 140 and the cathode of the flywheel diode 142. The other end of the current detection resistor 108 is grounded, and also connected to the anode side of the N LEDs 2-1 to 2-N. A voltage drop Vm proportional to the drive current lout is generated in the current detection resistor 108.
  • the cathode side of the N LEDs 2-1 to 2-N is applied with a drive voltage Vout of a negative polarity.
  • the downconverter driver circuit 136 conducts a current feedback control for allowing the drive current lout to fall within a given current range on the basis of the voltage drop Vm.
  • the downconverter driver circuit 136 turns off the second switching element 140 if the magnitude of the drive current lout exceeds a given current upper limit value Ith1.
  • the downconverter driver circuit 136 turns on the second switching element 140 if the magnitude of the drive current Iout falls below a current lower limit value Ith2 smaller than the current upper limit value Ith1.
  • the downconverter driver circuit 136 sets the downstream control signal S2 to the low level if the magnitude of the drive current lout exceeds the current upper limit value Ith1.
  • the downconverter driver circuit 136 sets the downstream control signal S2 to the high level if the magnitude of the drive current lout falls below the current lower limit value Ith2.
  • the hysteresis width setting circuit 138 sets a hysteresis width ⁇ I which is a difference between the current upper limit value Ith1 and the current lower limit value Ith2, on the basis of the drive voltage Vout.
  • the hysteresis width setting circuit 138 increases the hysteresis width ⁇ I more as an absolute value of the drive voltage Vout becomes larger if the absolute value of the drive voltage Vout falls below a voltage threshold value Vth smaller than the absolute value of the target voltage Vt.
  • the hysteresis width setting circuit 138 decreases the hysteresis width ⁇ I more as the absolute value of the drive voltage Vout becomes larger if the absolute value of the drive voltage Vout exceeds the voltage threshold value Vth.
  • FIG. 2 is a circuit diagram illustrating a configuration of the hysteresis width setting circuit 138.
  • the hysteresis width setting circuit 138 includes a first operational amplifier 146, a first diode 148, a first resistor 150, a second resistor 152, a third resistor 154, a fourth resistor 156, a fifth resistor 158, and a reference voltage source 160.
  • One end of the third resistor 154 is applied with a positive control supply voltage Vcc.
  • the other end of the third resistor 154 is connected with one end of the second resistor 152, one end of the fifth resistor 158, and one end of the fourth resistor 156.
  • the other end of the fourth resistor 156 is grounded.
  • the other end of the fifth resistor 158 is applied with the drive voltage Vout.
  • the other end of the second resistor 152 is connected to an inverting input terminal of the first operational amplifier 146.
  • the inverting input terminal of the first operational amplifier 146 is connected to an anode of the first diode 148 through the first resistor 150.
  • a cathode of the first diode 148 is connected with an output terminal of the first operational amplifier 146.
  • a non-inverting input terminal of the first operational amplifier 146 is applied with a reference voltage Vref which is generated by the reference voltage source 160.
  • a voltage applied to the anode of the first diode 148 is called "offset voltage Voffset".
  • the offset voltage Voffset corresponds to the hysteresis width ⁇ I, and the hysteresis width ⁇ I becomes larger as the offset voltage Voffset is higher.
  • values of the first resistor 150 and the second resistor 152 which determine a gain are set to be sufficiently larger than values of the third resistor 154, the fourth resistor 156, and the fifth resistor 158 which are differentials from the reference voltage Vref so that a feedback current does not affect the differentials from the reference voltage Vref.
  • FIG. 3 is a graph illustrating a relationship between the absolute value of the drive voltage Vout and the offset voltage Voffset.
  • the reference voltage Vref is set to the voltage between the common connection node when the absolute value of the drive voltage Vout is equal to the voltage threshold value Vth.
  • the hysteresis width setting circuit 138 transmits the offset voltage Voffset that is changed into an inverted V-shape responsive to the absolute value of the drive voltage Vout to the downconverter driver circuit 136 to control the hysteresis width ⁇ I, and allows a switching frequency of the downconverter 104 to fall within a given range.
  • FIG. 4 is a circuit diagram illustrating a configuration of the downconverter driver circuit 136.
  • the downconverter driver circuit 136 includes a second operational amplifier 162, a comparator 164, a gate driver 166, a first current mirror circuit 170, a seventh resistor 172, an eighth resistor 174, a tenth resistor 178, a twelfth resistor 182, a thirteenth resistor 184, a first npn bipolar transistor 190, a third switching element 202, a fourth switching element 204, and a second current mirror circuit 206.
  • a non-inverting input terminal of the second operational amplifier 162 is applied with the offset voltage Voffset.
  • An output terminal of the second operational amplifier 162 is connected to a base of the first npn bipolar transistor 190, and an inverting input terminal of the second operational amplifier 162 is connected with an emitter of the first npn bipolar transistor 190.
  • One end of the eighth resistor 174 is connected to the emitter of the first npn bipolar transistor 190, and the other end of the eighth resistor 174 is grounded.
  • a collector of the first npn bipolar transistor 190 is connected to the first current mirror circuit 170 through the seventh resistor 172.
  • the first current mirror circuit 170 includes a sixth resistor 168, a ninth resistor 176, an eleventh resistor 180, a first pnp bipolar transistor 192, a second pnp bipolar transistor 194, and a third pnp bipolar transistor 196. Those circuit elements are connected to each other to configure a known current mirror circuit.
  • the first current mirror circuit 170 receives a current that flows in the seventh resistor 172, and outputs a current that flows in the tenth resistor 178, and a current that flows in the third switching element 202, and makes a magnitude of the input current substantially equal to a magnitude of the output current.
  • the second current mirror circuit 206 includes a fourteenth resistor 186, a fifteenth resistor 188, a second npn bipolar transistor 198, and a third npn bipolar transistor 200. Those circuit elements are connected to each other to configure a known current mirror circuit.
  • the second current mirror circuit 206 receives a current that flows in the tenth resistor 178, and outputs a current that flows in between the fourth switching element 204, and makes a magnitude of the input current substantially equal to a magnitude of the output current.
  • the third switching element 202 is formed of, for example, a p-channel MOSFET.
  • the fourth switching element 204 is formed of, for example, an n-channel MOSFET.
  • a source of the third switching element 202 is connected to the first current mirror circuit 170.
  • a gate of the third switching element 202 is connected to an inverting output terminal of the comparator 164.
  • a drain of the third switching element 202 is connected to a drain of the fourth switching element 204.
  • a gate of the fourth switching element 204 is connected to the inverting output terminal of the comparator 164.
  • a source of the fourth switching element 204 is connected to the second current mirror circuit 206.
  • the twelfth resistor 182 and the thirteenth resistor 184 are connected in series between the control supply voltage Vcc and the ground potential in the stated order.
  • a connection node between the twelfth resistor 182 and the thirteenth resistor 184 is connected to a connection node between a drain of the third switching element 202 and a drain of the fourth switching element 204.
  • the connection node between the drain of the third switching element 202 and the drain of the fourth switching element 204 is connected to the non-inverting input terminal of the comparator 164.
  • the inverting input terminal of the comparator 164 is applied with a voltage drop Vm.
  • a non-inverting output terminal of the comparator 164 is connected to the gate driver 166.
  • the gate driver 166 matches a phase of the downstream control signal S2 with a phase of a signal that appears in the non-inverting output terminal of the comparator 164. That is, the gate driver 166 sets the downstream control signal S2 to high level (low level) when the signal appearing in the non-inverting output terminal of the comparator 164 become high level (low level).
  • the second operational amplifier 162 and the first npn bipolar transistor 190 which receive the offset voltage Voffset output a current of Voffset/(resistance value of the eighth resistor 174). This current is sunk or sourced into a voltage division node between the twelfth resistor 182 and the thirteenth resistor 184 by a phase of an output of the comparator 164 that receives the voltage drop Vm.
  • the third switching element 202 and the fourth switching element 204 configuring a bridge at timing when a gate of the second switching element 140 is high level (second switching element 140 is on), the third switching element 202 turns on, and a voltage at the voltage division node between the twelfth resistor 182 and the thirteenth resistor 184 is raised to set the current upper limit value Ith1.
  • the fourth switching element 204 turns on at substantially the same time when the gate of the second switching element 140 becomes low level (the second switching element 140 is off).
  • the voltage at the voltage division node between the twelfth resistor 182 and the thirteenth resistor 184 is lowered to set the current lower limit value Ith2.
  • the hysteresis width ⁇ I is smaller as the absolute value of the drive voltage Vout is farther from the voltage threshold value Vth. As will be described later, this acts so that the switching frequency of the downconverter 104 falls within a given range.
  • the semiconductor light source control device 100 is configured to control the N LEDs 2-1 to 2-N to turn on/off, individually.
  • the bypass driver circuit 112 generates N lighting on/off control signals Sc1 to ScN for controlling the on/off operation of the respective LEDs 2-1 to 2-N.
  • the bypass driver circuit 112 controls the levels of the respective N lighting on/off control signals Sc1 to ScN so as to obtain a desired brightness or light distribution pattern, individually. Specifically, the bypass driver circuit 112 sets the first lighting on/off control signal Sc1 to low level when the first LED 2-1 is turned on, and sets the first lighting on/off control signal Sc1 to high level when the first LEDs 2-1 is turned off.
  • the bypass driver circuit 112 outputs the respective lighting on/off control signals Sc1 to ScN to the corresponding bypass circuits 270-1 to 270-N.
  • the first bypass circuit 270-1 to the N th bypass circuit 270-N are connected in parallel to the first LED 2-1 to the N th LED 2-N, respectively.
  • the first bypass circuit 270-1 to the N th bypass circuit 270-N are connected in series between a high potential side output terminal and a low potential side output terminal of the downconverter 104 in the stated order.
  • the first bypass circuit 270-1 performs electric continuity between both ends of the first LED 2-1, that is, connects both ends of the first LED 2-1 to each other by an impedance lower than that of the first LED 2-1 when the first lighting on/off control signal Scl is high level. With this configuration, the first LED 2-1 is turned off. Hereinafter, a state of the bypass circuits that turn off the LEDs is called “bypass-on state”.
  • the first bypass circuit 270-1 connects both ends of the first LED 2-1 to each other by an impedance higher than that of the first LED 2-1 when the first lighting on/off control signal Sc1 is low level. With this configuration, the first LED 2-1 turns on.
  • a state of the bypass circuits that turn on the LEDs is called "bypass-off state”.
  • the first bypass circuit 270-1 generates a first abnormality detection signal Sdet1 for detecting the abnormality of the first LED 2-1 and lines around the first LED 2-1, and supplies the first abnormality detection signal Sdet1 to the bypass driver circuit 112. If the first abnormality detection signal Sdet1 is high level, a voltage to be applied to the first bypass circuit 270-1 when the first bypass circuit 270-1 is in the bypass-off state is lower than a short-circuit detection voltage, or higher than a disconnection detection voltage higher than the short-circuit detection voltage.
  • the short-circuit detection voltage is set to be lower than the forward drop voltage Vf of one LED.
  • the disconnection detection voltage is set to be higher than the forward drop voltage Vf of the LED, and lower than a sum 2Vf of the forward drop voltages of two LEDs.
  • the second bypass circuit 270-2 to the N th bypass circuit 270-N control the on/off state of the second LEDs 2-2 to the N th LED 2-N on the basis of the second lighting on/off control signals Sc2 to the N th lighting on/off control signal ScN, respectively. Also, the second bypass circuit 270-2 to the Nth bypass circuit 270-N generate second abnormality detection signal Sdet2 to N th abnormality detection signal SdetN, respectively, and supply those abnormality detection signals to the bypass driver circuit 1 12.
  • the bypass driver circuit 112 changes the first lighting on/off control signal Sc1 at a dimming frequency f1 of several hundred Hz to several kHz cyclically, that is, in a rectangular waveform.
  • the first LED 2-1 blinks at the dimming frequency f1 by the pulse modulation of the first lighting on/off control signal Sc1, and the brightness visible by human's eyes is dimmed.
  • a duty ratio of the first lighting on/off control signal Sc1 is set to obtain a desired degree of light mission. In this case, since a variation in a magnitude of the driver circuit that flows in the first LED 2-1 when the turning on the first LED 2-1 is suppressed, color shift is suppressed.
  • the bypass driver circuit 112 has a PWM (pulse width modulation) dimming function for the respective second LED 2-2 to N th LED 2-N.
  • the bypass driver circuit 112 determines whether an abnormality is generated in the first LED 2-1 and the lines around the first LED 2-1, or not, on the basis of the first abnormality detection signal Sdet1.
  • the bypass driver circuit 112 determines that the abnormality is generated when the first abnormality detection signal Sdet1 becomes high level, and forcedly sets the first lighting on/off control signal Sc1 to the high level, For example, the bypass driver circuit 112 keeps the first lighting on/off control signal Sc1 in the high level, even in a period when the first lighting on/off control signal Sc1 is to be set to the low level according to the PWM dimming function.
  • the bypass driver circuit 112 sets the first lighting on/off control signal Sc1 to the high level, even in a period when the first lighting on/off control signal Sc1 is to be set to the low level if it is not determined that the abnormality is generated.
  • the bypass driver circuit 112 also has the same abnormality detection function for the respective second LED 2-2 to N th LED 2-N.
  • a first bypass connection line 280-1 connects a first bypass side connection node NB1 between the first bypass circuit 270-1 and the second bypass circuit 270-2, and a first load side connection node NL1 between the first LED 2-1 and the second LED 2-2.
  • the polarity of the drive current lout flowing in the first bypass connection line 280-1 trends from a load side toward a bypass side.
  • the polarity of the drive current lout flowing in the first bypass connection line 280-1 trends from the bypass side toward the load side.
  • the polarity of the drive current lout flowing in the first bypass connection line 280-1 in the former case is opposite to the polarity of the drive current lout flowing in the first bypass connection line 280-1 in the latter case.
  • the same is applied to the second bypass connection line 280-2 to (N-1) th bypass connection line 280-(N-1).
  • bypass driver circuit 12 If the poor continuity is generated in the bypass connection line, the bypass driver circuit 12, and the first bypass circuit 270-1 to the N th bypass circuit 270-N are configured so that both of the two bypass circuits connected to the bypass connection lines are forcedly brought into the bypass-on state.
  • FIG. 5 is a circuit diagram illustrating configurations of the second bypass circuit 270-2 and the third bypass circuit 270-3.
  • the second bypass circuit 270-2 includes a second switch level shift circuit 254-2, a second bypass/limiter circuit 250-2, a second disconnection detector circuit 272-2, a second short-circuiting detector circuit 274-2, a second detection signal level shift circuit 276-2, and a second integrating circuit 278-2.
  • the second switch level shift circuit 254-2 receives the second lighting on/off control signal Sc2 from the bypass driver circuit 112, and converts the second lighting on/off control signal Sc2 into a second bypass switch drive signal Sd2 with a voltage across the cathode of the second LED 2-2 as a standard, that is, a low level.
  • a phase of the second bypass switch drive signal Sd2 matches a phase of the second lighting on/off control signal Sc2, and the low level of the second bypass switch drive signal Sd2 becomes the voltage of the cathode of the second LED 2-2.
  • the second switch level shift circuit 254-2 shifts the level of the second lighting on/off control signal Sc2, and supplies the signal to the corresponding second bypass/limiter circuit 250-2.
  • the second bypass/limiter circuit 250-2 includes a second bypass switch 110-2 which is connected in parallel to the second LED 2-2. If the second bypass switch drive signal Sd2 is high level (low level), the second bypass/limiter circuit 250-2 turns on (off) the second bypass switch 110-2 to turn on (off) the second LED 2-2. Further, when the second bypass switch drive signal Sd2 is low level, the second bypass/limiter circuit 250-2 is configured to limit an upper limit of a voltage between both ends of the second bypass switch 110-2 with the use of the second bypass switch 110-2.
  • the second bypass/limiter circuit 250-2 includes a limiter zener diode 256, a backflow prevention diode 258, a sixteenth resistor 260, and the second bypass switch 110-2.
  • the second bypass switch 110-2 is formed of, for example, an N-channel MOSFET.
  • a cathode of the limiter zener diode 256 is connected to a drain of the second bypass switch 110-2.
  • a connection node therebetween is connected to the first bypass connection line 280-1.
  • An anode of the limiter zener diode 256 is connected to an anode of the backflow prevention diode 258.
  • the second bypass switch drive signal Sd2 is input to a gate of the second bypass switch 110-2 through the sixteenth resistor 260.
  • a source of the second bypass switch 110-2 is connected to the second bypass connection line 280-2.
  • a series circuit of the limiter zener diode 256 and the backflow prevention diode 258 is connected to the gate side of the second bypass switch 110-2 with respect to the second bypass switch drive signal Sd2 that turns on/off the second bypass switch 110-2. That is, a cathode of the backflow prevention diode 258 is connected between the sixteenth resistor 260 and the gate of the second bypass switch I 10-2.
  • the zener voltage of the limiter zener diode 256 is set so that the disconnection detection voltage becomes higher than a maximum value of the forward drop voltage Vf of the second LED 2-2, becomes lower than the zener voltage defined by the second electrostatic protection zener diodes 252-2, and becomes lower than a sum of the forward drop voltage Vf of the second LED 2-2, and the forward drop voltage Vf of the third LED 2-3.
  • the zener voltage of the limiter zener diode 256 is set to range from 3V to 9V.
  • the backflow prevention diode 258 is configured to prevent the second bypass switch drive signal Sd2 from inhibiting the on/off operation of the second bypass switch 110-2. For example, when the second LED 2-2 that is connected in parallel to the backflow prevention diode 258 is turned off, or the second bypass switch 110-2 is forcedly turned on as measures against the disconnection or the contact failure which will be described later, if there is no backflow prevention diode 258, the gate voltage of the second bypass switch 110-2 is reduced through the second bypass switch 110-2 which is in the on-state from a forward direction of the limiter zener diode 256. The backflow prevention diode 258 prevents this status from occurring.
  • the second disconnection detector circuit 272-2 determines whether the poor continuity is generated on a route of the drive current lout that passes through the second LED 2-2, or not, when the second bypass switch 110-2 is off (that is, non-conduction state).
  • the second short-circuiting detector circuit 274-2 determines whether a short-circuiting abnormality is generated in the second LED 2-2 or between the lines when the second bypass switch 110-2 is off, or not. If the abnormality is detected in the second disconnection detector circuit 272-2 or the second short-circuiting detector circuit 274-2, an integration capacitor 282 of the second integrating circuit 278-2 is charged by a first time constant through the second detection signal level shift circuit 276-2.
  • This charging operation is continued in a period when the second bypass switch drive signal Sd2 is low level, and the abnormality is detected in the second disconnection detector circuit 272-2 or the second short-circuiting detector circuit 274-2.
  • the integration capacitor 282 is discharged by a second time constant longer than the first time constant.
  • the second detection signal level shift circuit 276-2 includes a seventeenth resistor 284, an eighteenth resistor 286. and a fourth pnp bipolar transistor 288.
  • One end of the seventeenth resistor 284 is connected to an emitter of the fourth pnp bipolar transistor 288.
  • a connection node therebetween is applied with the control supply voltage Vcc.
  • the other end of the seventeenth resistor 284 is connected to one end of the eighteenth resistor 286.
  • a connection node therebetween is connected to a base of the fourth pnp bipolar transistor 288.
  • the second disconnection detector circuit 272-2 includes a 23 rd resistor 210, and a sixth npn bipolar transistor 212.
  • a collector of the sixth npn bipolar transistor 212 is connected to the other end of the eighteenth resistor 286.
  • a base of the sixth npn bipolar transistor 212 is connected to the connection node between the anode of the limiter zener diode 256 and the anode of the backflow prevention diode 258 through the 23rd resistor 210.
  • An emitter of the sixth npn bipolar transistor 212 is connected to the second bypass connection line 280-2.
  • the second short-circuiting detector circuit 274-2 includes a nineteenth resistor 290, a twenty resistor 292, a 21 st resistor 294, a 22 nd resistor 296, a fourth npn bipolar transistor 298, and a fifth npn bipolar transistor 208.
  • the twenty resistor 292 and the 22nd resistor 296 are connected in series between the first bypass connection line 280-1 and the second bypass connection line 280-2 in the stated order.
  • a connection node between the twenty resistor 292 and the 22 nd resistor 296 is connected to one end of the 21st resistor 294 and a base of the fourth npn bipolar transistor 298.
  • the other end of the 21 st resistor 294 is connected to the cathode of the backflow prevention diode 258.
  • An emitter of the fourth npn bipolar transistor 298 is connected to the second bypass connection line 280-2.
  • a collector of the fourth npn bipolar transistor 298 is connected to one end of the nineteenth resistor 290.
  • the other end of the nineteenth resistor 290 is applied with the control supply voltage Vcc.
  • a connection node between the collector of the fourth npn bipolar transistor 298 and the nineteenth resistor 290 is connected to the base of the fifth npn bipolar transistor 208.
  • the emitter of the fifth npn bipolar transistor 208 is connected to the second bypass connection line 280-2, and a collector of the fifth npn bipolar transistor 208 is connected to the other end of the eighteenth resistor 286.
  • the second integrating circuit 278-2 includes the integration capacitor 282, a 24 th resistor 214, and a 25 th resistor 216.
  • One end of the 24 th resistor 214 is grounded to a ground potential which is substantially equal to a ground potential of a microcomputer, and the other end of the 24 th resistor 214 is connected to one end of the 25 th resistor 216.
  • a connection node between the 24 th resistor 214 and the 25 th resistor 216 is connected to a collector of the fourth pnp bipolar transistor 288.
  • the other end of the 25 th resistor 216 is connected to one end of the integration capacitor 282.
  • the other end of the integration capacitor 282 is grounded to a ground potential which is substantially equal to the ground potential of the microcomputer.
  • a voltage across one end of the integration capacitor 282 is applied to the bypass driver circuit 112 as the second abnormality detection signal Sdet2.
  • the voltage between both ends of the second bypass switch 110-2 is raised over the forward drop voltage Vf during the off-period of the second bypass switch 110-2. If the voltage between both ends thereof exceeds the disconnection detection voltage, a current flows into the limiter zener diode 256. Then, the sixth npn bipolar transistor 212 of the second disconnection detector circuit 272-2 turns on.
  • the voltage between both ends of the second bypass switch 110-2 becomes lower than the forward drop voltage Vf during the off-period of the second bypass switch 110-2. If the voltage between both ends thereof becomes lower than a short-circuit detection voltage, the fourth npn bipolar transistor 298 of the second short-circuiting detector circuit 274-2 turns off, and the fifth npn bipolar transistor 208 turns on.
  • the respective resistance values of the twenty resistor 292, the 21 resistor 294, and the 22 nd resistor 296 are set to satisfy the following three conditions.
  • the fourth pnp bipolar transistor 288 of the second detection signal level shift circuit 276-2 turns on.
  • the control supply voltage Vcc is a positive voltage with the ground potential of the microcomputer as a standard. If an abnormality is detected in the second disconnection detector circuit 272-2 or the second short-circuiting detector circuit 274-2, the control supply voltage Vcc is applied to the second integrating circuit 278-2.
  • the integration capacitor 282 is charged through the 25th resistor 216, and discharged through the 24 th resistor 214 and the 25 th resistor 216.
  • a resistance value of the 24 th resistor 214 is set to be larger than a resistance value of the 25 th resistor 216, the abnormality can be detected even in a dimming state where a period (that is, off-period of the second bypass switch 110-2) for abnormality detection is short such as a mean current 10% light-up (on state of the second bypass switch 110-2 is 90%, off state thereof is 10%).
  • the third bypass circuit 270-3 is configured in the same manner as that of the second bypass circuit 270-2.
  • the third bypass circuit 270-3 includes a third switch level shift circuit 254-3 corresponding to the second switch level shift circuit 254-2, a third bypass/limiter circuit 250-3 corresponding to the second bypass/limiter circuit 250-2, a third disconnection detector circuit 272-3 corresponding to the second disconnection detector circuit 272-2, a third short-circuiting detector circuit 274-3 corresponding to the second short-circuiting detector circuit 274-2, a third detection signal level shift circuit 276-3 corresponding to the second detection signal level shift circuit 276-2, and a third integrating circuit 278-3 corresponding to the second integrating circuit 278-2.
  • the first bypass circuit 270-1, the fourth bypass circuit 270-4 to the N th bypass circuit 270-N are configured in the same manner as that of the second bypass circuit 270-2.
  • FIGS. 6A to 6C are graphs illustrating a time variation of the drive current lout. Let us consider a status in which only one LED is first turned on, about half of the LEDS are then turned on, and all of the LEDs are thereafter turned on. In this case, the PWM dimming is not considered.
  • FIG. 6A illustrates a time variation of the drive current lout when only one LED is turned on, and the remaining (N-1) LEDs are turned off by turning on the corresponding bypass switches.
  • FIG. 6B illustrates a time variation of the drive current lout when about half of the LEDs, that is N/2 LEDs are turned on, and the remaining LED are turned off.
  • FIG. 6C illustrates a time variation of the drive current lout when all of the LEDS are turned on.
  • FIGS. 6A to 6C illustrate a case in which the hysteresis width ⁇ I is adjusted so that the switching frequency, that is, a switching cycle Ts of the second switching element 140 is kept substantially constant, without depending on the number of lighting of the LEDs and the number of extinction of the LEDs.
  • the hysteresis width ⁇ I is so controlled as to suppress a change in the switching cycle Ts caused by a change in the number of lighting of the LEDs and the number of extinction of the LEDs.
  • the drive current lout is relatively quickly raised in an on-time Ton of the second switching element 140, and the drive current lout is relatively slowly lowered in an off-time Toff of the second switching element 140.
  • the hysteresis width in this case is expressed as " ⁇ I1".
  • An absolute value of the drive voltage Vout is relatively low, and the offset voltage Voffset generated by the hysteresis width setting circuit 138 is also relatively low.
  • the drive voltage Vout is about half of the setting voltage of the flyback regulator 102, and the on-time Ton and the off-time Toff of the second switching element 140 balance with each other.
  • a speed of the overall change in the drive current lout is larger than that when the number of lighting of the LEDs is small.
  • the hysteresis width setting circuit 138 allows the higher offset voltage Voffset to be generated as illustrated in FIG. 3 .
  • the downconverter driver circuit 136 receives the high offset voltage Voffset, and makes a hysteresis width ⁇ I2 larger than a hysteresis width ⁇ I1 when the number of lighting of the LEDS is 1. As a result, an increment in the speed of the overall change of the drive current Iout is offset, and the switching cycle Ts is kept substantially constant.
  • the drive current lout when the number of extinction of the LEDs is small or null, the drive current lout is relatively slowly raised in the on-time Ton of the second switching element 140, and the drive current Iout is relatively quickly lowered in the off-time Toff of the second switching element 140.
  • the speed of the overall change of the drive current lout becomes smaller than that when the number of lighting of the LEDs and the number of extinction of the LEDS balance with each other.
  • the absolute value of the drive voltage Vout is relatively high, and the offset voltage Voffset generated by the hysteresis width setting circuit 138 is also relatively low.
  • the downconverter driver circuit 136 receives the low offset voltage Voffset, and makes a hysteresis width ⁇ I3 smaller than the hysteresis width ⁇ I2 when the number of lighting of the LEDs and the number of extinction of the LEDS balance with each other. As a result, a decrement in the speed of the overall change of the drive current lout is offset, and the switching cycle Ts is kept substantially constant.
  • FIG. 7 is a timing chart illustrating a change in the second bypass switch drive signal Sd2 and the second abnormality detection signal Sdet2 in a PWM dimming state.
  • the second bypass switch drive signal Sd2 corresponds to the mean current 20% lighting. That is, the off-time Toff of a period during which the second bypass switch drive signal Sd2 is low level is about 1/4 of the on-time Ton of a period during which the second bypass switch drive signal Sd2 is high level.
  • the second abnormality detection signal Sdet2 is kept constant in the vicinity of the ground potential of the microcomputer, that is, 0V, without depending on a change in the second bypass switch drive signal Sd2.
  • the poor continuity or the disconnection is generated at a time t1 during the period when the second bypass switch drive signal Sd2 is high level.
  • the second bypass switch drive signal Sd2 is high level, that is, the second bypass switch 110-2 is on (that is, conduction state)
  • both of the sixth npn bipolar transistor 212 and the fifth npn bipolar transistor 208 are kept off as they are. Therefore, the potential of the second abnormality detection signal Sdet2 is not substantially changed.
  • any one of the sixth npn bipolar transistor 212 and the fifth npn bipolar transistor 208 is turned on due to the generated abnormality, and the integration capacitor 282 starts to be charged.
  • the integration capacitor 282 is fully charged.
  • a voltage of the second abnormality detection signal Sdet2 when the integration capacitor 282 is fully charged is higher than a level threshold value Vg for determining a level of the second abnormality detection signal Sdet2 in the bypass driver circuit 112.
  • both of the sixth npn bipolar transistor 212 and the fifth npn bipolar transistor 208 turn off, and the integration capacitor 282 starts to be discharged.
  • the second abnormality detection signal Sdet2 is higher than the level threshold value Vg, an operating speed of the bypass driver circuit 112 which is the microcomputer is relatively low. Therefore, the level transition of the second bypass switch drive signal Sd2 is continued for a while.
  • the integration capacitor 282 starts to be again charged. Therefore, the integration capacitor 282 is again fully charged.
  • the second time constant for the discharge of the integration capacitor 282 is set to be longer than the first time constant for the charge of the integration capacitor 282. Therefore, even in a period between the time t4 when the second bypass switch drive signal Sd2 is high level, and the time t5, the voltage of the second abnormality detection signal Sdet2 is kept higher than the level threshold value Vg. Thus, after the second bypass switch drive signal Sd2 has repeated the level transition several times, the bypass driver circuit 112 determines that the second abnormality detection signal Sdet2 has transitioned from the low level to the high level. Also, referring to FIG. 7 , a case in which the integration capacitor 282 reaches a fully charged state in one off-period of the second bypass switch 110-2 has been described. However, the present invention is not limited to this configuration, but the integration capacitor 282 may come close to the fully charged state every time the off-period is repeated.
  • the poor continuity is generated in the second bypass connection line 280-2, that is, a case in which the poor continuity is generated at a portion of a mark "X" indicated by reference numeral 218 shown in FIG. 5 .
  • the potential of the connection node between the source of the second bypass switch 110-2 and the drain of the third bypass switch 110-3 floats.
  • both of the second bypass switch 110-2 and the third bypass switch 110-3 are off, the potential of the connection node comes closer to the potential of the source of the second bypass switch 110-2 or the potential of the drain of the third bypass switch 110-3 due to a difference in a characteristic between the second bypass switch 110-2 and the third bypass switch 110-3.
  • a third abnormality detection signal Sdet3 becomes high level, and the bypass driver circuit 112 fixes a third lighting on/off control signals Sc3 to the high level.
  • the third bypass switch 110-3 turns on, and a voltage between both ends of the second bypass switch 110-2 becomes substantially 2Vf. Since the disconnection detection voltage is lower than 2Vf, the second disconnection detector circuit 272-2 detects that the poor continuity is generated. The second abnormality detection signal Sdet2 becomes high level, and the bypass driver circuit 112 fixes the second lighting on/off control signal Sc2 to the high level. As a result of the above, both of the second bypass switch 110-2 and the third bypass switch 110-3 are forcedly turned on to maintain both of the second LED 2-2 and the third LED 2-3 in an extinction state.
  • the second short-circuiting detector circuit 274-2 detects the short-circuit abnormality
  • the third disconnection detector circuit 272-3 detects the disconnection abnormality
  • the third bypass switch 110-3 turns on, and the drive current lout does not flow into the third bypass switch 110-3, but flows in the third LED 2-3. That is, the third LED 2-3 cannot be turned off.
  • the second bypass switch drive signal Sd2 is set to the high level, and the third bypass switch drive signal Sd3 is set to the low level, the second bypass switch 110-2 turns on, and the drive current Iout does not flow in the second bypass switch 110-2, but flows in the second LED 2-2. That is, the second LED 2-2 cannot be turned off.
  • the poor continuity is generated in the second bypass connection line 280-2, it is difficult to control the respective lighting on/off states of the second LED 2-2 and the third LED 2-3, individually.
  • both of the two bypass switches connected to the bypass connection line in which the poor continuity is generated are forcedly turned on. As a result, both of the two LEDs connected to the bypass connection line are turned off.
  • the semiconductor light source control device 100 is intended for the high beam of the vehicle headlights, and the semiconductor light source control device 100 has a function of turning off the appropriate LED so as not to give a preceding vehicle and an oncoming vehicle glare.
  • the semiconductor light source control device 100 has a PWM dimming function of turning on/off the bypass switch at a relative high speed to adjust the brightness of the corresponding LED.
  • the bypass switch When the bypass switch is on, the voltage between both ends of the bypass switch comes close to 0V. However, this is not abnormal, and therefore should not be determined as the short-circuit abnormality. Under the circumstance, the semiconductor light source control device 100 does not conduct the short-circuit abnormality detection and the disconnection abnormality detection when the bypass switch is on, and detects the short-circuit and the disconnection abnormality when the bypass switch is off.
  • a microcomputer is frequently used as a main device that controls the on/off operation of the LEDs, and the PWM dimming function. Since the microcomputer usually operates at relatively long time intervals such as about several tens msec, the microcomputer is not suited for picking up only the respective abnormalities of a large number of LEDs at a high speed for determination.
  • a length of the off-period of the bypass switch is several hundred micro second order.
  • an abnormality detection signal that becomes high level in an abnormal state, and low level in a normal state is generated without depending on the PWM dimming, due to the action of the integrating circuit.
  • the bypass driver circuit 112 that is the microcomputer determines the normality or abnormality on the basis of the abnormality detection signal.
  • the semiconductor light source control device 100 of this embodiment even if the poor continuity such as the contact failure or the disconnection is generated on the route of the drive current lout, the voltage to be applied to the bypass switch can be prevented from being raised.
  • the contact failure or the disconnection is generated in a line upstream of the connection node between the anode of the first LED 2-1 and the cathode of the first electrostatic protection zener diode 252-1, that is, the line of a mark "X" indicated by reference numeral 262 in the circuit illustrated in FIG. 1 .
  • the bypass driver circuit 112 detects the above transition of the first abnormality detection signal Sdet 1, the bypass driver circuit 112 determines that the abnormality is generated in the first LED 2-1. and the circuit illustrated in FIG, 1 takes a countermeasure to turn on the first bypass switch 110-1 so that the other LEDs can be turned on.
  • the operating speed of the bypass driver circuit 112 which is the microcomputer is relatively low as described above, a time of several tens msec to several hundred msec is required for the above countermeasure.
  • a relatively high voltage such as several kV (absolute value) determined according to an energy accumulated in the inductor 144, and a parasitic capacitor of the first bypass switch is output immediately after the above contact failure or disconnection is generated.
  • This high voltage is applied to the first bypass switch before the first bypass switch turns on. Therefore, there is a need to select an element having a withstand voltage of several kV as the first bypass switch, taking the contact failure or the disconnection into account, although only a voltage of several V is normally applied in the lighting state,
  • the semiconductor light source control device 100 having the limiter function when the disconnection or the contact failure is generated as described above, the drain-source voltage of the first bypass switch 110-1 is raised. However, a rising of that voltage is limited by the action of the limiter zener diode 256 and the first bypass switch 110-1 per se. Therefore, the element having the lower withstand voltage can be selected as the first bypass switch 110-1 even taking the contact failure or the disconnection into account.
  • the contact failure or the disconnection is generated in a line downstream of the connection node between the anode of the first LED 2-1 and the cathode of the first electrostatic protection zener diode 252-1, that is, the line of a mark "X" indicated by reference numeral 264 in the circuit illustrated in FIG. 1 .
  • the semiconductor light source control device is equipped with no limiter function of this embodiment, most of an energy accumulated in the inductor 144 is consumed by the first electrostatic protection zener diode.
  • the upper limit value of the voltage between both ends of the first bypass switch 110-1 is set to be lower than the zener voltage defined by the first electrostatic protection zener diode 252-1, Therefor, the relatively small zener diode can be selected as the first electrostatic protection zener diode 252-1.
  • the upper limit of the voltage to be applied to the corresponding bypass switch or electrostatic protection zener diode is limited. Therefore, the element having the lower withstand voltage can be employed as the corresponding bypass switch, and the relatively small zener diode can be employed as the corresponding electrostatic protection zener diode.
  • the bypass switches for controlling the on/off operation of the LEDs are also used as switches for realizing the limiter function for the voltage between both ends of the LEDs. That is, the bypass switches are shared by the lighting on/off control signal and the limiter function. As a result, an increase in the number of elements can be suppressed while realizing the lighting on/off control function and the limiter function.
  • the semiconductor light source control device 100 since no smoothing capacitor is installed on an output stage of the N LEDs 2-1 to 2-N, the following property of the drive current lout to the second switching element 140 becomes excellent. In particular, when the second switching element 140 turns off, the drive current lout becomes small whereas when the second switching element 140 turns on, the drive current lout becomes large. Then, in order to stabilize the drive current lout in the vicinity of a target value, the hysteresis control of the drive current lout is employed instead of smoothing. As a result, a response to a current feedback can be speeded up.
  • the drive current lout can more rapidly follow a change in the load.
  • undershoot of the drive current lout when the number of lighting of the LEDs is increased, and overshoot of the drive current lout when the number of lighting of the LEDs is decreased can be suppressed.
  • the upstream flyback regulator 102 is set as a negative output
  • the downstream downconverter 104 is also set as the negative output.
  • the N-channel MOSFET having the more excellent characteristic can be employed as the bypass switch.
  • the inductor 144 is not disposed between the cathode of the flywheel diode 142 and the output, but disposed between the anode thereof and the output, the N-channel MOSFET having the more excellent characteristic can be employed as the second switching element 140 of the downconverter 104.
  • the drive voltage Vout can be stably detected.
  • the semiconductor light source control device has the positive output
  • the drive current is frequently detected on the high side taking a case in which the LEDs are grounded into account.
  • the load since the potential of the detected portion is also changed, it is difficult to precisely detect the drive current.
  • the configuration of the detector circuit may be more complicated. Under the circumstance, in the semiconductor light source control device 100 according to this embodiment, the negative output is employed, and output on the positive side, that is, the ground side is equipped with the current detection resistor 108.
  • the load drive voltage Vout
  • the configuration of the detector circuit can be simplified.
  • the switching frequency of the second switching element 140 can be changed.
  • the hysteresis width ⁇ I is adjusted so that a change in the switching frequency is suppressed.
  • a target switching frequency is so set as to avoid a frequency band of a known radio noise, thereby making it possible to suppress an adverse effect of the radio noise on the semiconductor light source control device 100.
  • a variation in the input voltage to the downconverter 104 due to a variation in the battery voltage Vbat is suppressed by the action of the flyback regulator 102. Therefore, a change in the switching frequency due to the fluctuation of the input voltage to the downconverter 104 is suppressed.
  • the hysteresis width ⁇ I can be selected mainly on the basis of the drive voltage Vout. Therefore, a control for adjusting the hysteresis width ⁇ I is simplified. This contributes to a reduction in the scale of the control signal, and an increase in the processing speed thereof.
  • the output capacitor 128 is disposed on an output stage of the flyback regulator 102. If the second switching element 140 is on when the bypass switch turns on, charge stored in the output capacitor 128 is going to flow in the LEDs at once. However, since the inductor 144 is disposed on the route of the drive current lout in the semiconductor light source control device 100, a flow of the charge is smoothed to suppress the overshoot of the drive current lout. Similarly, when the bypass switch turns off, the undershoot of the drive current lout is suppressed.
  • FIG. 8 is a circuit diagram illustrating a configuration of the semiconductor light source lighting circuit 300 according to the comparative example.
  • the semiconductor light source lighting circuit 300 is a forward converter that basically uses no smoothing capacitor.
  • the semiconductor light source lighting circuit 300 includes a control circuit 302, an input capacitor 306, a reset circuit 308, a transformer 310, a fifth switching element 312, a second diode 314, a third diode 316, an inductor 318, and a current detection resistor 320.
  • the control circuit 302 turns off the fifth switching element 312 if a magnitude of the drive current exceeds a given current upper limit value, and turns on the fifth switching element 312 if the magnitude of the driver circuit falls below a current lower limit value.
  • the switching frequency F' is varied between maximum/minimum by about 17 times.
  • this variation range can be suppressed by making the inductance larger, the circuit is upsized. Also, when a function of suppressing a large variation of the switching frequency F' within a given range by calculating the input voltage and the output voltage is realized, the control circuit scale becomes large.
  • a variation in the switching frequency F is suppressed to about 6.5 times. Also, since a main parameter that causes this variation is the drive voltage Vout, and the target voltage Vt is substantially fixed, the scale of the control circuit for adjusting the hysteresis width ⁇ I so as to suppress the variation in the switching frequency F can be relatively reduced.
  • the switching frequency F increases as the drive voltage Vout decreases from -4V to -44V, and the switching frequency F decreases as the drive voltage Vout decreases from -44V to -88V.
  • a boundary between the increase and the decrease of the switching frequency F is -50V which is about half of the output voltage (input voltage of the downconverter 104 at a second stage (post stage)) of the flyback regulator 102 at a first stage (previous stage).
  • control is conducted to increase the hysteresis width ⁇ I more as the drive voltage Vout is lower if Vout > -50V, and to decrease the hysteresis width ⁇ I if Vout ⁇ -50V, thereby making it possible that the switching frequency F easily falls within a given range.
  • the boundary between the increase and the decrease of the switching frequency F is about half of the output voltage of the flyback regulator 102.
  • this boundary is 1/3 or 1/4 of the output voltage.
  • the common element between those embodiments resides that the drive voltage Vout that gives the maximum value of the switching frequency F when the hysteresis width is kept constant can be present between the maximum value and the minimum value of the drive voltage Vout. Therefore, when such a drive voltage Vout is found out by experiments or simulations, and the circuit is configured so that the hysteresis width ⁇ I becomes minimum at the drive voltage Vout, the variation in the switching frequency F can be more preferably suppressed.
  • a setting example of the parameters in the semiconductor light source control device 100 according to this embodiment is represented by the following Table 3.
  • Table 3 Vout (V) Voffset Lower limit voltage Upper limit voltage Ith2 Ith 1 Mean Current Switching frequency -4 0.25 0.2356 0.2456 1.178 1.228 1.203 382.2 kHz -8 0.37 0.2332 0.2480 1.166 1.240 1.203 498.7 kHz -12 0.48 0.2309 0.2503 1.154 1.252 1.203 542.3 kHz -16 0.60 0.2285 0.2527 1.143 1.264 1.203 555.8 kHz -20 0.72 0.2262 0.2551 1.131 1.275 1.203 553.7 kHz -24 0.83 0.2238 0.2574 1.119 1.287 1.203 542.8 kHz -28 0.95 0.2215 0.2598 1.107 1.299 1.203 526.1 kHz -32 1.07 0.2191 0.2621 1.095 1.311 1.203 505.7 kHz -36 1.18 0.2167 0.2645 1.084 1.322 1.203 48
  • the lower limit voltage and the upper limit voltage are voltages of the voltage division node between the twelfth resistor 182 and the thirteenth resistor 184 of the downconverter driver circuit 136 illustrated in FIG. 4 , which correspond to the current lower limit value Ith2 and the current upper limit value Ith1, respectively.
  • the lower limit voltage and the upper limit voltage are calculated from the offset voltage Voffset by setting the respective resistance values of the eighth resistor 174, the twelfth resistor 182, and the thirteenth resistor 184, and the positive control supply voltage Vcc.
  • the mean current is a mean value of the current upper limit value Ith1 and the current lower limit value Ith2.
  • the semiconductor light source lighting circuit 300 according to the comparative example is compared with the semiconductor light source control device 100 according to this embodiment, in the semiconductor light source control device 100, the output capacitor 128 of the flyback regulator 102 and the second switching element 140 of the downconverter 104 are increased, but the reset circuit 308 can be reduced from the semiconductor light source lighting circuit 300. As a result, the circuit scale is substantially equal to each other.
  • the present invention is not limited to this configuration.
  • the flywheel diode may be connected in parallel to the output capacitor 128 of the flyback regulator 102.
  • the second switching element is disposed on the route of the drive current lout which leads to the LED from one end of the output capacitor 128, and returns to the other end of the output capacitor 128 from the LED.
  • the second switching element may be also disposed between the output capacitor 128 and the flywheel diode. The on/off operation of the second switching element may be controlled on the basis of the drive current.
  • the inductor 144 may be disposed on the route of the drive current lout, and disposed between the flywheel diode and the LED.
  • FIGS. 9A to 9C are circuit diagrams illustrating the configurations of semiconductor light source control devices 400, 500, and 600 according to first, second, and third modified examples.
  • FIG. 9A illustrates the configuration of the semiconductor light source control device 400 according to the first modified example.
  • One end of a second switching element 440 is connected to a high potential side output of the flyback regulator 102, and the other end of the second switching element 440 is connected to a cathode of a flywheel diode 442.
  • One end of an inductor 444 is connected to a connection node between the other end of the second switching element 440 and the cathode of the flywheel diode 442.
  • the other end of the inductor 444 is grounded, and forms a high potential side output terminal to the LEDs.
  • An anode of the flywheel diode 442 is connected to a low potential side output of the flyback regulator 102, and forms a low potential side output terminal to the LEDs.
  • FIG. 9B illustrates the configuration of the semiconductor light source control device 500 according to the second modified example.
  • a cathode of a flywheel diode 542 is connected to a high potential side output of the flyback regulator 102, and grounded, and forms a high potential side output to the LEDs.
  • One end of a second switching element 540 is connected to a low potential side output of the flyback regulator 102, and the other end of the second switching element 540 is connected to an anode of the flywheel diode 542.
  • One end of an inductor 544 is connected to a connection node between the other end of the second switching element 540 and the anode of the flywheel diode 542. The other end of the inductor 544 forms a low potential side output terminal to the LEDs.
  • FIG. 9C illustrates the configuration of the semiconductor light source control device 600 according to the third modified example.
  • One end of a second switching element 640 is connected to a low potential side output of the flyback regulator 102, and the other end of the second switching element 640 is connected to an anode of a flywheel diode 642.
  • a connection node between the other end of the second switching element 640 and the anode of the flywheel diode 642 forms a low potential side output to the LEDs.
  • a cathode of the flywheel diode 642 is connected to one end of an inductor 644.
  • a connection node between the cathode of the flywheel diode 642 and one end of the inductor 644 is connected to a high potential side output of the flyback regulator 102.
  • the other end of the inductor 644 is grounded, and forms a high potential side output terminal to the LEDs.
  • the overshoot and the undershoot of the drive current lout can be reduced as in the semiconductor light source control device 100 according to the embodiment.
  • the present invention is not limited to this configuration, but, for example, the anode side of the plurality of LEDs may be connected to a terminal to which a DC voltage such as the battery voltage Vbat is applied.
  • the semiconductor light source control device may include a circuit for measuring the switching frequency of the second switching element 140, and adjust the hysteresis width so that the measured switching frequency falls within a target frequency range.
  • the semiconductor light source control device 100 includes the N bypass switches 110-1 to 110-N.
  • the present invention is not limited to this configuration, but the bypass switches may be disposed separately from the semiconductor light source control device.
  • the present invention is not limited to this configuration, but, for example, a duty ratio of the second switching element 140 may be controlled so that a voltage obtained by appropriately filtering the voltage drop Vm comes closer to a reference voltage corresponding to a target current.
  • the driver circuit is configured to generate the drive current lout by the combination of the flyback regulator 102 and the downconverter 104, and control the magnitude of the drive current lout to come closer to the target value.
  • the present invention is not limited to this configuration, but, for example, a circuit illustrated in FIG. 8 may be employed as the above driver circuit, or a flyback regulator that is subjected to a current feedback control may be employed.
  • FIG. 10 is a circuit diagram illustrating a configuration of a semiconductor light source control device 700 according to a fourth modified example, and members connected to the semiconductor light source control device 700.
  • the semiconductor light source control device 700 includes a flyback regulator 702, a current detection resistor 708, the N bypass circuits 270-1 to 270-N, and the bypass driver circuit 112.
  • both of the second bypass switch and the third bypass switch are forcedly turned on by the actions of the second bypass circuit 270-2, the third bypass circuit 270-3, and the bypass driver circuit 112.
  • a limit value of the maximum voltage output by the flyback regulator 702 is set to a sum of the forward drop voltages Vf or more, taking a case in which all of the N LEDs connected in series are turned on into account. For example, when the maximum value of the forward drop voltage Vf of one LED is set to 6V, and the 30 LEDs are connected in series to each other, the limit value is set to 180V or higher. In this example, because the drive current Iout does not flow in the LED at the moment when the contact failure or the disconnection is generated in the line of the mark "X" indicated by reference numeral 762 in FIG. 10 , the output voltage of the flyback regulator 702 is raised toward 18OV.
  • the control circuit When the control circuit (not shown) detects that the drive current lout is stopped from flowing in the LEDs, the control circuit takes a countermeasure to inspect in which line or LED the disconnection is generated, and turn on the first bypass switch 110-1 in the circuit of FIG. 10 so as to turn on the other LEDs. Normally, a time of several ten msec to several hundred msec is required for this countermeasure.
  • the semiconductor light source control device does not include the limiter zener diode 256 and the backflow prevention diode 258, the output voltage of the flyback regulator 702 reaches 180V before the first bypass switch turns on.
  • the zener voltage of the first electrostatic protection zener diode is 20V
  • the zener voltage of the first electrostatic protection zener diode needs to be set to 90V or higher, which makes it difficult to perform the original function of the electrostatic protection.
  • the semiconductor light source control device 700 is equipped with a first bypass/limiter circuit 250-1 whereby even if the contact failure or the disconnection is generated, an upper limit of the voltage to be applied to the first bypass switch 110-1 is suppressed. Therefore, the element having the high withstand voltage of 100V or higher may not be selected as the first bypass switch 110-1. Also, if the limit voltage by the first bypass/limiter circuit 250-1 is set to the zener voltage or lower of the first electrostatic protection zener diode 252-1, a small zener diode can be selected. In the semiconductor light source control device 100 according to the embodiment, the withstand voltage of kV order is required for the bypass switch when there is no limiter function. Therefore, the withstand voltage suppression effect obtained by provision of the limiter function is more remarkable in the embodiment.
  • the present invention is not limited to this configuration, but the on/off operation of the plurality of LEDs may be controlled by one bypass switch.
  • the zener voltage of the limiter zener diode may fall within a range of from 9V to 21V.
  • the zener voltage of the limiter zener diode is set to 20V, the limit value of the voltage between both ends thereof becomes 23V. Therefore, the element having the withstand voltage of 30V may be selected as the bypass switch.
  • any one of the two bypass switches connected to the bypass connection line is forcedly turned on by the disconnection abnormality, and which of the bypass switches is forcedly turned on by the short-circuit abnormality depends on the characteristic of the bypass switch.
  • the present invention is not limited to this configuration.
  • resistors may be disposed in parallel to the respective odd-numbered bypass circuits (the first bypass circuit 270-1, the third bypass circuit 270-3, ).
  • resistors may be disposed in parallel to the respective even-numbered bypass circuits.
  • the present invention is not limited to this configuration.
  • a unit for detecting the poor continuity of the bypass connection line such as a current measurement unit may be disposed in the bypass connection line, and the unit may be used to determine whether the poor continuity is generated in the bypass connection line, or not. If it is determined that the poor continuity is generated, the bypass driver circuit may forcedly turn on the corresponding two bypass switches.
  • the integration capacitor may be discharged by the first time constant if the poor continuity or the short-circuit abnormality is detected when the bypass switch is off and the integration capacitor may be charged by the second time constant in the other cases.
  • the PWM dimming function is employed.
  • the bypass driver circuit 112 cyclically changes the voltage level of the lighting on/off control signal at the dimming frequency fl. If no abnormality is generated, the corresponding bypass switch is turned off when the lighting on/off control signal is low level, and the corresponding bypass switch is turned on when the lighting on/off control signal is high level, Therefore, the low level of the lighting on/off control signal corresponds to an off state of the corresponding bypass switch, and the high level of the lighting on/off control signal corresponds to an on state of the corresponding bypass switch.
  • the bypass driver circuit 112 is a microcomputer, and operates at relatively long time intervals, In particular, the bypass driver circuit 112 monitors the abnormality detection signal over a given abnormality determination period for the respective LEDs to determine whether the abnormality is generated, or not. Then, if it is determined that the abnormality is generated in a certain LED, the bypass driver circuit 112 fixes the lighting on/off control signal corresponding to that LED to the high level, This will be described with a concept of certainty and uncertainty of the abnormality, When the bypass driver circuit 112 continuously detects the abnormal state for the abnormality determination period, the bypass driver circuit 112 decides the abnormal state as abnormality, and subjects the bypass switch to on-latch control.
  • bypass switch normally-off
  • the switching element large in size and large in tolerated dose is required as the bypass switch, resulting in an upsized circuit and an increase in the costs. If the on-latch control is conducted on the bypass switch immediately after the detection of the disconnection abnormality, the power loss is reduced.
  • the number of determinations in the bypass driver circuit 112 is decreased (determination time is short), and in particular, a possibility of the misdetection (malfunction) of the disconnection abnormality in a PWM dimming mode becomes high.
  • the bypass switch operates as a switch for realizing the limiter function when the lighting on/off control signal is low level. For that reason, there is a risk that the power loss is increased in the bypass switch, likewise.
  • the power loss caused by the disconnection is increased more as the on-duty ratio is smaller.
  • the power loss in the bypass switch when the bypass switch is turned on is mainly caused by the on-resistance of the bypass switch, and slight, and extremely smaller than the power loss particularly when the bypass switch basically operates in the linear area,
  • FIG. 11 is a circuit diagram illustrating a configuration of a second bypass circuit 870-2 in a semiconductor light source control device according to a fifth modified example.
  • the other bypass circuits are configured in the same manner as that of the second bypass circuit 870-2.
  • a second switch level shift circuit 854-2 of the second bypass circuit 870-2 receives a second lighting on/off control signal Sc2' from a bypass driver circuit 812, and converts the second lighting on/off control signal Sc2' into the second bypass switch drive signal Sd2.
  • the second switch level shift circuit 854-2 sets the second bypass switch drive signal Sd2 to the low level if the second lighting on/off control signal Sc2' is high level, and sets the second bypass switch drive signal Sd2 to the high level if the second lighting on/off control signal Sc2' is low level.
  • a second bypass/limiter circuit 850-2 of the second bypass circuit 870-2 may not have a resistor corresponding to the sixteenth resistor 260.
  • the second switch level shift circuit 854-2 includes a 26 th resistor 822, a 27 th resistor 814, a 28 th resistor 816, a 29 th resistor 818, and a fifth pnp bipolar transistor 820.
  • One end of the 26th resistor 822 is connected to a terminal of the bypass driver circuit 812.
  • the second lighting on/off control signal Sc2' is output from the terminal of the bypass driver circuit 812.
  • the other end of the 26 th resistor 822 is connected to a base of the fifth pnp bipolar transistor 820.
  • One end of the 27 th resistor 814 is connected to a connection node between the other end of the 26 th resistor 822 and the base of the fifth pnp bipolar transistor 820.
  • a positive control supply voltage Vcc is applied to the other end of the 27 th resistor 814, and an emitter of the fifth pnp bipolar transistor 820.
  • a collector of the fifth pnp bipolar transistor 820 is connected to one end of the 28 th resistor 816.
  • the other end of the 28 th resistor 816 is connected to one end of the 29 th resistor 818.
  • the other end of the 29 th resistor 818 is connected to the cathode of the second LED 2-2.
  • a connection node between the 28 th resistor 816 and one end of the 29 th resistor 818 is connected to the gate of the second bypass switch 110-2.
  • a signal generated in the connection node forms the second bypass switch drive signal Sd2.
  • the bypass driver circuit 812 sets the second lighting on/off control signal Sc2' as a high level/low level repetitive signal having a cycle of several msec.
  • the bypass driver circuit 812 increases the on-duty ratio and the cycle of a signal to be supplied to the control input terminal, that is, the gate of the second bypass switch 110-2 larger than those of the normal PWM dimming in synchronization with the second lighting on/off control signal Sc2'.
  • the bypass driver circuit 812 starts the abnormality determination period for the second LED 2-2, and increases the ratio of a duration of the low level to one cycle of the second lighting on/off control signal Sc2'.
  • the cycle of the second lighting on/off control signal Sc2' increases to several hundred msec, and the on-duty ratio increases to 90% or higher.
  • FIG. 12 is a timing chart illustrating a change in the second lighting on/off control signals Sc2 and Sc2' when the disconnection is generated in the second LED 2-2.
  • a waveform represented on an upper stage of FIG. 12 represents the second lighting on/off control signal Sc2' when the semiconductor light source control device according to the fifth modified example conducts the PWM dimming in a first cycle PT1 of about several msec in the normal lighting state.
  • a waveform represented in a middle stage of FIG. 12 represents the second lighting on/off control signal Sc2 when the semiconductor light source control device 100 according to the embodiment always conducts lighting in the normal lighting state.
  • a waveform represented on a lower stage of FIG. 12 represents the second lighting on/off control signal Sc2 when the semiconductor light source control device 100 according to the embodiment conducts the PWM dimming in the first cycle PT1 in the normal lighting state.
  • a cycle of the second lighting on/off control signal Sc2' becomes a second cycle PT2 of about several hundred msec larger than the first cycle PT1.
  • the bypass driver circuit 812 lengthens the duration of the low level while maintaining a length of the duration of the high level in one cycle of the second lighting on/off control signal Sc2', to thereby realize an increase in the cycle
  • the second cycle PT2 may be smaller than the second time constant for the discharge of the second integrating circuit 278-2.
  • the bypass driver circuit 812 keeps the increased on-duty ratio and cycle of the signal to be supplied to the gate of the second bypass switch 110-2 in synchronization with the second lighting on/off control signal Sc2' if the voltage of the second abnormality detection signal Sdet2 when the second lighting on/off control signal Sc2' is set to the high level is higher than the level threshold value Vg.
  • the bypass driver circuit 812 If the voltage of the second abnormality detection signal Sdet2 falls below the level threshold value Vg, the bypass driver circuit 812 returns the second lighting on/off control signal Sc2' to a state having the first cycle PT1, The bypass driver circuit 812 determines that the abnormality is generated (that is, abnormality certainty) if a state in which the voltage of the second abnormality detection signal Sdet2 is higher than the level threshold value Vg is continued until the abnormality determination period PT3 is expired. Then, the bypass driver circuit 812 fixes the second lighting on/off control signal Sc2' to the low level,
  • the state of the second lighting on/off control signal Sc2 remains in the same state as that before the abnormality is generated, during the abnormality determination period PT3. Then, if the abnormality determination period PT3 is expired, it is determined that the abnormality is generated, and the second lighting on/off control signal Sc2 is fixed to the high level.
  • a total length of the off-periods of the bypass switch in the abnormality determination period can be shortened even in the always-on state or even in the PWM dimming. Since the off-period corresponds to a period during which the bypass switch operates in the linear area when the disconnection is generated, the power loss in the bypass switch can be reduced in the fifth modified example. As a result, the switching element low in withstand can be employed as the bypass switch, so that the circuit can be downsized, and the costs can be reduced.
  • the fifth modified example in a status where it is improper to determine that the abnormality is generated immediately with the level transition of the abnormality detection signal, according to the fifth modified example, it can be more precisely determined whether the abnormality is generated, or not, by monitoring the abnormality detection signal over the abnormality determination period, and the power loss of the bypass switch in the abnormality determination period can be reduced.

Landscapes

  • Circuit Arrangement For Electric Light Sources In General (AREA)
  • Led Devices (AREA)
  • Dc-Dc Converters (AREA)
  • Lighting Device Outwards From Vehicle And Optical Signal (AREA)
  • Optical Communication System (AREA)
EP13171471.9A 2012-06-11 2013-06-11 Dispositif de commande de source lumineuse Active EP2675247B1 (fr)

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JP2012242710A JP6030922B2 (ja) 2012-06-11 2012-11-02 光源制御装置

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2170011A3 (fr) * 2008-09-30 2014-07-16 Koito Manufacturing Co., Ltd. Lampe véhiculaire
DE102015224918A1 (de) * 2015-12-10 2017-06-14 Automotive Lighting Reutlingen Gmbh Schaltanordnung für ein Lichtmodul einer Beleuchtungseinrichtung eines Kraftfahrzeugs
EP3247173A3 (fr) * 2016-05-17 2018-01-24 Rohm Co., Ltd. Circuit intégré de commande d'élément électroluminescent
CN108141940A (zh) * 2015-08-04 2018-06-08 株式会社小糸制作所 车辆用灯具及光源的点亮电路
US10327290B2 (en) 2017-09-22 2019-06-18 Koito Manufacturing Co., Ltd. Lighting circuit and vehicle lamp
EP3544384A1 (fr) * 2018-03-22 2019-09-25 Toyota Jidosha Kabushiki Kaisha Dispositif de commande de source lumineuse pour véhicule et support lisible par ordinateur stockant un programme de commande de source de lumière pour véhicule

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6235367B2 (ja) * 2014-02-17 2017-11-22 株式会社小糸製作所 車両用灯具およびその駆動装置、その制御方法
JP6302706B2 (ja) * 2014-03-05 2018-03-28 株式会社小糸製作所 車両用灯具およびその駆動装置
WO2015145742A1 (fr) * 2014-03-28 2015-10-01 株式会社島津製作所 Circuit d'excitation de diode laser et dispositif laser
KR101796608B1 (ko) 2014-07-31 2017-11-10 가부시키가이샤 니혼 마이크로닉스 시트상 전지 시험장치 및 시트상 전지 시험방법
JP6314743B2 (ja) * 2014-08-20 2018-04-25 株式会社デンソー 発光装置
CN104483956B (zh) * 2014-10-28 2017-04-19 北京汽车股份有限公司 汽车控制器性能检测方法与装置
JP6634293B2 (ja) * 2015-04-06 2020-01-22 株式会社小糸製作所 駆動回路、車両用灯具
EP3426009A4 (fr) * 2016-03-03 2019-10-09 Koito Manufacturing Co., Ltd. Appareil d'éclairage de véhicule et son circuit d'éclairage
EP3836756A4 (fr) * 2018-08-10 2021-09-22 Koito Manufacturing Co., Ltd. Circuit d'éclairage et lampe de véhicule
JP7353809B2 (ja) * 2019-06-14 2023-10-02 キヤノン株式会社 電源装置及び画像形成装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050140345A1 (en) * 2003-10-23 2005-06-30 Mitsubishi Denki Kabushiki Kaisha Redundancy circuit for series-connected diodes
DE102007024784A1 (de) * 2007-05-26 2008-11-27 Automotive Lighting Reutlingen Gmbh Schaltungsanordnung insbesondere für Kraftfahrzeugscheinwerfer und Kraftfahrzeugleuchten
JP2011192865A (ja) * 2010-03-16 2011-09-29 Koito Mfg Co Ltd 点灯制御装置及び車両用灯具
US20120025713A1 (en) * 2010-07-30 2012-02-02 International Rectifier Corporation System using shunt circuits to selectively bypass open loads
EP2427033A2 (fr) * 2010-09-07 2012-03-07 Monolithic Power Systems, Inc. Circuit de dérivation pour diodes électroluminescentes couplées en série et procédés de fonctionnement associés

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002025784A (ja) * 2000-04-28 2002-01-25 Takashi Ishizawa Ｌｅｄ点灯回路
JP4241487B2 (ja) * 2004-04-20 2009-03-18 ソニー株式会社 Ｌｅｄ駆動装置、バックライト光源装置及びカラー液晶表示装置
US7994725B2 (en) * 2008-11-06 2011-08-09 Osram Sylvania Inc. Floating switch controlling LED array segment
JP2010272410A (ja) * 2009-05-22 2010-12-02 Hitachi Displays Ltd バックライト装置並びに表示装置
WO2010148196A2 (fr) * 2009-06-18 2010-12-23 Musco Corporation Appareil et procédé pour une dérivation de del défectueuses dans des réseaux d'éclairage
CN201663727U (zh) * 2009-12-18 2010-12-01 国琏电子（上海）有限公司 旁路保护电路及使用其的发光二极管驱动装置
RU2562957C2 (ru) * 2010-07-09 2015-09-10 Конинклейке Филипс Электроникс Н.В. Схема контроля для органического светоизлучающего диода
CN102355778B (zh) * 2010-09-07 2014-02-19 成都芯源系统有限公司 一种旁路电路及旁路方法
CN101969720B (zh) * 2010-09-15 2013-09-18 成都芯源系统有限公司 Led旁路控制电路和控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050140345A1 (en) * 2003-10-23 2005-06-30 Mitsubishi Denki Kabushiki Kaisha Redundancy circuit for series-connected diodes
DE102007024784A1 (de) * 2007-05-26 2008-11-27 Automotive Lighting Reutlingen Gmbh Schaltungsanordnung insbesondere für Kraftfahrzeugscheinwerfer und Kraftfahrzeugleuchten
JP2011192865A (ja) * 2010-03-16 2011-09-29 Koito Mfg Co Ltd 点灯制御装置及び車両用灯具
US20120025713A1 (en) * 2010-07-30 2012-02-02 International Rectifier Corporation System using shunt circuits to selectively bypass open loads
EP2427033A2 (fr) * 2010-09-07 2012-03-07 Monolithic Power Systems, Inc. Circuit de dérivation pour diodes électroluminescentes couplées en série et procédés de fonctionnement associés

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2170011A3 (fr) * 2008-09-30 2014-07-16 Koito Manufacturing Co., Ltd. Lampe véhiculaire
CN108141940A (zh) * 2015-08-04 2018-06-08 株式会社小糸制作所 车辆用灯具及光源的点亮电路
EP3334255A4 (fr) * 2015-08-04 2019-05-15 Koito Manufacturing Co., Ltd. Outil d'éclairage pour véhicule et circuit d'éclairage de source lumineuse
CN108141940B (zh) * 2015-08-04 2019-11-19 株式会社小糸制作所 车辆用灯具及光源的点亮电路
US10569695B2 (en) 2015-08-04 2020-02-25 Koito Manufacturing Co., Ltd. Vehicular lamp
EP3624566A1 (fr) * 2015-08-04 2020-03-18 Koito Manufacturing Co., Ltd. Outil d'éclairage pour véhicule et circuit d'éclairage à source lumineuse
DE102015224918A1 (de) * 2015-12-10 2017-06-14 Automotive Lighting Reutlingen Gmbh Schaltanordnung für ein Lichtmodul einer Beleuchtungseinrichtung eines Kraftfahrzeugs
EP3247173A3 (fr) * 2016-05-17 2018-01-24 Rohm Co., Ltd. Circuit intégré de commande d'élément électroluminescent
US10360969B2 (en) 2016-05-17 2019-07-23 Rohm Co., Ltd. Light emitting element driving semiconductor integrated circuit, light emitting element driving device, light emitting device, and vehicle
US10327290B2 (en) 2017-09-22 2019-06-18 Koito Manufacturing Co., Ltd. Lighting circuit and vehicle lamp
EP3544384A1 (fr) * 2018-03-22 2019-09-25 Toyota Jidosha Kabushiki Kaisha Dispositif de commande de source lumineuse pour véhicule et support lisible par ordinateur stockant un programme de commande de source de lumière pour véhicule
US10836310B2 (en) 2018-03-22 2020-11-17 Toyota Jidosha Kabushiki Kaisha Light source control device for vehicle and computer-readable medium storing a light source control program for vehicle

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Publication number Publication date
EP2800457B1 (fr) 2021-08-04
EP2675247B1 (fr) 2020-08-05
EP2800457A3 (fr) 2015-08-26
CN103491668A (zh) 2014-01-01
CN104902630B (zh) 2019-02-19
CN103491668B (zh) 2017-04-26
EP2800457A2 (fr) 2014-11-05
CN104902630A (zh) 2015-09-09
JP6030922B2 (ja) 2016-11-24
JP2014017463A (ja) 2014-01-30

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