EP2617071A1 - Composant semiconducteur optoélectronique avec revêtement galvanique et procédé de fabrication d'un composant semiconducteur optoélectronique - Google Patents

Composant semiconducteur optoélectronique avec revêtement galvanique et procédé de fabrication d'un composant semiconducteur optoélectronique

Info

Publication number
EP2617071A1
EP2617071A1 EP11743492.8A EP11743492A EP2617071A1 EP 2617071 A1 EP2617071 A1 EP 2617071A1 EP 11743492 A EP11743492 A EP 11743492A EP 2617071 A1 EP2617071 A1 EP 2617071A1
Authority
EP
European Patent Office
Prior art keywords
optoelectronic semiconductor
semiconductor chip
metallic carrier
electrically insulating
semiconductor component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11743492.8A
Other languages
German (de)
English (en)
Inventor
Siegfried Herrmann
Helmut Fischer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of EP2617071A1 publication Critical patent/EP2617071A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/647—Heat extraction or cooling elements the elements conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0217—Removal of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0235—Method for mounting laser chips
    • H01S5/02355—Fixing laser chips on mounts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting

Definitions

  • An optoelectronic semiconductor component is specified.
  • a method for producing an optoelectronic semiconductor device is specified.
  • WO 2009/079978 describes optoelectronic
  • An object to be solved is to provide an optoelectronic semiconductor device, the improved thermal
  • the optoelectronic semiconductor device In accordance with at least one disclosed embodiment of the optoelectronic semiconductor device, the optoelectronic
  • Semiconductor component at least one substrathom
  • Optoelectronic semiconductor chip may be a
  • Radiation-emitting semiconductor chip in particular a light-emitting diode act.
  • Semiconductor chip is then formed by a laser diode or by a light emitting diode.
  • UV radiation Radiation in the wavelength range between UV radiation and infrared radiation, in particular of visible light
  • the optoelectronic semiconductor chip is a part of the optoelectronic semiconductor chip.
  • the optoelectronic semiconductor chip is substrateless. That is, a growth substrate onto which the semiconductor layers of the optoelectronic
  • Optoelectronic semiconductor chip therefore consists of its epitaxially grown semiconductor layers and
  • metallizations which are applied to an outer surface of the semiconductor body formed by the epitaxially grown semiconductor layers.
  • Substrate-free optoelectronic semiconductor chip is characterized, inter alia, by its small thickness.
  • Semiconductor chip has a thickness of less than 10 ⁇ , preferably less than 7 ⁇ , for example, about 6 ⁇ on.
  • the substratlose optoelectronic semiconductor chip has on its upper side a first main surface and at its
  • Main surfaces can pass through at least one side surface
  • the second main surface can then serve as a mounting surface with which the optoelectronic
  • the optoelectronic component comprises
  • Semiconductor device has a metallic carrier attached to the
  • the metallic carrier is formed with a material having metallic properties.
  • the metallic carrier is made of a metal or a metal alloy.
  • the metallic carrier is arranged on the underside of the optoelectronic semiconductor chip and
  • the metallic carrier is deposited galvanically or de-energized on the second main surface of the optoelectronic semiconductor chip. That is, the metallic carrier is generated by electrodeposition or electroless deposition.
  • the production by means of galvanic or electroless deposition is an objective feature of the finished optoelectronic semiconductor device
  • the optoelectronic semiconductor component Semiconductor chips is deposited and not otherwise attached to the optoelectronic semiconductor chip.
  • the metallic carrier projects beyond the optoelectronic semiconductor chip in at least one embodiment
  • the lateral directions are included For example, ene directions which are parallel to the second main surface of the optoelectronic semiconductor chip. In the present case, therefore, the metallic carrier does not terminate flush with the optoelectronic in the lateral direction
  • the metallic carrier preferably projects completely beyond the optoelectronic semiconductor chip. That is, the metallic carrier then projects beyond the optoelectronic semiconductor chip in all lateral directions, that is, on all side surfaces of the optoelectronic
  • the metallic carrier thereby has a larger base area than the optoelectronic semiconductor chip.
  • the semiconductor component comprises a substrateless optoelectronic semiconductor chip which has a first main surface on an upper side and a second main surface on an underside.
  • Optoelectronic semiconductor device a metallic
  • Semiconductor chips is arranged, wherein the metallic carrier projects beyond the optoelectronic semiconductor chip in at least one lateral direction and the metallic carrier is deposited galvanically or de-energized on the second main surface of the optoelectronic semiconductor chip.
  • optoelectronic semiconductor chip The present described optoelectronic semiconductor device allows this geometry dependence between optoelectronic
  • the metallic carrier may have other geometric dimensions and shapes than the optoelectronic semiconductor chip.
  • the metallic carrier on which the optoelectronic semiconductor chip is located can be made geometrically variable.
  • Semiconductor chips can be expanded in a lateral direction. This can, for example, an improved
  • Semiconductor device can be achieved.
  • a method for producing an optoelectronic semiconductor component is specified.
  • a multiplicity of optoelectronic semiconductor chips is initially provided
  • the optoelectronic semiconductor chip is
  • Substrate-free optoelectronic semiconductor chips That is, the growth substrate of the optoelectronic semiconductor chips is removed prior to deployment and before the
  • Optoelectronic semiconductor chips are separated into, for example, a semiconductor wafer in the plurality of substrateless optoelectronic semiconductor chips. According to at least one embodiment of the method, in a next method step, the plurality of
  • Optoelectronic semiconductor chips disposed on an intermediate carrier and mechanically fastened may for example consist of a ceramic material or glass.
  • the attachment can be done for example by means of a releasable adhesive bond.
  • the optoelectronic semiconductor chips can be arranged on the intermediate carrier at arbitrary distances from each other. Preferably, the optoelectronic semiconductor chips are arranged at a distance from each other, so that between each two immediately adjacent to each other optoelectronic semiconductor chips
  • Gap be chosen particularly large, so that there is a metallic carrier, which is particularly far in the lateral direction over the optoelectronic semiconductor chip
  • the electrically insulating layer can For example, be formed with a silicone, an epoxy resin or a combination of these materials. Further, it is possible that the electrically insulating layer contains PCB or a spin-on glass or consists of one of these materials.
  • a seed layer is applied to the side of the optoelectronic side facing away from the intermediate carrier
  • the seed layer is formed for example with a metallic material and can be applied by vapor deposition or sputtering.
  • the seed layer makes an intimate connection with the optoelectronic semiconductor chips and the electrically insulating layer.
  • a metallic carrier is then deposited galvanically or electrolessly.
  • the method comprises the following steps:
  • Optoelectronic semiconductor chips are spaced from each other, so that between two
  • each immediately adjacent optoelectronic semiconductor chips is formed a gap, and Filling the intermediate spaces with an electrically insulating layer,
  • an optoelectronic semiconductor component described here can preferably be produced. That is, all features disclosed for the method are also disclosed for the optoelectronic semiconductor device and vice versa.
  • the following embodiments relate to both
  • the form dominates
  • the metallic carrier the optoelectronic semiconductor chip in at least one lateral direction by at least 100 ⁇ , preferably by at least 250 ⁇ . It is possible that the metallic carrier the optoelectronic semiconductor chip in all lateral directions by at least 100 ⁇ ,
  • the form dominates
  • the metallic carrier the optoelectronic semiconductor chip in at least one lateral direction by at least 10%, preferably by at least 25% of the maximum edge length of the optoelectronic semiconductor chip.
  • the maximum edge length of the optoelectronic semiconductor chip is the length of the longer of the two edges in the case of a rectangular optoelectronic semiconductor chip.
  • At a round Optoelectronic semiconductor chip is the maximum edge length of the diameter of the optoelectronic
  • the seed layer may consist of the same or a different material than the metallic carrier.
  • the seed layer is applied by sputtering or vapor deposition.
  • the germ layer is applied by sputtering or vapor deposition.
  • the seed layer is set up to reflect electromagnetic radiation to be emitted or to be detected by the optoelectronic semiconductor chip.
  • the seed layer then has a
  • the seed layer may contain silver, for example.
  • the metallic carrier is electrically conductive and forms at least one
  • the metallic carrier is at least one contact point of the optoelectronic Semiconductor chips electrically conductively connected, for example, the side facing away from the optoelectronic semiconductor chip side of the metallic carrier then forms at least one
  • the seed layer is also designed to be electrically conductive, so that an over the
  • the metallic carrier comprises subareas that are electrically insulated from one another, wherein each of the subregions forms an electrical connection point of the optoelectronic semiconductor component, and the
  • connection points are unequal names. That is, the metallic carrier is divided into at least two subregions, the connection points to the n- and p-side
  • the optoelectronic semiconductor device is surface mountable, wherein the
  • connection points are formed on the side remote from the optoelectronic semiconductor chip side of the metallic carrier.
  • the metallic support comprises or consists of one of the following materials: nickel, copper, gold, palladium.
  • the metallic carrier it is possible for the metallic carrier to have regions, for example layers, of other materials.
  • the following layer structure comprising: a layer of nickel, a layer of
  • this comprises
  • Optoelectronic semiconductor device a variety
  • the optoelectronic semiconductor device in particular also be optoelectronic semiconductor chips that emit light of different colors.
  • the optoelectronic semiconductor device then comprises at least a red light, a green light and a blue light-emitting optoelectronic semiconductor chip.
  • the optoelectronic semiconductor chips of the optoelectronic semiconductor component can be electrically separated from one another so that they can be operated independently of one another.
  • this comprises
  • Optoelectronic semiconductor device exactly one single substrateless optoelectronic semiconductor chip.
  • this comprises
  • Optoelectronic semiconductor device an electrical
  • the electrically insulating layer which covers the metallic carrier on its outer surface facing the optoelectronic semiconductor chip and on the outer surface free of the optoelectronic semiconductor chip, wherein the electrically insulating layer comprises a
  • the electrically insulating layer may, for example, be flush with the first main area of the optoelectronic semiconductor chip facing away from the carrier
  • the optoelectronic semiconductor chip can be completely separated from the electrical surface at its side surfaces
  • the optoelectronic semiconductor chip facing the main surface of the carrier at the top of the carrier is therefore completely from the
  • the electrically insulating layer is set up to be emitted or supplied by the optoelectronic semiconductor chip during operation
  • the electrically insulating layer may, for example, comprise particles of a filler. Reflective means that the electrically insulating layer has a reflectivity of radiation in the visible spectral range
  • the electrically insulating circuitry in particular more than 80% or more than 90%, preferably more than 94%.
  • the electrically insulating layer preferably reflects diffusely.
  • the electrically insulating layer preferably appears white.
  • the reflective particles are made of, for example, a metal oxide such as alumina or titania, a metal fluoride such as calcium fluoride or a silica, or consist thereof.
  • a mean diameter of the particles for example a median diameter d5 Q in Qg, is preferably between 0.3 ⁇ and 5 ⁇ .
  • reflective layer is preferably between
  • the particles work reflective due to its preferably white color and / or due to its refractive index difference to that
  • Matrix material According to at least one embodiment, only the first main surface of the optoelectronic semiconductor chip is freely accessible. That is, except for the first main surface, the optoelectronic semiconductor chip is completely covered. The optoelectronic semiconductor chip can thereby
  • the seed layer For example, be covered by the seed layer, the metallic carrier and / or the electrically insulating layer.
  • the optoelectronic semiconductor chip if it is a radiation-emitting semiconductor chip, emits the electromagnetic radiation generated during operation exclusively through the first main surface.
  • Separation structures are used to form electrically isolated portions of the metallic carrier in the finished optoelectronic semiconductor device
  • Form connecting points of the optoelectronic semiconductor device which may be unlike names.
  • Figures 1A and 1B show schematically
  • Figure 1A Representation of Figure 1A is a first embodiment of an optoelectronic device described herein
  • the optoelectronic semiconductor component comprises a substrateless
  • Optoelectronic semiconductor chip 1 is free of one
  • the optoelectronic semiconductor chip is, for example, a
  • Lumineszenzdiodenchip for example, a light-emitting diode, or to a radiation-detecting chip such as a photodiode.
  • the optoelectronic semiconductor chip has at its
  • the optoelectronic semiconductor chip 1 On top of a first major surface la. On its underside, the optoelectronic semiconductor chip 1 has a second main surface 1b.
  • the optoelectronic semiconductor chip is cuboid, so that the first
  • Main surface la and the second major surface lb have the same shape and size.
  • the optoelectronic semiconductor component further comprises a metallic carrier 2.
  • the metallic carrier is produced by galvanic or electroless deposition.
  • a seed layer 21 is arranged, which has a mechanically strong connection between the metallic carrier 2 and the optoelectronic
  • Semiconductor chip 1 mediates.
  • the carrier 2 completely projects beyond the optoelectronic semiconductor chip 1 on its side surfaces 1c in all lateral directions 1.
  • the base area of the carrier 2 is at least twice the area of the second main area 1b and / or the first main area 1a of the optoelectronic semiconductor chip.
  • the carrier 2 is designed to be electrically conductive.
  • the seed layer 21 is formed electrically conductive.
  • the carrier 2 therefore forms an electrical connection point of the optoelectronic semiconductor component and is connected to the bottom lb electrically conductively connected to the optoelectronic semiconductor chip 1.
  • the carrier 2 has two partial regions 2 a, 2 b, which are electrically insulated from one another by an electrically insulating material 3.
  • the electrically insulating material may be formed, for example, with silicone, epoxy, a ceramic material or a glass-containing material.
  • the subareas 2a, 2b form unequal connection points of the optoelectronic semiconductor chip 1. For example, they are with
  • the optoelectronic semiconductor component is therefore surface-mountable, that is to say it can be remote from the semiconductor chip 1 by means of an adhesive or soldered connection
  • the underside of the carrier 2 mechanically fixed and be electrically contacted.
  • an electrically insulating layer 4 which covers the optoelectronic semiconductor chip 1 at the side surfaces lc and flush with the first
  • Main surface la can complete, so that the
  • insulating layer 4 do not project beyond each other.
  • insulating layer 4 is formed radiation-reflective and is provided with particles of a filler.
  • the electrically insulating layer 4 can cover, for example, the seed layer 21. In the region of the electrically insulating material 3, however, the seed layer 21 is removed, so that the electrically insulating layer 4 and the electrically
  • insulating material 3 are in direct contact with each other.
  • Optoelectronic semiconductor chip 1 is replaced by a
  • Connecting agent layer 6 mediates, which is for example an adhesive connection. Between the optoelectronic semiconductor chips 1 spaces 7 are formed.
  • the gaps 7 are subsequently provided with the electrically insulating layer 4, which may be formed for example with PCB or spin-on glass.
  • the seed layer 21 is on the top of the intermediate carrier 5 facing away from the
  • the seed layer 21 is followed by the metallic carrier composite 20, which is deposited, for example, galvanically or electrolessly on the seed layer 21
  • step 2d the separation takes place to individual optoelectronic semiconductor components, each having a metallic carrier 2 and at least one
  • Optoelectronic semiconductor chip 1 see Figure 2D.
  • Connection carrier for example, a lead frame 11 with the underside of the metallic support 2 facing away from the optoelectronic semiconductor chip 1
  • Example be fixed by soldering.
  • the metallic carrier 2 then forms a first electrical connection point of the optoelectronic semiconductor component.
  • connection point is formed by the bonding pad 10a on the first main surface la of the optoelectronic semiconductor chip 1, which is connected by means of a connecting wire 9 with a corresponding bonding pad 10b of the support frame 11. As shown schematically in FIG. 2E, from
  • Optoelectronic semiconductor chip 1 generated in operation heat 8 are discharged through the metal substrate 2 particularly large area to the support frame 11.
  • Figures 3A to 3G is another
  • Separation structures for example, by exposure and developing a photoresist 12 on the side facing away from the intermediate carrier 5 side of the seed layer 21 is formed.
  • the isolating structures 12 form electrical insulators during the deposition of the carrier composite 20 galvanically or de-energized.
  • FIG. 3E the electrically insulating separating structures 12 are detached, so that openings 13 in the carrier assembly 20 are formed.
  • FIG. 3F shows that the openings 13 are subsequently filled up with the electrically insulating material 3.
  • Singling can, for example, as synonymous with the
  • Photographic technique and subsequent etching for example, with FeC13 done.
  • Optoelectronic semiconductor device for example, prepared by a method similar to the method described in connection with Figures 3A to 3G can be.
  • the electrically insulating layer 4 is dispensed with by removal of the same after completion of the method.
  • the layer 4 can also remain in the optoelectronic semiconductor component.
  • the contacting of the optoelectronic semiconductor chip 1 is now shown in more detail with reference to FIGS. 4A and 4B.
  • the optoelectronic semiconductor chip 1 has at its
  • Contact point 14a serves for n-side connection.
  • Optoelectronic semiconductor chip 1 may be formed, which is coated with an electrically insulating material and filled with an electrically conductive material, which produces an electrical contact to the p-side of the semiconductor chip 1.
  • the breakdown may also be connected to the n-type semiconductor material, that is, unlike in FIG. 4B, n-side and p-side contacts may also be interchanged.
  • the electrically insulating material 3 is now arranged in a trench so that a partial region 2b of the carrier 2 is formed, which is electrically insulated from the partial regions 2a. In this way, on the semiconductor chip 1 opposite bottom of the carrier two connection points for electrical contacting of the optoelectronic
  • FIG. 4B shows a sectional view along the interface between carrier 2 and optoelectronic semiconductor chip 1.

Abstract

L'invention concerne un composant semiconducteur optoélectronique, comportant une puce de semiconducteur optoélectronique (1) sans substrat qui possède, sur une face supérieure, une première surface principale (1a) et, sur une face inférieure, une deuxième surface principale (1b), et comportant un support métallique (2) qui est disposé sur la face inférieure de la puce de semiconducteur optoélectronique (1). Le support métallique (2) dépasse de la puce de semiconducteur optoélectronique (1) dans au moins une direction latérale (1) et le support métallique (2) est déposé galvaniquement ou sans courant sur la deuxième surface principale (1b) de la puce de semiconducteur optoélectronique (1).
EP11743492.8A 2010-09-15 2011-07-27 Composant semiconducteur optoélectronique avec revêtement galvanique et procédé de fabrication d'un composant semiconducteur optoélectronique Withdrawn EP2617071A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102010045390A DE102010045390A1 (de) 2010-09-15 2010-09-15 Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronisches Halbleiterbauteils
PCT/EP2011/062916 WO2012034764A1 (fr) 2010-09-15 2011-07-27 Composant semiconducteur optoélectronique avec revêtement galvanique et procédé de fabrication d'un composant semiconducteur optoélectronique

Publications (1)

Publication Number Publication Date
EP2617071A1 true EP2617071A1 (fr) 2013-07-24

Family

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EP11743492.8A Withdrawn EP2617071A1 (fr) 2010-09-15 2011-07-27 Composant semiconducteur optoélectronique avec revêtement galvanique et procédé de fabrication d'un composant semiconducteur optoélectronique

Country Status (6)

Country Link
US (1) US9041020B2 (fr)
EP (1) EP2617071A1 (fr)
KR (1) KR101505336B1 (fr)
CN (1) CN103140948B (fr)
DE (1) DE102010045390A1 (fr)
WO (1) WO2012034764A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082921B2 (en) * 2007-10-31 2015-07-14 Cree, Inc. Multi-die LED package
US9172012B2 (en) 2007-10-31 2015-10-27 Cree, Inc. Multi-chip light emitter packages and related methods
US9666762B2 (en) 2007-10-31 2017-05-30 Cree, Inc. Multi-chip light emitter packages and related methods
DE102010045390A1 (de) 2010-09-15 2012-03-15 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronisches Halbleiterbauteils
US20130075928A1 (en) * 2011-09-23 2013-03-28 Texas Instruments Incorporated Integrated circuit and method of making
KR101961310B1 (ko) * 2012-07-09 2019-07-17 엘지이노텍 주식회사 발광 장치
DE102012108160A1 (de) * 2012-09-03 2014-03-06 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauelement und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauelements
DE102012111245A1 (de) 2012-11-21 2014-05-22 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Anschlussbereichs eines optoelektronischen Halbleiterchips
DE102015103571A1 (de) * 2015-03-11 2016-09-15 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Vielzahl an Konversionselementen, Konversionselement und optoelektronisches Bauelement
DE102015119343A1 (de) * 2015-11-10 2017-05-11 Osram Opto Semiconductors Gmbh Anordnung mit einem Träger aus einem Glasmaterial und einem optoelektronischen Halbleiterbauteil
DE102017104742A1 (de) * 2017-03-07 2018-09-13 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements
DE102017106410A1 (de) * 2017-03-24 2018-09-27 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Bauelements und optoelektronisches Bauelement

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3896044B2 (ja) 2002-07-11 2007-03-22 シャープ株式会社 窒化物系半導体発光素子の製造方法およびその製品
DE10355600B4 (de) * 2003-11-28 2021-06-24 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Halbleiterchip und Verfahren zur Herstellung von Halbleiterchips
DE502005006760D1 (de) 2004-09-22 2009-04-16 Osram Opto Semiconductors Gmbh Seitlich optisch gepumpter oberflächenemittierender halbleiterlaser mit einer integrierten wärmesenke
US7256483B2 (en) * 2004-10-28 2007-08-14 Philips Lumileds Lighting Company, Llc Package-integrated thin film LED
US7195944B2 (en) * 2005-01-11 2007-03-27 Semileds Corporation Systems and methods for producing white-light emitting diodes
DE102005053274A1 (de) 2005-09-30 2007-04-12 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen einer Mehrzahl von Halbleiterchips und Halbleiterbauelement
KR100714589B1 (ko) 2005-10-05 2007-05-07 삼성전기주식회사 수직구조 발광 다이오드의 제조 방법
KR100899805B1 (ko) 2006-07-04 2009-05-28 학교법인 포항공과대학교 조셉슨 볼텍스 운동을 이용한 테라헤르즈 전자기파 발진 및검출 소자
KR100867541B1 (ko) * 2006-11-14 2008-11-06 삼성전기주식회사 수직형 발광 소자의 제조 방법
DE102007022947B4 (de) * 2007-04-26 2022-05-05 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronischer Halbleiterkörper und Verfahren zur Herstellung eines solchen
DE102007029370A1 (de) 2007-05-04 2008-11-06 Osram Opto Semiconductors Gmbh Halbleiterchip und Verfahren zur Herstellung eines Halbleiterchips
US7759670B2 (en) * 2007-06-12 2010-07-20 SemiLEDs Optoelectronics Co., Ltd. Vertical LED with current guiding structure
DE102007035896A1 (de) 2007-07-31 2009-02-05 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterkörper und optoelektronisches Bauelement
DE102007046743A1 (de) * 2007-09-28 2009-04-02 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement sowie Verfahren zu dessen Herstellung
DE102008011809A1 (de) 2007-12-20 2009-06-25 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement
DE102008035900A1 (de) * 2008-04-30 2009-11-05 Osram Opto Semiconductors Gmbh Leuchtdiodenchip
KR101016171B1 (ko) 2008-06-27 2011-02-23 동광리어유한회사 자동차 시트용 헤드레스트의 폴딩장치
DE102008035254A1 (de) * 2008-07-29 2010-02-11 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip und optoelektronisches Bauteil
DE102010045390A1 (de) 2010-09-15 2012-03-15 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronisches Halbleiterbauteils

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2012034764A1 *

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US9041020B2 (en) 2015-05-26
CN103140948B (zh) 2016-05-11
DE102010045390A1 (de) 2012-03-15
KR20130054414A (ko) 2013-05-24
CN103140948A (zh) 2013-06-05
WO2012034764A1 (fr) 2012-03-22
KR101505336B1 (ko) 2015-03-23

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