Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
  • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0093—Wafer bonding; Removal of the growth substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
  • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
  • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
  • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
  • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
  • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers

Definitions

• the present application relates to a
• Luminescent diodes are often used to increase the
• Component layers deposit buffer layers and / or epitaxial growth promoting growth layers.
• One task is to use a radiation-emitting
• a radiation-emitting semiconductor chip has a carrier and one on the carrier
• the semiconductor layer sequence comprises an active region provided for generating radiation, an n-conducting region and a side of the n-conducting region which faces away from the active region on an active region
• cover layer On the cover layer, a contact structure for external electrical contacting of the n-type region is arranged and the cover layer has at least one recess through which the
• Contact structure extends to the n-type region.
• the electrical contact of the n-type region thus takes place through the recess.
• the electrical contact can be made independently of the electrical conductivity of the cover layer.
• the cover layer can therefore be optimized with regard to other physical properties.
• the cover layer may be used as an adhesion layer and / or as a buffer layer
• the efficiency of radiation production can be increased in this way.
• Cover layer can be omitted. This will be at the
• Production of the semiconductor chip reduces the risk of breakage and further increases the mechanical stability of the semiconductor chip.
• a surface of the cover layer facing away from the active region preferably forms a first main surface of the cover
• Semiconductor body extending direction, is limited by the first main surface.
• the contact structure is thus arranged outside the epitaxial semiconductor body on the semiconductor body and serves in the operation of the semiconductor chips of the injection of
• the covering layer is preferably lattice-matched to the n-conducting region.
• the cover layer can thus have the function of a buffer layer and / or a
• the cover layer is undoped or has a doping concentration of at most 1 * 10 17 cnf 3 .
• Cover layer falls despite the relatively high resistance of a cover layer with such a low
• the carrier is arranged on the side of the active region which faces away from the n-conductive region, and furthermore preferably integrally connected to the semiconductor body.
• connection partners are held together by means of atomic and / or molecular forces.
• a cohesive connection can for example by means of a
• Connecting layer which may contain, for example, an adhesive or a solder can be achieved. Usually a separation of the connection goes with a destruction of the
• the carrier is preferably different from the growth substrate.
• the carrier therefore does not have the high crystalline
• a semiconductor chip in which the growth substrate is completely or at least partially removed or is at least thinned is also referred to as a thin-film semiconductor chip.
• a thin-film semiconductor chip such as a thin-film light-emitting diode chip, can continue to be used within the scope of the present invention
• a support element e.g. A mirror layer is applied to the support, turned first first surface of a semiconductor body, which comprises a semiconductor layer sequence with an active region, in particular an epitaxial layer sequence
• Bragg mirror integrated in the semiconductor layer sequence formed, at least part of the in
• the semiconductor layer sequence has a thickness in the range of 20 ⁇ or less, in particular in the range of 10 ⁇ on; and or
• the semiconductor layer sequence contains at least one
• Semiconductor layer having at least one surface which has a mixing structure which, in the ideal case, results in an approximately ergodic distribution of the light in the
• the coating may, for example, contain a dielectric material, such as an oxide, a nitride or a
• the refractive index of the dielectric material is a
• Refractive indices the greater is the proportion of the radiation that is totally reflected in the direction of the recess on the dielectric material
• Contact structure formed at least partially reflective for the radiation generated in the active region.
• the contact structure has a connection layer adjacent to the n-conducting region and a reflector layer.
• Connection layer is expediently chosen with regard to a good layer adhesion and / or a good contact property to the semiconductor body.
• the semiconductor body For example, the
• Connection layer aluminum or titanium included.
• the reflector layer preferably has a high, in particular for the radiation generated in the active region
• the reflector layer preferably contains a metal or a metallic alloy.
• a metal or a metallic alloy for example, silver, Aluminum, rhodium, palladium or chromium by a high reflectivity in the visible spectral range.
• Gold is particularly suitable for the infrared spectral range.
• the contact surface closes the contact structure on the
• the at least one recess extends in a plan view of the semiconductor chip at least partially along a border of the
• Semiconductor chip in which the semiconductor chip is embedded in a potting can also be an absorption of radiation, which is scattered in the potting, for example, to radiation converter material or diffuser material, and fed back into the semiconductor chip can be reduced.
• Emerging radiation power can therefore be increased.
• At least two of the recesses overlap in a plan view of the semiconductor chip with the contact surface.
• the contact surface thus covers at least two of the recesses.
• Nub structure be formed with elevations and / or depressions.
• the degree of toothing can be adjusted by means of the spatial density of the recesses and / or by means of a degree of filling of the recesses with the material of the contact structure.
• Distribution layer can be provided to several
• the distribution layer can be full-surface or only
• a material for the distribution layer for example, a metal, a semi-metal or a suitable
• TCO transparent conductive oxide
• the cover layer has a structuring, which in particular for increasing the
• the structuring is formed only partially on the cover layer. At least in an area in which the contact structure is formed, the cover layer is preferably unstructured.
• Structuring may be formed, for example, in the form of a roughening or a regular structuring.
• An unstructured surface of the cover layer in the region of the contact structure can be a particularly simple and
• Contact structure must be leveled. As a result, material for the deposition of the contact structure can be saved in the production. Furthermore, a contact structure with a smooth surface has a higher reflectivity than a contact structure on a rough surface.
• At least one light outcoupling region may be defined on a radiation exit surface of the semiconductor chip, for example, the first main surface, in which the
• Cover layer having the structuring, wherein in a laterally adjacent to the Lichtauskoppel Scheme area, the contact structure on an unstructured region of
• Cover layer is formed.
• semiconductor chips are provided on a substrate with a semiconductor layer sequence comprising a cover layer, one for generating radiation
• the semiconductor layer sequence is attached to a carrier.
• the substrate is removed.
• Recesses are formed in the cover layer.
• On the cover layer a contact structure is formed, wherein the
• Contact structure extends into the recesses.
• the semiconductor layer sequence with the carrier is separated into a plurality of semiconductor chips, so that each semiconductor chip has at least one of the recesses.
• the method is particularly suitable for producing a semiconductor chip described above, so that in
• the contact structure is deposited by means of a galvanic process.
• tough hard contact surfaces such as for a Drahtbonditati, can be produced in a simple and cost-effective manner.
• FIG. 1A and 1B show a first exemplary embodiment of a radiation-emitting semiconductor chip in a schematic top view (FIG. 1A) and associated sectional view (FIG. 1B);
• Figure 2 is an enlarged view of a recess according to the first embodiment in a schematic sectional view
• Figures 3A and 3B show a second embodiment of a radiation-emitting semiconductor chip in a schematic plan view ( Figure 3A) and associated sectional view ( Figure 3B).
• Figure 3A shows a third embodiment of a radiation-emitting semiconductor chip in a schematic plan view
• Figure 3B shows a fourth embodiment of a radiation-emitting semiconductor chip in a schematic plan view
• FIGS. 6A to 6D show an exemplary embodiment of FIG
• the semiconductor chip 1 comprises a semiconductor body 2 with a semiconductor layer sequence, which forms the semiconductor body.
• the semiconductor layer sequence is preferably epitaxial, for example deposited by means of MBE or MOCVD.
• the semiconductor body 2 is fastened to a carrier 5 by means of a cohesive connection.
• the carrier is thus different from a growth substrate for the semiconductor layer sequence of the semiconductor body.
• the semiconductor chip in this embodiment is thus formed as a thin-film semiconductor chip. In the vertical direction, ie in a direction perpendicular to a main plane of extension of the
• semiconductor layers of the semiconductor body 2 extending direction, the semiconductor body extends between a first major surface 25 and a second major surface 26th
• the semiconductor layer sequence of the semiconductor body 2 has an active one intended for generating radiation
• Region 23 which is disposed between an n-type region 21 and a p-type region 22.
• a cover layer 24 is formed on the side facing away from the active region of the n-type region. The cover layer closes off the semiconductor body in the vertical direction.
• the cover layer has a low doping concentration in relation to the n-conducting region, for example a doping concentration of at most 1 ⁇ 10 17 cnf 3 .
• a mirror layer 7 is arranged, which reflects the radiation generated in the active region 23 and emitted in the direction of the carrier 5 and in the direction of the first main surface 25
• the first main surface 25 thus serves as
• Connecting layer 6 is formed, for example a
• Adhesive layer or a solder layer Adhesive layer or a solder layer.
• the semiconductor body 2 On the side of the first main surface 25, the semiconductor body 2 has recesses 3, which extend through the cover layer into the n-conductive region 21 or at least toward the n-conductive region. In the recesses, a contact structure 4 is formed, which is adjacent in the recesses 3 to the n-type region and the external
• the contact structure 4 is formed as an example circular.
• One of the recesses 3 is annular and follows a border 46 of the contact structure.
• a mating contact 49 is formed on the side opposite the contact structure 4 side of the semiconductor chip.
• the cover layer 24 has a structuring 8.
• the patterning is formed in the region of the first main surface of the semiconductor body 2, which is referred to as
• Light exit area is provided.
• the structuring can be done, for example, mechanically and / or chemically.
• the first main surface 25 is
• the contact structure thus has on the semiconductor body 2 side facing a smooth surface, whereby the reflectivity of the contact surface is increased.
• the semiconductor body 2, in particular the active region 23, preferably has an I I I-V compound semiconductor material.
• III IV semiconductor materials are for radiation generation in the ultraviolet (Al x In y Gai- x - y N) over the visible (Al x In y Gai-x- y N, in particular for blue to green radiation, or Al x In y Gai- x - y P, in particular for yellow to red
• the carrier is
• the carrier may be a semiconductor material
• FIGS. 1A and 1B A section of a recess 3 according to the first described in connection with FIGS. 1A and 1B
• Embodiment is in Figure 2 in more schematic
• a lateral extent of the recesses 3 is preferably small compared to the lateral extent of the semiconductor chip 1. In contrast to a large area or even full surface removal of the cover layer 24 cause the recesses 3 no significant impairment of the mechanical stability of the semiconductor chip.
• the lateral extent of the recess 3 is preferably at most 40 ⁇ , more preferably at most 20 ⁇ .
• a side surface 30 of the recess 3 is provided with a
• the coating contains
• a dielectric material such as an oxide, for example silicon oxide or titanium oxide, a nitride, for example silicon nitride, or an oxynitride,
• silicon oxynitride for example, silicon oxynitride
• the refractive index of the coating 35 is preferably smaller than the refractive index of the semiconductor material adjoining the recess 3, so that the largest possible proportion of the radiation emitted in the direction of the contact structure 4 is totally reflected at the side surface 30.
• Deviating from such a coating can also be dispensed with.
• the contact structure 4 on the side surface 30 directly adjoins the side surface 30.
• the contact structure 4 has a connection layer 41, which adjoins the recess 3 in the n-conducting region.
• the connection layer is expediently with respect to
• the contact structure 4 has a reflector layer 42, which is designed to be reflective for the radiation generated in the active region.
• a reflector layer 42 which is designed to be reflective for the radiation generated in the active region.
• silver, aluminum, rhodium, chromium or palladium is suitable for the visible spectral range. In the infrared spectral range, for example, gold is suitable.
• the contact structure 4 has a distribution layer 43.
• the contact surface 40 provided for external electrical contacting is formed.
• the distribution layer 43 can also be dispensed with.
• the contact surface 40 may be formed by means of the reflector layer.
• the contact surface 40 On the contact surface 40, a pattern is formed, which follows the arrangement of the recesses 3.
• the contact surface thus has elevations 44 in the region of the recesses, so that a knob-like structure is created.
• Producing a Drahtbonditati with the contact surface 40 can be done by this knob-like structure a toothing, which can increase the stability of the Drahtbonditati.
• the recesses 3 may also be only partially filled.
• a pattern may be formed on the contact surface 40 in each case recesses 3 are formed in the region of the recesses.
• the pattern of the contact surface 40 is thus by means of
• the described embodiment of the recess 3 and the contact structure 4 can also for the following in the
• Embodiments find application.
• Radiation-emitting semiconductor chip is in Figures 3A and 3B in a schematic plan view or
• the contact structure 4 is arranged in a corner region of the semiconductor chip 1. So can
• a bonding wire causes shading of the radiation exit surface.
• recess may additionally be provided.
• recesses 3 are arranged in the region of the contact surface 40 and the web-like regions, which are provided for electrical contacting of the n-type region.
• Charge carriers are achieved via the n-type region 21 in the active region 23.
• a material for the web-like region 45 is for example a metal, such as gold, palladium, rhodium, silver, chromium or aluminum.
• the cover layer As described in connection with the embodiment shown in FIGS. 1A and 1B, the cover layer
• charge carriers injected via the contact surface 40 are distributed over a large area by means of the distribution layer 43 and injected via the recesses 3 into the n-conducting region.
• the distribution layer may be formed on the semiconductor body 2 over the entire area or essentially over the entire area or may only partially cover the semiconductor body from it.
• distribution layer 43 is particularly suitable for the radiation generated in the active region 23
• a permeable material for example, a transparent conductive oxide, such as zinc oxide (ZnO) or indium tin oxide (ITO).
• ZnO zinc oxide
• ITO indium tin oxide
• the distribution layer 43 may also have a metal layer which is so thin that it is at least translucent for the emitted radiation.
• the cover layer in this embodiment can likewise be provided with a structuring, wherein the
• Structure in plan view of the semiconductor chip 1 can also overlap with the distribution layer.
• An exemplary embodiment of a method for producing a radiation-emitting semiconductor chip is shown schematically in FIGS. 6A to 6D by means of sectional views for various intermediate steps. For a simplified representation is only a part of a
• the semiconductor layer sequence 200 may be provided on a substrate 20, a semiconductor layer sequence 200 is provided.
• the semiconductor layer sequence 200 may be provided on a substrate 20, a semiconductor layer sequence 200.
• Separation method such as MBE or MOVPE, are deposited on the substrate 20.
• the semiconductor layer sequence 200 has a cover layer 24, which adjoins the substrate and the function of a buffer layer and / or a growth-promoting
• an n-type region 21, an active region 23 provided for generating radiation and a p-type region 22 are deposited.
• the cover layer 24 is in the n-type region
• a mirror layer 7 is formed. This can be done for example by sputtering or vapor deposition.
• mirror layer 7 in particular those mentioned in connection with the reflector layer 42 are suitable
• the carrier 5 serves for the mechanical stabilization of
• Main surface 25 of the semiconductor layer sequence recesses 3 is formed. Dry-chemical etching is particularly suitable for particularly small recesses with steep flanks. Alternatively or additionally, however, a wet-chemical etching method can also be used.
• the recesses 3 extend through the cover layer 24 into the n-type region 21.
• the semiconductor layer sequence 200 on the first main surface 25 is provided with a structuring 8.
• the structuring is preferably carried out only in
• Light exit areas are provided.
• areas in which the contact structure is subsequently deposited are free of structuring, such that the first main area in these areas represents a smooth surface.
• the light exit areas can by means of a
• Photolithographic process can be defined.
• the structuring 8 can take place, for example, by means of a mechanical and / or chemical roughening. Regular structuring, for example by means of a photolithographic process, can also be used.
• the deposition of the contact structure 4 can take place, for example, by means of vapor deposition or sputtering on the prefabricated semiconductor layer sequence. Alternatively or additionally, a galvanic deposition method can also be used. By galvanic deposition particularly hard and resistant contact surfaces can be realized.
• the contact structure 4 is preferably multilayered
• the layers may each contain a metal such as palladium, nickel, nickel-phosphorus (Ni: P), copper or gold.
• the galvanic deposition is in the document
• the cover layer 24 may be used in the deposition of the semiconductor layer sequence with regard to high crystal quality for the semiconductor layers, especially for the active area. In the subsequent contacting of the n-type region, this occurs through at least one recess in the cover layer, so that the cover layer has no significant influence on the electrical properties of the semiconductor chip. The cover layer 24 can thus despite a small

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• 2010
  • 2010-07-28 DE DE102010032497A patent/DE102010032497A1/de not_active Withdrawn
• 2011
  • 2011-07-15 WO PCT/EP2011/062158 patent/WO2012013523A1/de active Application Filing
  • 2011-07-15 CN CN2011800367782A patent/CN103026510A/zh active Pending
  • 2011-07-15 KR KR1020137004994A patent/KR20130060272A/ko not_active Application Discontinuation
  • 2011-07-15 US US13/811,847 patent/US8946761B2/en not_active Expired - Fee Related
  • 2011-07-15 EP EP11739023.7A patent/EP2599131A1/de not_active Withdrawn
  • 2011-07-15 JP JP2013521058A patent/JP2013535828A/ja active Pending

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