EP2599131A1

EP2599131A1 - Radation-emitting semi-conductor chip and a method for producing a radiation-emitting semi-conductor chip

Info

Publication number: EP2599131A1
Application number: EP11739023.7A
Authority: EP
Inventors: Dieter Eissler; Andreas PLÖSSL
Original assignee: Osram Opto Semiconductors GmbH
Current assignee: Ams Osram International GmbH
Priority date: 2010-07-28
Filing date: 2011-07-15
Publication date: 2013-06-05
Also published as: US20130214322A1; US8946761B2; KR20130060272A; CN103026510A; WO2012013523A1; DE102010032497A1; JP2013535828A

Abstract

The invention relates to a radiation-emitting semi-conductor chip (1) having a substrate (5) and a semi-conductor body (2) arranged on said substrate and with a semi-conductor layer sequence which comprises an active region (23) provided for producing radiation, an n-type region (21), and a covering layer (24) arranged on a side of the n-type region that faces away from said active region. There is a contact structure (4) arranged on the covering layer for the external electrical contacting of the n-type region, and said covering layer has at least one recess (3) through which said contact structure extends to the n-type region. Moreover, the invention discloses a method for producing a semi-conductor chip.

Description

description

A radiation-emitting semiconductor chip and method for producing a radiation-emitting semiconductor chip

The present application relates to a

radiation-emitting semiconductor chip.

This patent application claims the priority of German patent application 10 2010 032 497.3, the disclosure of which is hereby incorporated by reference.

In the epitaxial deposition of semiconductor layers for radiation-emitting semiconductor chips, for example

Luminescent diodes, are often used to increase the

crystalline quality before deposition for the

optoelectronic properties relevant

Component layers deposit buffer layers and / or epitaxial growth promoting growth layers. These

Layers can complicate the electrical contacting of the component layers due to their comparatively low electrical conductivity.

One task is to use a radiation-emitting

Specify semiconductor chip, which simplifies electrical

is contactable and reliable to produce. Furthermore, a method for producing such

radiation-emitting semiconductor chips can be specified.

These objects are achieved by the subject matter of the independent claims. Further embodiments and

Expediencies are the subject of dependent

Claims. According to one embodiment, a radiation-emitting semiconductor chip has a carrier and one on the carrier

arranged semiconductor body having a

Semiconductor layer sequence on. The semiconductor layer sequence comprises an active region provided for generating radiation, an n-conducting region and a side of the n-conducting region which faces away from the active region on an active region

Area arranged cover layer. On the cover layer, a contact structure for external electrical contacting of the n-type region is arranged and the cover layer has at least one recess through which the

Contact structure extends to the n-type region.

The electrical contacting of the n-type region thus takes place through the recess. Thus, the electrical contact can be made independently of the electrical conductivity of the cover layer. The cover layer can therefore be optimized with regard to other physical properties. In particular, in the production of the radiation-emitting semiconductor chip, the cover layer may be used as an adhesion layer and / or as a buffer layer

be educated. When applying an external electrical voltage during operation of the radiation-emitting

Semiconductor chips can be avoided by means of the recess that an unintentionally high voltage drop occurs on the cover layer and thus its functionality

impaired. The efficiency of radiation production can be increased in this way.

Furthermore, on a large-scale removal of

Cover layer can be omitted. This will be at the

Production of the semiconductor chip reduces the risk of breakage and further increases the mechanical stability of the semiconductor chip.

In other words, by means of contacting the n-type region with a recess in the cover layer, efficient electrical contacting can be achieved while maintaining the optical, electrical and / or

mechanical properties of the cover layer can be achieved.

A surface of the cover layer facing away from the active region preferably forms a first main surface of the cover

Semiconductor body, wherein the semiconductor body in the vertical direction, ie in a direction perpendicular to a

Main extension plane of the semiconductor layers of

Semiconductor body extending direction, is limited by the first main surface.

The contact structure is thus arranged outside the epitaxial semiconductor body on the semiconductor body and serves in the operation of the semiconductor chips of the injection of

Charge carriers in the active region of the semiconductor body.

At least on the side facing the n-conducting region, the covering layer is preferably lattice-matched to the n-conducting region. In the production, the cover layer can thus have the function of a buffer layer and / or a

Growth layer to increase the crystalline quality of the active area meet.

In the production of the semiconductor body, the

Deposition of the cover layer so take place before the deposition of the n-type region. In a preferred embodiment, the cover layer is undoped or has a doping concentration of at most 1 * 10 ¹⁷ cnf ³ . By means of such a cover layer, a high crystal quality can be achieved in a simplified manner in the production of the semiconductor body. Due to the recess in the

Cover layer falls despite the relatively high resistance of a cover layer with such a low

Doping concentration no significant proportion of

Operating voltage on the cover layer from.

In a preferred embodiment, the carrier is arranged on the side of the active region which faces away from the n-conductive region, and furthermore preferably integrally connected to the semiconductor body.

In a cohesive connection, the, preferably prefabricated, connection partners are held together by means of atomic and / or molecular forces. A cohesive connection can for example by means of a

Connecting layer, which may contain, for example, an adhesive or a solder can be achieved. Usually a separation of the connection goes with a destruction of the

Connecting layer and / or at least one of

Associated partner.

The carrier is preferably different from the growth substrate. The carrier therefore does not have the high crystalline

Meet requirements for a growth substrate, but may be in terms of other properties, for example

mechanical stability, thermal conductivity or large-scale and cost-effective availability can be selected. A semiconductor chip in which the growth substrate is completely or at least partially removed or is at least thinned, is also referred to as a thin-film semiconductor chip.

A thin-film semiconductor chip, such as a thin-film light-emitting diode chip, can continue to be used within the scope of the present invention

Registration by at least one of the following

Characteristics distinguish:

at one to a support element, e.g. A mirror layer is applied to the support, turned first first surface of a semiconductor body, which comprises a semiconductor layer sequence with an active region, in particular an epitaxial layer sequence

Bragg mirror integrated in the semiconductor layer sequence, formed, at least part of the in

Semiconductor layer sequence reflected radiation back into this;

the semiconductor layer sequence has a thickness in the range of 20μπι or less, in particular in the range of 10 μπι on; and or

the semiconductor layer sequence contains at least one

Semiconductor layer having at least one surface which has a mixing structure which, in the ideal case, results in an approximately ergodic distribution of the light in the

Semiconductor layer sequence leads, i. she instructs

possibly ergodically stochastic scattering behavior.

A basic principle of a thin-film light-emitting diode chip is described, for example, in I. Schnitzer et al. , Appl. Phys. Lett. 63 (16), 18 October 1993, 2174 - 2176, the

The disclosure content is hereby incorporated by reference into the present application. In a further preferred embodiment is a

Side surface of the at least one recess with a

Coating provided.

The coating may, for example, contain a dielectric material, such as an oxide, a nitride or a

Oxynitride.

The refractive index of the dielectric material is

preferably small relative to the adjacent material of the semiconductor body. The bigger the difference between the

Refractive indices, the greater is the proportion of the radiation that is totally reflected in the direction of the recess on the dielectric material and

subsequently escape from the semiconductor chip.

In a further preferred embodiment, the

Contact structure formed at least partially reflective for the radiation generated in the active region.

In a preferred embodiment, the contact structure has a connection layer adjacent to the n-conducting region and a reflector layer. The material for the

Connection layer is expediently chosen with regard to a good layer adhesion and / or a good contact property to the semiconductor body. For example, the

Connection layer aluminum or titanium included.

The reflector layer preferably has a high, in particular for the radiation generated in the active region

Impact angle largely independent, reflectivity on. The reflector layer preferably contains a metal or a metallic alloy. For example, silver, Aluminum, rhodium, palladium or chromium by a high reflectivity in the visible spectral range. Gold is particularly suitable for the infrared spectral range.

In a further preferred embodiment, the

Contact structure a contact surface for the external

electrical contacting of the semiconductor chip, for example for a wire bond on. Preferably, the contact surface closes the contact structure on the

Semiconductor body facing away in the vertical direction.

In a further preferred embodiment, the at least one recess extends in a plan view of the semiconductor chip at least partially along a border of the

Contact surface. By means of such a recess can

be avoided that radiation generated in the active region in the region of the contact surface of the contact structure

is absorbed. In a component with such

Semiconductor chip in which the semiconductor chip is embedded in a potting, can also be an absorption of radiation, which is scattered in the potting, for example, to radiation converter material or diffuser material, and fed back into the semiconductor chip can be reduced. The total of the semiconductor chip or from the device

Emerging radiation power can therefore be increased.

For example, the at least one recess the

Contact surface frame-shaped, approximately annular in the case of a circular contact surface, circulate.

In a further preferred embodiment, the

Cover layer on a plurality of recesses, in which the contact structure adjacent to the n-type region in each case. By means of the plurality of recesses, a direction running in a lateral direction, that is to say in a direction running along a main extension plane of the semiconductor layer sequence,

uniform and large-area distribution of impressed in the semiconductor chip during operation current can be achieved.

In a preferred embodiment, at least two of the recesses overlap in a plan view of the semiconductor chip with the contact surface. The contact surface thus covers at least two of the recesses. By means of the recesses, the stability of the semiconductor chip during the contacting can be increased in this case. In particular, the

Contact surface a pattern following the recesses

exhibit. As a result of a plastic deformation of the

Wire bonds can do this to better interlock the

Wire bond with the semiconductor chip lead.

For example, by means of the recesses a

Nub structure be formed with elevations and / or depressions. The degree of toothing can be adjusted by means of the spatial density of the recesses and / or by means of a degree of filling of the recesses with the material of the contact structure.

In a further preferred embodiment, the

Contact structure on a distribution layer. The

Distribution layer can be provided to several

Recesses in the cover layer electrically conductive

to connect with each other.

The distribution layer can be full-surface or only

in regions, for example, in at least one region web-like, be formed on the semiconductor body. As a material for the distribution layer, for example, a metal, a semi-metal or a suitable

transparent conductive oxide (TCO).

In a preferred embodiment, the cover layer has a structuring, which in particular for increasing the

Decoupling efficiency of the radiation generated in the semiconductor chip is provided. Further preferably, the structuring is formed only partially on the cover layer. At least in an area in which the contact structure is formed, the cover layer is preferably unstructured. The

Structuring may be formed, for example, in the form of a roughening or a regular structuring.

An unstructured surface of the cover layer in the region of the contact structure can be a particularly simple and

Ensure reliable wire-bonding installation. In particular, comparatively low layer thicknesses are sufficient for the contact structure since the structuring is not achieved by means of a thick layer

Contact structure must be leveled. As a result, material for the deposition of the contact structure can be saved in the production. Furthermore, a contact structure with a smooth surface has a higher reflectivity than a contact structure on a rough surface.

In other words, at least one light outcoupling region may be defined on a radiation exit surface of the semiconductor chip, for example, the first main surface, in which the

Cover layer having the structuring, wherein in a laterally adjacent to the Lichtauskoppelbereich area, the contact structure on an unstructured region of

Cover layer is formed. In a method for producing a plurality of

According to an embodiment, semiconductor chips are provided on a substrate with a semiconductor layer sequence comprising a cover layer, one for generating radiation

having provided active region and an n-type region. The semiconductor layer sequence is attached to a carrier. The substrate is removed. Recesses are formed in the cover layer. On the cover layer, a contact structure is formed, wherein the

Contact structure extends into the recesses. The semiconductor layer sequence with the carrier is separated into a plurality of semiconductor chips, so that each semiconductor chip has at least one of the recesses.

The procedure here does not necessarily have to be in the order of the abovementioned enumeration

Manufacturing steps are performed.

The method is particularly suitable for producing a semiconductor chip described above, so that in

Characteristics described in connection with the semiconductor chip can also be used for the method and

vice versa. With the method, semiconductor chips

are produced, which are characterized by a high crystalline quality of the active region and at the same time by a good contactability of the n-type region.

In a preferred embodiment, the contact structure is deposited by means of a galvanic process. In this way, tough hard contact surfaces, such as for a Drahtbondverbindung, can be produced in a simple and cost-effective manner. Further features, embodiments and expediencies will become apparent from the following description of

Embodiments in conjunction with the figures.

1A and 1B show a first exemplary embodiment of a radiation-emitting semiconductor chip in a schematic top view (FIG. 1A) and associated sectional view (FIG. 1B);

Figure 2 is an enlarged view of a recess according to the first embodiment in a schematic sectional view; Figures 3A and 3B show a second embodiment of a radiation-emitting semiconductor chip in a schematic plan view (Figure 3A) and associated sectional view (Figure 3B). a third embodiment of a radiation-emitting semiconductor chip in a schematic plan view; a fourth embodiment of a radiation-emitting semiconductor chip in a schematic plan view; and FIGS. 6A to 6D show an exemplary embodiment of FIG

Method for producing a semiconductor chip based on intermediate steps shown schematically in sectional view. The same, similar or equivalent elements are provided in the figures with the same reference numerals.

The figures and the proportions of the elements shown in the figures with each other are not as

to scale. Rather, individual elements for better presentation and / or better

Understanding to be exaggeratedly tall.

A first embodiment of a

Radiation-emitting semiconductor chip is shown schematically in FIGS. 1A and 1B. The semiconductor chip 1 comprises a semiconductor body 2 with a semiconductor layer sequence, which forms the semiconductor body. The semiconductor layer sequence is preferably epitaxial, for example deposited by means of MBE or MOCVD.

The semiconductor body 2 is fastened to a carrier 5 by means of a cohesive connection. The carrier is thus different from a growth substrate for the semiconductor layer sequence of the semiconductor body. The semiconductor chip in this embodiment is thus formed as a thin-film semiconductor chip. In the vertical direction, ie in a direction perpendicular to a main plane of extension of the

Semiconductor layers of the semiconductor body 2 extending direction, the semiconductor body extends between a first major surface 25 and a second major surface 26th

The semiconductor layer sequence of the semiconductor body 2 has an active one intended for generating radiation

Region 23, which is disposed between an n-type region 21 and a p-type region 22. On the side facing away from the active region of the n-type region, a cover layer 24 is formed. The cover layer closes off the semiconductor body in the vertical direction.

Furthermore, the cover layer has a low doping concentration in relation to the n-conducting region, for example a doping concentration of at most 1 × 10 ¹⁷ cnf ³ .

Between the semiconductor body 2 and the carrier 5, a mirror layer 7 is arranged, which reflects the radiation generated in the active region 23 and emitted in the direction of the carrier 5 and in the direction of the first main surface 25

deflects. The first main surface 25 thus serves as

Radiation exit surface.

For the production of the cohesive connection is between the semiconductor body 2 and the carrier 5 a

Connecting layer 6 is formed, for example a

Adhesive layer or a solder layer.

On the side of the first main surface 25, the semiconductor body 2 has recesses 3, which extend through the cover layer into the n-conductive region 21 or at least toward the n-conductive region. In the recesses, a contact structure 4 is formed, which is adjacent in the recesses 3 to the n-type region and the external

electrical contacting of the semiconductor chip is provided.

The construction of the recesses 3 will be explained in more detail in connection with FIG.

In a plan view of the semiconductor chip, the contact structure 4 is formed as an example circular. One of the recesses 3 is annular and follows a border 46 of the contact structure.

By means of this recess, the proportion of radiation is reduced, which is generated in the active region and below a contact surface 40 of the contact 4 would be at least partially absorbed.

On the side opposite the contact structure 4 side of the semiconductor chip, a mating contact 49 is formed. By means of the contact structure and the mating contact, charge carriers from different sides can be injected into the active region 23 during operation of the semiconductor chip and can be injected thereunder

Recombining emission of radiation.

The cover layer 24 has a structuring 8. The patterning is formed in the region of the first main surface of the semiconductor body 2, which is referred to as

Light exit area is provided. The structuring can be done, for example, mechanically and / or chemically.

In the region covered by the contact structure in a plan view of the semiconductor chip, the first main surface 25 is

unstructured. The contact structure thus has on the semiconductor body 2 side facing a smooth surface, whereby the reflectivity of the contact surface is increased.

The semiconductor body 2, in particular the active region 23, preferably has an I I I-V compound semiconductor material.

II IV semiconductor materials are for radiation generation in the ultraviolet (Al _x In _y Gai- _x - _y N) over the visible (Al _x In _y Gai-x- _y N, in particular for blue to green radiation, or Al _x In _y Gai- _x - _y P, in particular for yellow to red

Radiation) to the infrared (Al _x In _y Gai- _x - _y As)

Spectral range particularly suitable. In each case 0 <x <1, 0 <y <1 and x + y <1, in particular with x Φ 1, y Φ 1, x Φ 0 and / or y Φ 0. With II IV semiconductor materials, in particular from Material systems mentioned, can continue in the generation of radiation high internal

Quantum efficiencies are achieved.

In the embodiment shown, the

Contacting the p-type region 22 through the substrate 5 through. In this case, the carrier is

expediently carried out electrically conductive.

For example, the carrier may be a semiconductor material

contain, such as silicon, germanium or gallium arsenide.

Deviating but can also find an electrically insulating material for the carrier 5 application, for example sapphire or a ceramic, such as aluminum nitride or

Boron nitride. In this case, the electrical contacting of the p-type region 22, for example, by a

Recess in the carrier 5 or by a recess in the semiconductor body 2, which extends from the first main surface 25 to the p-type region 22, carried out.

A section of a recess 3 according to the first described in connection with FIGS. 1A and 1B

Embodiment is in Figure 2 in more schematic

Section view shown.

A lateral extent of the recesses 3 is preferably small compared to the lateral extent of the semiconductor chip 1. In contrast to a large area or even full surface removal of the cover layer 24 cause the recesses 3 no significant impairment of the mechanical stability of the semiconductor chip.

The lateral extent of the recess 3 is preferably at most 40 μπι, more preferably at most 20 μπι.

A side surface 30 of the recess 3 is provided with a

Coating 35 provided. The coating contains

preferably a dielectric material, such as an oxide, for example silicon oxide or titanium oxide, a nitride, for example silicon nitride, or an oxynitride,

for example, silicon oxynitride.

The refractive index of the coating 35 is preferably smaller than the refractive index of the semiconductor material adjoining the recess 3, so that the largest possible proportion of the radiation emitted in the direction of the contact structure 4 is totally reflected at the side surface 30.

Deviating from such a coating can also be dispensed with. In this case, the contact structure 4 on the side surface 30 directly adjoins the side surface 30.

The contact structure 4 has a connection layer 41, which adjoins the recess 3 in the n-conducting region. The connection layer is expediently with respect to

used with regard to the best possible adhesion to the semiconductor body 2 and a good electrical contact property. For example, aluminum or titanium is suitable. Further materials for connection to an n-type region are in the publication QZ Liu and SS Lau in solid state Electronics Vol. 42, No. 5, pp. 677-691 (1998), the disclosure content of which is hereby explicitly incorporated into the present application.

Furthermore, the contact structure 4 has a reflector layer 42, which is designed to be reflective for the radiation generated in the active region. For example, silver, aluminum, rhodium, chromium or palladium is suitable for the visible spectral range. In the infrared spectral range, for example, gold is suitable.

Furthermore, the contact structure 4 has a distribution layer 43. By means of the distribution layer, the contact surface 40 provided for external electrical contacting is formed.

Deviating from the described embodiment, the distribution layer 43 can also be dispensed with. In this case, the contact surface 40 may be formed by means of the reflector layer.

On the contact surface 40, a pattern is formed, which follows the arrangement of the recesses 3. The contact surface thus has elevations 44 in the region of the recesses, so that a knob-like structure is created. In the

Producing a Drahtbondverbindung with the contact surface 40 can be done by this knob-like structure a toothing, which can increase the stability of the Drahtbondverbindung.

Deviating from the described embodiment, the recesses 3 may also be only partially filled. In this case, a pattern may be formed on the contact surface 40 in each case recesses 3 are formed in the region of the recesses.

The pattern of the contact surface 40 is thus by means of

Filling the recesses and / or adjustable by means of the density of the recesses.

The described embodiment of the recess 3 and the contact structure 4 can also for the following in the

Described in connection with the other figures

Embodiments find application.

A second embodiment of a

Radiation-emitting semiconductor chip is in Figures 3A and 3B in a schematic plan view or

schematic sectional view shown. This second embodiment corresponds essentially to the in

Connection with Figures 1A and 1B described first embodiment.

In contrast, the contact structure 4 is arranged in a corner region of the semiconductor chip 1. So can

be avoided that a bonding wire causes shading of the radiation exit surface.

Furthermore, in contrast to the first exemplary embodiment, no recess is provided which runs along a border of the contact structure 4. Such a frame-like

However, recess may additionally be provided.

A third embodiment of a

Radiation-emitting semiconductor chip is shown schematically in Figure 4 in plan view. This third Embodiment corresponds substantially to the im

Connection with Figure 3 described second

Embodiment. In contrast to this, the

Contact structure 4 in addition to that for the external

electrical contacting provided contact surface 40 web-like areas 45. The contact surface and the

web-like regions form a coherent contact structure.

In plan view of the semiconductor chip 1 45 recesses 3 are arranged in the region of the contact surface 40 and the web-like regions, which are provided for electrical contacting of the n-type region.

By means of the recesses distributed over the semiconductor chip, a large-area and uniform injection of

Charge carriers are achieved via the n-type region 21 in the active region 23.

As a material for the web-like region 45 is for example a metal, such as gold, palladium, rhodium, silver, chromium or aluminum.

As described in connection with the embodiment shown in FIGS. 1A and 1B, the cover layer

be structurally provided in regions (not explicitly shown), wherein the areas of the contact surface 40 and the web-like regions 45 are preferably free of the structuring. This way is between the

Semiconductor body 2 and the contact structure 4 a smooth surface can be realized, which reflects the radiation compared to a roughened surface with an increased efficiency. A fourth embodiment of a

radiation-emitting semiconductor chip is shown in Figure 5 in a schematic plan view. This fourth

Embodiment corresponds substantially to the im

Related to Figure 4 described third

Embodiment. In contrast, the in

Supervision of the semiconductor chip outside the contact surface 40 arranged recesses 3 by means of a

Distribution layer 43 with each other electrically conductive

connected. Thus, during operation of the semiconductor chip, charge carriers injected via the contact surface 40 are distributed over a large area by means of the distribution layer 43 and injected via the recesses 3 into the n-conducting region. The distribution layer may be formed on the semiconductor body 2 over the entire area or essentially over the entire area or may only partially cover the semiconductor body from it.

For the distribution layer 43 is particularly suitable for the radiation generated in the active region 23

permeable material, for example, a transparent conductive oxide, such as zinc oxide (ZnO) or indium tin oxide (ITO).

Alternatively or additionally, the distribution layer 43 may also have a metal layer which is so thin that it is at least translucent for the emitted radiation.

As described in connection with FIGS. 1A and 1B, the cover layer in this embodiment can likewise be provided with a structuring, wherein the

Structure in plan view of the semiconductor chip 1 can also overlap with the distribution layer. An exemplary embodiment of a method for producing a radiation-emitting semiconductor chip is shown schematically in FIGS. 6A to 6D by means of sectional views for various intermediate steps. For a simplified representation is only a part of a

Semiconductor layer sequence shown in the

Production of a semiconductor chip emerges. Of course, in the manufacture of multiple semiconductor chips

be made side by side at the same time.

On a substrate 20, a semiconductor layer sequence 200 is provided. The semiconductor layer sequence 200 may

for example by means of an epitaxial

Separation method, such as MBE or MOVPE, are deposited on the substrate 20.

The semiconductor layer sequence 200 has a cover layer 24, which adjoins the substrate and the function of a buffer layer and / or a growth-promoting

Growth layer fulfilled.

On the cover layer 24, an n-type region 21, an active region 23 provided for generating radiation and a p-type region 22 are deposited.

At least on the side facing the n-type region, the cover layer 24 is in the n-type region

grid-adapted.

As shown in Figure 6B, the

Semiconductor layer sequence on the part of the second main surface 26 remote from the substrate 20 with a carrier 5

cohesively connected. Between the carrier 5 and the Semiconductor layer sequence 200, a mirror layer 7 is formed. This can be done for example by sputtering or vapor deposition.

For the mirror layer 7, in particular those mentioned in connection with the reflector layer 42 are suitable

Materials .

The carrier 5 serves for the mechanical stabilization of

Semiconductor layer sequence 200, so that the substrate 20 is no longer required for this and can be removed. By removing the substrate, the cover layer 24

exposed.

As shown in Figure 6C, be on the part of the first

Main surface 25 of the semiconductor layer sequence recesses 3 is formed. Dry-chemical etching is particularly suitable for particularly small recesses with steep flanks. Alternatively or additionally, however, a wet-chemical etching method can also be used. The recesses 3 extend through the cover layer 24 into the n-type region 21.

Furthermore, the semiconductor layer sequence 200 on the first main surface 25 is provided with a structuring 8. The structuring is preferably carried out only in

Areas of the first main area, which as

Light exit areas are provided. In contrast, areas in which the contact structure is subsequently deposited are free of structuring, such that the first main area in these areas represents a smooth surface. The light exit areas can by means of a

Photolithographic process can be defined.

The structuring 8 can take place, for example, by means of a mechanical and / or chemical roughening. Regular structuring, for example by means of a photolithographic process, can also be used.

The deposition of the contact structure 4 can take place, for example, by means of vapor deposition or sputtering on the prefabricated semiconductor layer sequence. Alternatively or additionally, a galvanic deposition method can also be used. By galvanic deposition particularly hard and resistant contact surfaces can be realized.

The contact structure 4 is preferably multilayered

wherein the layers may each contain a metal such as palladium, nickel, nickel-phosphorus (Ni: P), copper or gold.

The galvanic deposition is in the document

WO2010 / 012267 described, the disclosure of which

In this regard, the present application is incorporated by reference.

A finished semiconductor chip 1, which is produced by separating the composite of the semiconductor layer sequence 200 and carrier 5 into individual semiconductor chips, is shown schematically in a sectional view in FIG. 6D.

In the method described, the cover layer 24 may be used in the deposition of the semiconductor layer sequence with regard to high crystal quality for the semiconductor layers, especially for the active area. In the subsequent contacting of the n-type region, this occurs through at least one recess in the cover layer, so that the cover layer has no significant influence on the electrical properties of the semiconductor chip. The cover layer 24 can thus despite a small

electrical conductivity remain in the semiconductor chip. On a complete or at least large-scale

Area-wise removal of the cover layer before the deposition of the contact structure can thus be dispensed with. The

Risk of breakage is thereby reduced as far as possible.

The invention is not limited by the description with reference to embodiments. Rather, the includes

Invention every new feature as well as every combination of

Features, which includes in particular any combination of features in the claims, even if this feature or this combination itself is not explicitly in the

Claims or the embodiments is given.

Claims

claims

A radiation-emitting semiconductor chip (1) having a carrier (5) and arranged on the carrier

Semiconductor body (2) with a semiconductor layer sequence, which has an active radiation intended for the generation of radiation

Area (23), an n-type region (21) and on a side facing away from the active region (23) side of the n-type region arranged cover layer (24) comprises, wherein on the cover layer (24) has a contact structure (4 ) is arranged for external electrical contacting of the n-type region (21) and the cover layer (24) has at least one recess (3) through which the contact structure (4) extends to the n-type region (21).

2. The radiation-emitting semiconductor chip according to claim 1, wherein the cover layer delimits the semiconductor body in the vertical direction and on the n-type region

facing side is lattice-matched to the n-type region.

3. A radiation-emitting semiconductor chip according to claim 1 or 2,

wherein the cover layer is undoped or a

Doping concentration of at most l * 10 ¹⁷ cnf ³ has.

4. The radiation-emitting semiconductor chip according to one of claims 1 to 3,

wherein the carrier is arranged on the side of the active region which faces away from the n-conducting region and is connected to the semiconductor body in a materially bonded manner.

5. The radiation-emitting semiconductor chip according to one of claims 1 to 4,

wherein a side surface (30) of the at least one recess is provided with a coating (35).

A radiation-emitting semiconductor chip according to claim, the coating containing a dielectric material

7. A radiation-emitting semiconductor chip according to one of claims 1 to 6,

wherein the contact structure comprises a contact surface (40) for a wire bond connection.

8. Radiation-emitting semiconductor chip according to claim 7, wherein the at least one recess in a plan view of the

Semiconductor chip at least partially along a

Outline (46) of the contact surface extends.

9. radiation-emitting semiconductor chip after a

Claims 1 to 8,

wherein the cover layer has a plurality of recesses

in which the contact structure in each case to the

adjacent to the conductive area.

10. A radiation-emitting semiconductor chip according to claim 7 and 9,

wherein at least two of the recesses overlap in plan view of the semiconductor chip with the contact surface.

11. A radiation-emitting semiconductor chip according to claim 10, wherein the contact surface has a pattern following the recesses with elevations (44) and / or recesses.

12. A radiation-emitting semiconductor chip according to one of claims 1 to 11,

wherein the cover layer has a structuring (8) and is unstructured at least in a region in which the contact structure is formed.

13. A method for producing a plurality of

Semiconductor chips (1) comprising the steps of: a) providing a semiconductor layer sequence (200) comprising a cap layer (24), an active region (23) provided for generating radiation, and an n-type conductive layer

Area (21), on a substrate (20);

b) attaching the semiconductor layer sequence (200) to a carrier (5);

c) removing the substrate (20);

d) forming recesses (3) in the cover layer (24); e) forming a contact structure (4) on the cover layer (24), the contact structure (4) extending into the recesses (3);

f) singulating the semiconductor layer sequence (200) with the carrier (5) in the plurality of semiconductor chips (1), so that each semiconductor chip (1) has at least one of the recesses (3).

14. The method according to claim 13,

in which the contact structure by means of a galvanic

Process is deposited.

15. The method according to claim 13 or 14,

wherein a semiconductor chip according to any one of claims 1 to 12 is produced.