DE102019122593A1 - Optoelectronic semiconductor chip - Google Patents

Abstract

An optoelectronic semiconductor chip (1) is specified, comprising
- A semiconductor layer sequence (2) arranged on a carrier (10) and having an active region (20),
- A first electrical connection layer (31) and a second electrical connection layer (32) which are arranged at least in regions between the carrier (10) and the semiconductor layer sequence (2), wherein
- the first electrical connection layer (31) is electrically conductively connected to a first semiconductor region (21),
- the second electrical connection layer (32) is guided through at least one opening (25) in the first semiconductor region (21) and the active region (20) into the second semiconductor region (22) and is connected to it in an electrically conductive manner, and
- An insulation layer (5) between the first electrical connection layer (31) and the second electrical connection layer (32),
- wherein the insulation layer (5) is a reflection-increasing dielectric layer sequence which has alternating first dielectric layers (51) with a refractive index n ₁ and second dielectric layers (52) with a refractive index n ₂ > n ₁ .

Description

The present application relates to an optoelectronic semiconductor chip.

From the pamphlet WO 2012/110364 A1 an optoelectronic semiconductor chip is known in which a first and a second electrical connection layer are arranged between a semiconductor body with an active region provided for generating radiation and a carrier element. In addition to its electrical function, the first electrical connection layer can be provided to reflect radiation generated in the active area and thus to increase the total radiation power emitted. The second electrical connection layer extends through at least one recess in a first semiconductor layer and the active region into a second semiconductor layer.

One object is to specify an optoelectronic semiconductor chip which is distinguished by improved efficiency, in particular by a further improved radiation yield.

This object is achieved by the subject matter of the independent patent claim. Advantageous refinements and developments are the subject of the dependent claims.

In accordance with at least one embodiment, the optoelectronic semiconductor chip has a semiconductor layer sequence which has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active region arranged between the first semiconductor region and the second semiconductor region. The active area is preferably provided for generating radiation. The optoelectronic semiconductor chip can in particular be a light-emitting diode chip. The active area can for example have a pn junction, a double heterostructure, a single quantum well structure (SQW structure) or a multiple quantum well structure (MQW structure). In addition to the active area, the semiconductor layer sequence can comprise further functional layers and functional areas, for example p- or n-doped charge carrier transport layers, undoped or p- or n-doped confinement, cladding or waveguide layers, barrier layers, planarization layers, buffer layers, protective layers and / or Electrodes and combinations thereof.

Depending on the light to be generated, the optoelectronic semiconductor chip can have a semiconductor layer sequence based on different semiconductor material systems. _{A semiconductor layer sequence based on In x} Ga _y Al _1-xy As is suitable for long-wave, infrared to red radiation, for example, a semiconductor _{layer sequence based on In x} Ga _y Al _1-xy P is suitable for red to green radiation and for Short-wave visible radiation, in particular for green to blue radiation, and / or for UV radiation, for example, a semiconductor layer sequence based on In _x Ga _y Al _1-xy N is suitable, where 0 x 1 and 0 y 1 in each case applies.

Furthermore, the optoelectronic semiconductor chip has a carrier on which the semiconductor layer sequence is arranged. The first semiconductor region is preferably a p-type semiconductor region and is arranged on the side of the semiconductor layer sequence facing the carrier. The second semiconductor region is preferably an n-type semiconductor region and is arranged on the side of the semiconductor layer sequence facing away from the carrier. The p-type semiconductor region and the n-type semiconductor region may each include one or more semiconductor layers. It is also not excluded that the p-type semiconductor region and / or the n-type semiconductor region contain one or more undoped layers.

In accordance with at least one embodiment, the optoelectronic semiconductor chip has a first electrical connection layer and a second electrical connection layer, the first electrical connection layer and the second electrical connection layer being arranged in regions between the carrier and the semiconductor layer sequence. The first electrical connection layer is electrically conductively connected to the first semiconductor region and can, for example, directly adjoin the first semiconductor region. The second electrical connection layer is led through at least one opening or preferably a plurality of openings in the first semiconductor region and the active region into the second semiconductor region and in this way is electrically conductively connected to the second semiconductor region.

In accordance with at least one embodiment, the optoelectronic semiconductor chip has an insulation layer which is arranged between the first electrical connection layer and the second electrical connection layer. The insulation layer has the function in particular of preventing an electrical short circuit between the first electrical connection layer and the second electrical connection layer.

In accordance with at least one embodiment, the insulation layer comprises a reflection-increasing dielectric layer sequence which has alternating first dielectric layers with a refractive index n ₁ and second dielectric layers with a refractive index n ₂ > n ₁ . The insulation layer has in the case of the one described herein Optoelectronic semiconductor chip advantageously an additional functionality, namely to reflect radiation from the active region that strikes the insulation layer and in this way to increase the radiation yield of the optoelectronic semiconductor chip. The reflection-increasing effect of the dielectric layer sequence is advantageously achieved by constructive interference at the boundary surfaces of the alternating first layers and second layers. In other words, the reflection-increasing dielectric layer sequence is a dielectric interference layer system. Such a reflection-increasing dielectric layer system based on constructive interference is often referred to as a Bragg mirror.

In accordance with at least one embodiment, the reflection-increasing dielectric layer sequence has a reflection maximum in the emission wavelength range of the radiation emitted by the active region. In particular, the reflection-increasing dielectric layer sequence has a reflection _{maximum at a wavelength λ R, max} and the radiation emitted by the active area has an intensity _{maximum at a wavelength λ I, max} , where λ _{R, max} is matched to λ _{I, max.} The wavelength λ _{R, max} can in particular be set by the materials and layer thicknesses of the first dielectric layers and second dielectric layers. For this purpose, for example, simulation programs known per se to the person skilled in the art can be used to calculate the reflection of thin-film systems. By adapting the reflection maximum of the reflection-increasing dielectric layer sequences to the intensity maximum of the emitted radiation, the radiation yield can be increased. In an advantageous embodiment, | λ _{R, max} - λ _{I, max} | ≤ 30 nm, preferably | λ _{R, max} - λ _{I, max} | ≤ 20 nm, particularly preferably | λ _{R, max} - λ _{I, max} | ≤ 10 nm or even | λ _{R, max} - λ _{I, max} | ≤ 5 nm.

In accordance with at least one embodiment, the first dielectric layers have a refractive index n ₁ <1.7. The refractive index of the first dielectric layers is preferably n ₁ <1.6, particularly preferably n ₁ <1.5. A low refractive index of the first layers has the advantage that a high refractive index difference from the second layers with the higher refractive index can be achieved. This is advantageous in order to achieve a high reflection of the reflection-increasing dielectric layer sequence.

In accordance with at least one embodiment, the second dielectric layers have a refractive index n ₂ > 1.8. The refractive index of the second dielectric layers is preferably n ₂ > 2.0. A high refractive index of the second dielectric layers has the advantage that a high refractive index difference from the first dielectric layers with the lower refractive index can be achieved. This is advantageous in order to achieve a high reflection of the reflection-increasing dielectric layer sequence.

In accordance with at least one embodiment, the first dielectric layers have SiO ₂ . SiO ₂ is characterized in particular by a low refractive index of approximately n ₁ = 1.46.

According to at least one embodiment, the second dielectric layers have Nb ₂ O ₅ , TiO ₂ , HfO ₂ , Ta ₂ O ₅ or ZrO ₂ . The materials mentioned are characterized in particular by a comparatively high refractive index.

In accordance with at least one embodiment, the reflection-increasing dielectric layer sequence comprises at least three layer pairs of the first dielectric layers and second dielectric layers. The reflection-increasing dielectric layer sequence particularly preferably comprises at least four layer pairs of the first dielectric layers and second dielectric layers. With a number of at least three or preferably at least four pairs of layers, a comparatively high reflection can be achieved with a still low manufacturing cost.

In accordance with at least one embodiment, the second electrical connection layer comprises aluminum or titanium or consists thereof. It is possible for the second electrical connection layer to have a plurality of partial layers, with a first partial layer being able to function, for example, as an adhesion promoter layer. The insulation layer embodied as a reflection-increasing dielectric layer sequence can in particular directly adjoin the second electrical connection layer. Viewed from the active area, the second electrical connection layer is arranged at least in some areas behind the insulation layer. When calculating the reflection of the reflection-increasing dielectric layer sequence, the second electrical connection layer can be viewed as a metallic substrate which has aluminum or titanium, for example.

In accordance with at least one embodiment, the first electrical connection layer comprises or consists of silver. Silver is characterized by a particularly high reflectivity in the visible spectral range. As an alternative or in addition, the first connection layer can contain another material with a high reflectivity, in particular a metal such as aluminum, platinum, titanium or palladium.

Further features, refinements and expediencies result from the following Description of the exemplary embodiments in connection with the figures.

• 1 eine schematische Ansicht eines optoelektronischen Halbleiterchips gemäß einem Ausführungsbeispiel in einer Draufsicht,
• 2 eine schematische Ansicht des optoelektronischen Halbleiterchips gemäß 1 in einem Querschnitt entlang der Linie AA',
• 3 eine schematische Detailansicht eines Beispiels der Isolationsschicht in einem Querschnitt,
• 4 eine grafische Darstellung der berechneten Reflektivität R in Abhängigkeit von der Wellenlänge A für zwei Ausführungsbeispiele der Isolationsschicht und ein Vergleichsbeispiel,
• 5 eine schematische Detailansicht eines weiteren Beispiels der Isolationsschicht in einem Querschnitt, und
• 6 eine grafische Darstellung der berechneten Reflektivität R in Abhängigkeit von der Wellenlänge A für ein weiteres Ausführungsbeispiel der Isolationsschicht.

Show it:

• 1 a schematic view of an optoelectronic semiconductor chip according to an embodiment in a top view,
• 2 a schematic view of the optoelectronic semiconductor chip according to 1 in a cross section along the line AA ',
• 3 a schematic detailed view of an example of the insulation layer in a cross section,
• 4th a graphical representation of the calculated reflectivity R as a function of the wavelength A for two exemplary embodiments of the insulation layer and a comparative example,
• 5 a schematic detailed view of a further example of the insulation layer in a cross section, and
• 6th a graphical representation of the calculated reflectivity R as a function of the wavelength A for a further exemplary embodiment of the insulation layer.

Identical or identically acting elements are provided with the same reference symbols in the figures.

The figures and the proportions of the elements shown in the figures are not to be regarded as being to scale. Rather, individual elements can be shown in exaggerated size for better illustration and / or for better understanding.

In the 1 and 2 Fig. 3 is an embodiment of the optoelectronic semiconductor chip 1 shown, which is a light emitting diode chip. The optoelectronic semiconductor chip 1 contains a semiconductor layer sequence 2 that have a first semiconductor area 21st of a first conductivity type and a second semiconductor region 22nd having a second type of conduction. The first semiconductor region is preferred 21st a p-type semiconductor region and the second semiconductor region 22nd an n-type semiconductor region.

Between the first semiconductor area 21st and the second semiconductor region 22nd is an active area 20th arranged. The active area 20th of the optoelectronic semiconductor chip 1 is particularly suitable for emitting radiation. The active area 20th can be designed, for example, as a pn junction, as a double heterostructure, as a single quantum well structure or as a multiple quantum well structure. In the context of the application, the term quantum well structure includes any structure in which charge carriers experience a quantization of their energy states through confinement. In particular, the term quantum well structure does not contain any information about the dimensionality of the quantization. It thus includes, among other things, quantum wells, quantum wires and quantum dots and any combination of these structures.

The semiconductor layer sequence 2 of the semiconductor chip 1 is preferably based on a III-V compound semiconductor material, in particular on a nitride, phosphide or arsenide compound semiconductor material. For example, the semiconductor layer sequence 2 In _x Al _y Ga _1-xy N, In _x Al _y Ga _1-xy P or In _x Al _y Ga _1-xy AS, each with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1, contain. The III-V compound semiconductor material does not necessarily have to have a mathematically exact composition according to one of the above formulas. Rather, it can have one or more dopants and additional components. For the sake of simplicity, however, the above formulas only contain the essential components of the crystal lattice, even if these can be partially replaced by small amounts of other substances.

The semiconductor chip 1 is with a tie layer 7th , which can in particular be a solder layer made of a metal or a metal alloy, a solder layer or an electrically conductive adhesive layer, with a carrier 10 connected. In the embodiment described, the carrier is 10 formed from an electrically conductive material, for example a doped semiconductor material, such as silicon or germanium. The carrier can deviate from this 10 be formed from an electrically insulating material in which electrically conductive vias are formed for electrical contacting. A ceramic, for example aluminum nitride or boron nitride, or a plastic is suitable as the electrically insulating material.

The carrier 10 can from the growth substrate of the semiconductor layer sequence 2 to be different. In particular, the optoelectronic semiconductor chip 1 be a semiconductor chip from which the growth substrate is detached. Such a semiconductor chip is often referred to as a thin-film semiconductor chip. In the production of a thin-film semiconductor chip, the functional semiconductor layer sequence is 2 which, in particular, have a radiation-emitting active layer 20th comprises, first grown epitaxially on a growth substrate, then a new carrier 10 onto the surface of the semiconductor layer sequence lying opposite the growth substrate 2 applied and subsequently separated the growth substrate. Since in particular the growth substrates used for nitride compound semiconductors, for example SiC, sapphire or GaN, are comparatively expensive, this method is particularly advantageous the advantage that the growth substrate can be reused.

The one to the wearer 10 opposite main surface of the semiconductor layer sequence 2 serves as a radiation exit surface 11 of the optoelectronic semiconductor chip 1 and is advantageously free from electrical contact layers. In order to improve the coupling-out of radiation, the radiation exit surface 11 with a coupling-out structure 9 or a roughening. The decoupling structure 9 can be regular or irregular. For example, the structuring can be formed by means of pyramid-shaped or truncated pyramid-shaped depressions or a roughening.

The semiconductor chip 1 a first electrical connection layer 31 and a second electrical connection layer 32. The first electrical connection layer 31 is with the first semiconductor area 21st and the second electrical connection layer 32 with the second semiconductor region 22nd electrically connected.

The first electrical connection layer 31 follows the first semiconductor area 21st at the carrier 10 facing side and can in particular directly to the first semiconductor region 21st the semiconductor layer sequence 2 adjoin. It is also possible that between the first semiconductor region 21st and the first electrical connection layer 31 at least one intermediate layer is arranged, for example a thin adhesion promoter layer or a current spreading layer, for example a layer made of a transparent conductive oxide. The first electrical connection layer 31 contains in particular silver, aluminum or a metal alloy with silver or aluminum. These materials are characterized by high reflectivity in the visible spectral range and good electrical conductivity. The first electrical connection layer 31 has, in addition to its electrical function, the electrical contacting of the first semiconductor area 21st advantageously the function of a mirror layer from the active area 20th towards the wearer 10 emitted radiation to the radiation exit surface 11 reflected back.

The second electrical connection layer 32 is through several openings 25th that extends through the first semiconductor area 21st and the active area 20th extend to the second semiconductor region 22nd electrically connected. The second electrical connection layer 32 functions in the areas in which it is directly connected to the semiconductor layer sequence 2 adjoins, advantageously not only as a contact layer, but also as a reflective layer, the radiation as a radiation exit surface 11 serving second main surface of the semiconductor layer sequence 2 reflected back.

The semiconductor chip has for external electrical contacting 1 a first contact 41 and a second contact 42 on, being the first contact 41 with the first electrical connection layer 31 is connected and the second contact, for example, via the carrier 10 and the tie layer 7th is electrically conductively connected to the second electrical connection layer 32, so that during operation of the semiconductor chip charge carriers from different sides of the active region 20th are injected into these and can recombine there with emission of radiation.

On one of the semiconductor layer sequence 2 facing away from the side is bounded by an encapsulation layer 6th to the first electrical connection layer 31 at. The encapsulation layer 6th has in particular the function of protecting the first electrical connection layer, which has silver, for example, and can also be provided to protect the first electrical connection layer 31 electrically to the first contact 41 to connect. The encapsulation layer 6th can have several sub-layers and / or be structured (not shown). The encapsulation layer 6th can in particular comprise metals such as titanium, platinum, gold, tungsten or metal alloys such as TiW. It is also possible that the encapsulation layer 6th has one or more dielectric layers such as Al ₂ O ₃ , at least in some areas.

In the example shown, the optoelectronic semiconductor chip 1 a transparent dielectric protective layer 8th on. The transparent dielectric protective layer 8th covers in particular the side surfaces and the radiation exit surface 11 serving main area of the semiconductor layer sequence 2 . The semiconductor layer sequence 2 is advantageously completely covered by the transparent protective layer 8th covered. The transparent protective layer 8th is preferably an aluminum oxide layer, in particular an A1 ₂ O ₃ layer, or a silicon oxide layer, in particular an SiO ₂ layer. The transparent encapsulation layer is advantageously deposited by means of atomic layer deposition or as spin-on glass. Such a silicon oxide layer deposited by means of ALD or as spin-on glass advantageously has a high level of resistance to corrosion and the penetration of moisture.

Can be advantageous through the transparent protective layer 8th possibly on the surfaces of the semiconductor layer sequence 2 existing fine cracks are closed. The complete encapsulation of the semiconductor layer sequence 2 is therefore advantageous for the long-term stability of the semiconductor chip.

The transparent protective layer 8th shows next to the one provided with a mesa structure Semiconductor layer sequence 2 an opening in the first contact 41 is arranged over the conductive encapsulation layer 6th with the first electrical contact layer 31 connected is. The first contact 41 can in particular be a bond pad, which is provided for connecting a bond wire. The first contact 41 is preferably off the center of the semiconductor chip 1 arranged, in particular in the region of a corner of the semiconductor chip 1 .

Both the first electrical connection layer 31 and also the second electrical connection layer 32 are at least regionally between one of the carriers 10 facing main surface of the semiconductor layer sequence 2 and the wearer 10 arranged. The first electrical connection layer 31 and the second electrical connection layer 32 are by means of an insulation layer 5 electrically isolated from each other.

The insulation layer 5 , in the 2 is only shown schematically, is in the optoelectronic semiconductor chip 1 a reflection-increasing dielectric layer sequence. Detailed views of possible designs of the insulation layer 5 are in the 3 and 4th shown.

As in 3 shown, has the insulation layer 5 alternating first dielectric layers 51 and second dielectric layers 52 on. The first dielectric layers 51 have a refractive index n ₁ , for which n ₁ <1.7, preferably n ₁ <1.6 and particularly preferably n ₁ <1.5 applies. The second dielectric layers 52 have a refractive index n ₂ > n ₁ , preferably n ₂ > 1.8 and particularly preferably n ₂ > 2. In other words, the first are dielectric layers 51 low refractive index layers and the second dielectric layers 52 high index layers. The first dielectric layers 51 preferably contain or consist of _{SiO 2.} SiO ₂ is characterized by a low refractive index n ₁ = 1.46. Suitable materials for the second dielectric layers 52 are for example Nb ₂ O ₅ , TiO ₂ , HfO ₂ , Ta ₂ O ₅ or ZrO ₂ . These materials are characterized by a high refractive index n ₂ > 2.

It is not necessary to have the dielectric layers 51 , 52 form a periodic layer sequence in which all first dielectric layers 51 and all of the second dielectric layers 52 each have the same layer thickness. Rather, the layer thicknesses of the plurality of first dielectric layers can 51 and second dielectric layers differ from each other. Computer simulations can be used to optimize the layer thicknesses in order to achieve the highest possible reflectivity at a given wavelength or in a given wavelength range.

The optimization is preferably carried out in such a way that the reflection-increasing dielectric layer sequence 5 a reflection maximum at a wavelength λ _{R, max} and the radiation emitted by the active area has an intensity _{maximum at a wavelength λ I, max} , where λ _{R, max is} adapted to λ _{I, max} . The wavelength λ _{R, max} can be determined in particular by the materials and layer thicknesses of the first dielectric layers 51 and second dielectric layers 52 can be set. In an advantageous embodiment, | λ _{R, max} - λ _{I, max} | ≤ 30 nm, preferably | λ _{R, max} - λ _{I, max} | ≤ 20 nm, particularly preferably | λ _{R, max} - λ _{I, max} | ≤ 10 nm or even | λ _{R, max} - λ _{I, max} | ≤ 5 nm.

The insulation layer 5 adjoins the second electrical contact layer 32 on a side facing away from the semiconductor layer sequence. The second electrical contact layer, which contains a metal such as aluminum or titanium, can be viewed as a substrate when calculating the reflectivity of the dielectric layer sequence. On one of the semiconductor layer sequence 2 facing side can be the insulation layer 5 in some areas to the encapsulation layer 6th or the transparent dielectric protective layer 8th adjoin.

In the embodiment of 3 has the insulation layer 5 a reflection-increasing dielectric layer sequence which, starting from the second electrical contact layer 32, has three pairs of layers made up of alternating first dielectric layers 51 and second dielectric layers 52 and another first dielectric layer 51 having. It has been found that even with such a small number of layers 51 , 53 can achieve a high level of reflection. The manufacturing expense for the insulation layer designed as a reflection-increasing dielectric layer sequence 5 is therefore advantageously low.

In a first example the insulation layer 5 according to 3 the second electrical connection layer 32 is a titanium layer, the Insulation layer 5 Starting from the second electrical connection _{layer 32, an SiO 2} layer 51 with a thickness of 67.0 nm, an Nb ₂ O ₅ layer 52 with a thickness of 53.5 nm, an SiO ₂ layer 51 with a thickness of 94 , 6 nm, an Nb ₂ O ₅ layer 52 with a thickness of 60.7 nm, an SiO ₂ layer 51 with a thickness of 92.3 nm, an Nb ₂ O ₅ layer 52 with a thickness of 52, 6 nm and an SiO ₂ layer 51 with a thickness of 94.3 nm. In this example, the layer thicknesses have been optimized by means of a computer simulation in such a way that a maximum reflection is achieved at a wavelength of 450 nm.

In a second example the insulation layer 5 according to 3 the second electrical connection layer 32 is an aluminum layer, the insulation layer 5 Starting from the second electrical connection _{layer 32, an SiO 2} layer 51 with a thickness of 64.4 nm, an Nb ₂ O ₅ layer 52 with a thickness of 57.2 nm, an SiO ₂ layer 51 with a thickness of 90 , 2 nm, an Nb ₂ O ₅ layer 52 with a thickness of 63.4 nm, an SiO ₂ layer 51 with a thickness of 94.9 nm, an Nb ₂ O ₅ layer 52 with a thickness of 52, 3 nm and an SiO ₂ layer 51 with a thickness of 93.0 nm. In this example, the layer thicknesses have been optimized by means of a computer simulation in such a way that a maximum reflection is achieved at a wavelength of 450 nm.

In 4th is the reflection R as a function of the wavelength A for the first example according to 3 (Curve 61), the second example according to 3 (Curve 62) and a comparative example not according to the invention (curve 63) in which the insulation layer is formed _{only by a 600 nm thick SiO 2 layer.} It can be seen that with the insulation layer formed as a reflection-increasing dielectric layer sequence 5 a significantly higher reflection can be achieved than when using an SiO ₂ layer as the insulation layer.

In the embodiment according to 5 has the insulation layer 5 a reflection-increasing dielectric layer sequence, which, starting from the second electrical contact layer 32, has four layer pairs made of alternating first dielectric layers 51 and second dielectric layers 52 and another first dielectric layer 51 having. The manufacturing effort for the insulation layer 5 is still advantageously low in this case.

In one example the insulation layer 5 according to 5 the second electrical connection layer 32 is a titanium layer, the insulation layer 5 Starting from the second electrical connection _{layer 32, an SiO 2} layer 51 with a thickness of 63.0 nm, an Nb ₂ O ₅ layer 52 with a thickness of 54.0 nm, an SiO ₂ layer 51 with a thickness of 90 , 0 nm, an Nb ₂ O ₅ layer 52 with a thickness of 54.0 nm, an SiO ₂ layer 51 with a thickness of 90.0 nm, an Nb ₂ O ₅ layer 52 with a thickness of 54, 0 nm, an SiO ₂ layer 51 with a thickness of 90.0 nm, an Nb ₂ O ₅ layer 52 with a thickness of 54.0 nm and an SiO ₂ layer 51 with a thickness of 90.0 nm .

In 6th is the reflection R as a function of the wavelength A for the example according to 5 shown. It can be seen that with the insulation layer formed as a reflection-increasing dielectric layer sequence 5 A reflection of more than 90% is achieved in the entire wavelength range from 450 nm to 600 nm.

The high reflectivity of the insulation layer designed as a reflection-increasing dielectric layer sequence 5 is in the case of the optoelectronic semiconductor chips described herein 1 advantageous, in particular in the edge regions of the optoelectronic semiconductor chip 1 in which the insulation layer 5 directly under a transparent protective layer 8th can be arranged to achieve an improvement in the radiation yield. From the active area 20th in the direction of the insulation layer 5 emitted radiation or on optical components such as a lens or a conversion element in the direction of the insulation layer 5 reflected radiation is through the insulation layer formed as a reflection-increasing dielectric layer sequence 5 advantageously reflected in the emission direction.

The optoelectronic semiconductor chip described herein 1 is therefore advantageous for all applications in which a high level of brightness and a light image that is as homogeneous as possible is desirable. The optoelectronic semiconductor chip 1 can be used, for example, as a light-emitting diode chip for vehicle headlights, particularly in the automotive sector, in lamps for general lighting or for other special lighting purposes.

The design of the insulation layer as a reflection-increasing dielectric layer sequence also contributes to protecting the optoelectronic semiconductor chip from external influences such as moisture or corrosive substances. The alternating dielectric layers have a good barrier effect, which increases the long-term stability of the optoelectronic semiconductor chip.

The invention is not restricted by the description based on the exemplary embodiments. Rather, the invention encompasses every new feature and every combination of features, which in particular includes every combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or the exemplary embodiments.

List of reference symbols

1

Semiconductor chip

2

Semiconductor layer sequence

20th

active layer

21st

first semiconductor area

22nd

second semiconductor area

25th

breakthrough

31

first electrical connection layer

31

second electrical connection layer

41

first contact

42

second contact

5

electrically insulating layer

51

first layer

52

second layer

6th

Encapsulation layer

7th

Link layer

8th

transparent protective layer

9

Decoupling structure

10

carrier

11

Radiation exit surface

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• WO 2012/110364 A1 [0002]

Claims (14)

Optoelectronic semiconductor chip (1), comprising - a semiconductor layer sequence (2) which has a first semiconductor region (21) of a first conductivity type, a second semiconductor region (22) of a second conductivity type and one between the first semiconductor region (21) and the second semiconductor region (22) arranged active region (20), - a carrier (10) on which the semiconductor layer sequence (2) is arranged, - a first electrical connection layer (31) and a second electrical connection layer (32) which are at least partially between the carrier (10 ) and the semiconductor layer sequence (2) are arranged, wherein - the first electrical connection layer (31) is electrically conductively connected to the first semiconductor region (21), - the second electrical connection layer (32) through at least one opening (25) in the first semiconductor region (21) and the active area (20) in the second semiconductor area (22) and so with the second semiconductor area ch (22) is electrically conductively connected, and - an insulation layer (5) which is arranged between the first electrical connection layer (31) and the second electrical connection layer (32), - the insulation layer (5) being a reflection-increasing dielectric layer sequence, which has alternating first dielectric layers (51) with a refractive index n ₁ and second dielectric layers (52) with a refractive index n ₂ > n ₁ . Optoelectronic semiconductor chip according to Claim 1 wherein the active area (20) is suitable for emitting radiation in an emission wavelength range and the insulation layer (5) has a reflection maximum in the emission wavelength range. Optoelectronic semiconductor chip according to one of the preceding claims, the insulation layer (5) has a reflection _{maximum at a wavelength λ R, max} and radiation emitted by the active region has an intensity _{maximum at a wavelength λ I, max} , and where | λ _{R, max} - λ _{I , max} | ≤ 30 nm. Optoelectronic semiconductor chip according to Claim 3 , where | λ _{R, max} - λ _{I, max} | ≤ 10 nm. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the first dielectric layers (51) have a refractive index n ₁ <1.7. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the first dielectric layers (51) have a refractive index n ₁ <1.5. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the second dielectric layers (52) have a refractive index n ₂ > 1.8. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the second dielectric layers (52) have a refractive index n ₂ > 2. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the first dielectric layers (51) comprise SiO ₂ . Optoelectronic semiconductor chip according to one of the preceding claims, wherein the second dielectric layers (52) have Nb ₂ O _s , TiO ₂ , HfO ₂ , Ta ₂ O _s or ZrO ₂ . Optoelectronic semiconductor chip according to one of the preceding claims, wherein the insulating layer (5) comprises at least three layer pairs of the first dielectric layers (51) and second dielectric layers (52). Optoelectronic semiconductor chip according to one of the preceding claims, wherein the insulating layer (5) comprises at least four layer pairs of the first dielectric layers (51) and second dielectric layers (52). Optoelectronic semiconductor chip according to one of the preceding claims, wherein the second electrical connection layer (32) comprises aluminum or titanium. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the first electrical connection layer (31) comprises silver.

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