DE102017112099A1 - Optoelectronic semiconductor chip - Google Patents

Abstract

An optoelectronic semiconductor chip (100) with a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material is described, wherein the semiconductor layer sequence (10) has a p-type semiconductor region (4), an n-type semiconductor region (2 ) and an active layer (3) arranged between the p-type semiconductor region (4) and the n-type semiconductor region (2),
wherein an n-doped semiconductor layer (21) of the n-type semiconductor region (2) adjoins a p-doped semiconductor layer (11) on a side facing away from the active layer (3), wherein the n-doped semiconductor layer (21) and the P-type semiconductor layer (11) forming a tunnel junction (13), and wherein the p-type semiconductor layer (11) adjacent to an electrical contact layer (12) having a transparent conductive oxide.

Description

The invention relates to an optoelectronic semiconductor chip, in particular a semiconductor chip based on a phosphide compound semiconductor material or arsenide compound semiconductor material.

For optoelectronic semiconductor chips, such as e.g. LED chips is usually arranged between the electrical contact and the light-emitting semiconductor layer sequence a comparatively thick Stromaufweitungsschicht of a semiconductor material having good electrical conductivity in order to achieve the most uniform current flow through the active layer.

It has been found that with comparatively thick current spreading layers a good current spreading layer can be achieved, but on the other hand also a not inconsiderable proportion of the emitted radiation is absorbed. The absorption of a thick current spreading layer is not negligible, in particular, if the emitted radiation is short-waved and / or or aluminum content in the current spreading layer is low.

The invention has for its object to provide an optoelectronic semiconductor chip, which is characterized by an improved current spreading, especially at relatively low absorption.

This object is achieved by an optoelectronic semiconductor chip according to the independent claim. Advantageous embodiments and modifications of the invention are the subject of the dependent claims.

The optoelectronic semiconductor chip contains, according to at least one embodiment, a semiconductor layer sequence based on a phosphide compound semiconductor material or on an arsenide compound semiconductor material. "Based on a phosphide compound semiconductor material" in the present context means that one or more layers of the semiconductor layer sequence, a III-phosphide compound semiconductor material, in particular In _x Al _y Ga _1-xy P with 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≦ 1 or Al _n Ga _{1 -n} As _1-m P _m with 0 ≦ n ≦ 1 and 0 <m ≦ 1. Accordingly, "based on an arsenide compound semiconductor material" in the present context means that one or more layers of the semiconductor layer sequence comprise a III-arsenide compound semiconductor material, for example In _x Al _y Ga _1-xy As with 0 ≦ x ≦ 1, 0 ≦ y ≦ 1 and x + y ≤ 1, preferably Al _y Ga _1-y As with 0 ≤ y ≤ 1. The respective material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, it can have one or more dopants and additional constituents. For the sake of simplicity, however, the above formulas contain only the essential constituents of the crystal lattice (In, Al, Ga, P, As), even though these may be partially replaced by small amounts of other substances.

In particular, the semiconductor layer sequence contains a p-type semiconductor region, an n-type semiconductor region. and an active layer disposed between the p-type semiconductor region and the n-type semiconductor region. The active layer is provided in particular for the emission of electromagnetic radiation. The optoelectronic semiconductor chip may in particular be an LED chip, which is preferably suitable for emitting light in the visible or infrared spectral range. Alternatively, it is also possible that the active layer is a radiation-receiving layer and the optoelectronic semiconductor chip is a detector. The optoelectronic semiconductor chip has in particular exactly one active layer.

The active layer may, for. As a pn junction, as a double heterostructure, as a single-quantum well structure or multiple quantum well structure may be formed. The term quantum well structure encompasses any structure in which charge carriers undergo quantization of their energy states by confinement. In particular, the term quantum well structure does not include information about the dimensionality of the quantization. It thus includes, among other things, quantum wells, quantum wires or quantum dots and any combination of these structures.

According to at least one embodiment of the semiconductor chip, an n-doped semiconductor layer of the n-type semiconductor region adjoins a p-doped semiconductor layer on a side remote from the active layer. The n-doped semiconductor layer and the p-doped semiconductor layer form a tunnel junction. The p-doped semiconductor layer, which forms the tunnel junction with the n-doped semiconductor layer, adjoins an electrical contact layer, wherein the electrical contact layer has a transparent conductive oxide (TCO).

The semiconductor chip described herein differs in particular from the feature of tunnel junction of a conventional optoelectronic semiconductor chip in which the p-type semiconductor region and the n-type semiconductor region surrounding the active layer are each directly connected to electrical contact layers. In particular, the semiconductor chip described here has three different electrical polarities in the order pnp. In this way it is advantageously possible that the Current injection takes place on both sides of the active layer in each case in a p-doped semiconductor material. In particular, a particularly low contact resistance can be achieved at the interface between the p-doped semiconductor layer and the adjacent electrical contact layer made of the transparent conductive oxide. The optoelectronic semiconductor chip makes use in particular of the finding that a lower contact resistance can be achieved when connecting the electrical contact layer made of the transparent conductive oxide to the p-doped semiconductor layer than in the case of applying a transparent conductive oxide directly to the n-type semiconductor region.

In a preferred embodiment of the optoelectronic semiconductor chip, the p-doped semiconductor layer of the tunnel junction Al _y1 Ga _1-y1 As with 0 ≤ y1 ≤ 0.3. It has been found that when arranging the electrical contact layer of the transparent conductive oxide on Al _{y1 Ga1 -y1} As with 0 ≤ y1 ≤ 0.3 a particularly low contact resistance is achieved.

According to an advantageous embodiment of the optoelectronic semiconductor chip, the p-doped semiconductor layer has carbon as dopant. The use of carbon as a dopant can advantageously achieve high dopant concentrations.

By means of a high dopant concentration, a particularly good electrical contact between the p-doped semiconductor layer and the electrical contact layer is produced. According to an advantageous embodiment, the dopant concentration in the p-doped semiconductor layer is at least 1 * 10 ¹⁹ cm ^-3 , more preferably at least 1 * 10 ²⁰ cm ^-3 . In particular, the dopant concentration may have a value between 1 * 10 ¹⁹ cm ^-3 and 1 * 10 ²¹ cm ^-3 .

In a preferred embodiment of the optoelectronic semiconductor chip, the thickness of the p-doped semiconductor layer is between 3 nm and 50 nm. Such a small thickness of the p-doped semiconductor layer has the particular advantage that the absorption in the p-doped semiconductor layer is particularly low.

According to a preferred embodiment of the optoelectronic semiconductor _chip , the n-doped semiconductor _{layer of} the tunnel junction Al _y2 Ga _1-y2 As with 0 ≤ y2 ≤ 0.3. Apart from the different dopant, the n-doped semiconductor layer may in particular comprise the same semiconductor material as the p-doped semiconductor layer.

The n-doped semiconductor layer preferably comprises silicon or tellurium as dopant. The dopant concentration in the n-doped semiconductor layer is preferably at least 5 × 10 ¹⁷ cm ^-3 .

According to at least one embodiment, the electrical contact layer of the optoelectronic semiconductor chip comprises indium tin oxide (ITO), indium zinc oxide (IZO) or zinc oxide (ZnO). These materials are advantageously transparent and have good electrical conductivity. The electrical contact layer advantageously acts simultaneously as a current spreading layer. Particularly preferably, the electrical contact layer has ITO.

The thickness of the electrical contact layer is preferably between 1 nm and 200 nm, particularly preferably between 30 nm and 60 nm. In this thickness range, good electrical conductivity is achieved with only slight absorption in the electrical contact layer.

In a preferred embodiment of the optoelectronic semiconductor chip, the contact resistance between the p-doped semiconductor layer and the electrical contact layer made of the transparent conductive oxide is less than 1 * 10 ^-3 Ωcm ² .

According to an advantageous embodiment of the optoelectronic semiconductor chip, the n-type semiconductor region is less than 5 microns thick. Preferably, the thickness of the n-type semiconductor region is less than 1 .mu.m, and more preferably less than 500 nm. The n-type semiconductor region may be comparatively thin in the optoelectronic semiconductor chip described herein because of the transparent conductive oxide and adjacent dielectric contact layer P-doped semiconductor layer is already achieved a good current expansion. Therefore, a comparatively thick current spreading layer in the n-type semiconductor region which is generally used in conventional optoelectronic semiconductor chips can advantageously be dispensed with.

In a preferred embodiment of the optoelectronic semiconductor chip, the n-type semiconductor region faces a radiation exit surface of the optoelectronic semiconductor chip, and the p-type semiconductor region faces a carrier substrate of the optoelectronic semiconductor chip.

In a preferred embodiment, the optoelectronic semiconductor chip has no growth substrate. The optoelectronic semiconductor chip is preferably a so-called thin-film light-emitting diode chip, in which a growth substrate used for growing the semiconductor layer sequence is detached from the optoelectronic semiconductor chip. The original growth substrate may be of the n-type in particular Semiconductor region of the semiconductor layer sequence to be detached. On the side of the p-type semiconductor region opposite the original growth substrate, the optoelectronic semiconductor chip is preferably connected to a carrier substrate, for example by means of a solder connection. In this case, the carrier substrate is different from a growth substrate of the semiconductor layer sequence and has, for example, silicon, molybdenum, germanium or a ceramic. In contrast to conventional LEDs, in which usually the n-type semiconductor region faces the substrate and the p-type semiconductor region of the radiation exit surface, in the embodiment as a thin-film light-emitting diode chip, the p-type semiconductor region is the carrier substrate and the n-type semiconductor region facing the radiation exit surface.

In an optoelectronic semiconductor chip without growth substrate, in which the p-type semiconductor region faces a carrier substrate, the contacting of the n-type semiconductor region described herein by means of a p-doped layer which forms a tunnel junction and a subsequent electrical contact layer of a transparent conductive Oxide particularly advantageous. In particular, a lower contact resistance can be achieved than if the n-type semiconductor region would directly adjoin an electrical contact layer made of a transparent conductive oxide.

• 1 zeigt eine schematische Darstellung eines Querschnitts durch einen optoelektronischen Halbleiterchip gemäß einem Ausführungsbeispiel.

The invention will be described below with reference to an embodiment in connection with the 1 explained in more detail.

• 1 shows a schematic representation of a cross section through an optoelectronic semiconductor chip according to an embodiment.

The sizes of the individual elements and the size ratios of the elements with each other are not to be regarded as true to scale.

The in 1 illustrated optoelectronic semiconductor chip 100 contains a semiconductor layer sequence 10 , which is an n-type semiconductor region 2 and a p-type semiconductor region 4 having. Between the n-type semiconductor region 2 and the p-type semiconductor region 4 is an active layer 3 arranged. The optoelectronic semiconductor chip is in particular an LED chip, which is provided, for example, for generating electromagnetic radiation in the visible or near infrared spectral range.

The semiconductor layer sequence 10 is preferably based on a phosphide compound semiconductor material or on an arsenide compound semiconductor material. In particular, one or more layers of the semiconductor layer sequence 10 a III-phosphide compound semiconductor material, for example, In _x Al _y Ga _1-xy P where 0≤x≤1, 0≤y≤1 and x + y≤1. Alternatively or additionally, the semiconductor layer sequence may comprise one or more layers comprising In _x Al _y Ga _1-xy As where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1, or preferably Al _y Ga _1-y As include with 0 ≤ y ≤ 1.

The active layer 3 is in the embodiment as a quantum well structure 31 . 32 designed, preferably as a multi-quantum well structure. The quantum well structure has, for example, a periodic arrangement of alternating quantum well layers 31 and barrier layers 32 on. The quantum well structure has a number N Periods on, where P for example, between 1 and 120. The quantum well layers provided for generating radiation 31 have an electronic band gap E _QW that is less than an electronic band gap E _{B of} the barrier layers 32 ,

The p-type semiconductor region 4 may contain one or more p-doped semiconductor layers. However, it is not excluded that the p-type Halbeiterbereich 4 contains one or more undoped layers. Accordingly, the n-type semiconductor region 2 one or more n-doped layers 21 . 22 and optionally one or more undoped layers.

In the embodiment of the optoelectronic semiconductor chip shown here 100 it is a so-called thin-film LED, in which the semiconductor layer sequence 10 detached from its original growth substrate. The original growth substrate is of the n-type semiconductor region 2 detached, in this embodiment, the radiation exit surface 14 of the optoelectronic semiconductor chip 100 is facing. On the opposite side of the original growth substrate is the optoelectronic semiconductor chip 100 with at least one compound layer 7 such as a solder layer on a carrier substrate 1 applied. From the active layer 3 Thus, the p-type semiconductor region is seen 4 the carrier substrate 1 facing. The carrier substrate 1 is unlike that for epitaxially growing the semiconductor layer sequence 10 used growth substrate. The carrier substrate 1 For example, it may comprise a semiconductor material such as silicon, germanium or molybdenum or a ceramic.

The p-type semiconductor region 4 partially adjacent to a mirror layer 6 at. The mirror layer 6 is intended to be that of the active zone 3 in the direction of the carrier substrate 1 emitted radiation to the opposite radiation exit surface 14 on the surface of the n-type Semiconductor region 2 to reflect. The mirror layer 6 may in particular comprise or consist of silver or gold. Silver and gold are characterized by a high reflectivity.

In the embodiment shown here is between the p-type semiconductor region 4 and the mirror layer 6 partially a dielectric layer 5 arranged, which may be in particular a silicon oxide layer. Due to the comparatively low refractive index of the dielectric material of the dielectric layer 5 For example, SiO ₂ , the dielectric layer 5 a total reflection of a part of the in the direction of the carrier substrate 1 emitted radiation to the radiation exit surface 14 effect. The reflective effect of the metallic mirror layer 6 is therefore due to the dielectric layer 5 advantageous further reinforced. As the dielectric layer 5 is not electrically conductive, is the mirror layer 6 through one or more openings in the dielectric layer 5 to the p-type semiconductor region 4 connected.

For electrical contacting of the optoelectronic semiconductor chip 100 are a first connection layer 8th and a second terminal layer 9 intended. The first connection layer 8th for electrical contacting of the n-side, for example, on a portion of the radiation exit surface 14 be arranged. The second connection layer 9 For example, at the back of the carrier substrate 1 be arranged when an electrically conductive carrier substrate 1 is used.

The first connection layer 8th is advantageously not directly in the optoelectronic semiconductor chip on the n-type semiconductor region 2 applied. Rather, the n-type semiconductor region 2 an n-doped semiconductor layer 21 on, on to one of the active layer 3 side facing away from a p-doped semiconductor layer 11 borders. The p-doped semiconductor layer 11 forms with the n-doped semiconductor layer 21 a tunnel crossing 13 out.

Through the tunnel crossing 13 At the n-side of the optoelectronic semiconductor chip, it is possible to change the polarity of the semiconductor material to the p-type. In order to achieve a high electrical conductivity in the region of the tunnel junction, it is advantageous if the p-doped semiconductor layer 11 has a high dopant concentration. The dopant concentration in the p-doped semiconductor layer 11 is preferably at least 1 * 10 ¹⁹ cm ^-3 , more preferably at least 1 * 10 ²⁰ cm ^-3 .

The n-doped semiconductor layer 21 and the p-type semiconductor layer 11 passing the tunnel crossing 13 preferably each comprise AlGaAs or GaAs. In particular, the n-doped semiconductor layer 21 Al _{y2 Ga1 -y2} As with 0 ≦ y2 ≦ 0.3 and the p-doped semiconductor layer 11 Al _y1 Ga _1-y1 As with 0 ≤ y1 ≤ 0.3. Here, y2 = y1 or y2 ≠ y1.

To the p-doped semiconductor layer 11 adjoins an electrical contact layer 12 which has a transparent conductive oxide. The electrical contact layer 12 is preferably an ITO layer. A transparent conductive oxide, in particular ITO, is distinguished by high transparency and good electrical conductivity. The electrical contact layer 12 from the transparent conductive oxide can be over the entire surface or structured on the p-doped semiconductor layer 11 be applied.

It has been found that an electrical contact layer 12 of a transparent conductive oxide such as in particular ITO with a particularly low contact resistance to a p-doped semiconductor layer 11 , which in particular has Al _y1 Ga _1-y1 As with 0 ≦ y1 <0.3, can be connected. In particular, by the arrangement of the electrical contact layer 12 from the transparent conductive oxide on the p-type semiconductor layer 11 a lower contact resistance can be achieved than would be the case with an arrangement of the transparent conductive oxide on an n-doped semiconductor layer. The contact resistance between the electrical contact layer 12 and the p-type semiconductor layer 11 is preferably less than 1 * 10 ^-3 Ωcm ² .

On a portion of the electrical contact layer 12 is the first connection layer 8th arranged, wherein the first connection layer 8th preferably contains a metal such as Au. The first connection layer 8th In particular, it can be designed as a bonding pad and, in one embodiment, can have one or more contact webs (not shown) originating from the bond pad.

The contacting of the n-side of the optoelectronic semiconductor chip 100 takes place by means of the p-doped semiconductor layer 11 passing the tunnel crossing 13 and thus the polarity of the n-type semiconductor material changes to the p-type, the subsequent electrical contact layer 12 of the transparent conductive oxide and the subsequent first terminal layer 8th in particular comprising a metal and, for example, can be connected to a bonding wire.

An advantage of this type of contacting is in particular that by means of the electrical contact layer 12 of the transparent conductive oxide and the p-type semiconductor layer 11 a high transverse conductivity and thus a good flow expansion is achieved with low layer thicknesses. The thickness of the electrical contact layer 12 of the transparent conductive oxide is advantageously between 1 nm and 200 nm and preferably between 30 nm and 60 nm. The p-doped semiconductor layer 11 is preferably between 3 nm and 50 nm thick.

In that already in the electrical contact layer 12 of the transparent conductive oxide and the p-type semiconductor layer 11 a good current expansion takes place, the thickness of the n-type semiconductor region 2 be advantageous low. The thickness of the n-type semiconductor region 2 is advantageously less than 5 .mu.m, preferably less than 1 .mu.m and more preferably less than 500 nm. In particular, may be a Stromaufweitungsschicht of a semiconductor material in the n-type semiconductor region 2 be waived. The comparatively small thicknesses of above the active layer 3 arranged n-type semiconductor region 2 as well as the layers 11 . 12 has the advantage that the absorption is low.

Alternatively to the in 1 In the embodiment shown, the optoelectronic semiconductor chip can be embodied with reversed polarity, in which case the n-type semiconductor region 2 the carrier substrate and the p-type semiconductor region 4 the radiation exit surface 14 is facing. In this embodiment, for example, starting from a carrier substrate 1 the electrical contact layer 12 that of the p-doped semiconductor layer 21 and the n-type semiconductor layer formed tunnel junction 13 , the n-type semiconductor region 2 , the active layer 3 and the p-type semiconductor region 4 each other.

The invention is not limited by the description with reference to the embodiments. Rather, the invention encompasses any novel feature as well as any combination of features, which in particular includes any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

1

carrier substrate

2

n-type semiconductor region

3

active layer

4

p-type semiconductor region

5

dielectric layer

6

mirror layer

7

link layer

8th

first connection layer

9

second connection layer

10

Semiconductor layer sequence

11

p-doped semiconductor layer

12

electrical contact layer

13

Tunnel junction

14

Radiation exit area

21

n-doped semiconductor layer

22

n-doped semiconductor layer

31

Quantum well layer

32

barrier layer

100

optoelectronic semiconductor chip

Claims (14)

An optoelectronic semiconductor chip (100) having a semiconductor layer sequence (10) based on a phosphide compound semiconductor material or arsenide compound semiconductor material, the semiconductor layer sequence (10) having a p-type semiconductor region (4), an n-type semiconductor region (2) and an inter-cell the active layer (3) arranged in the p-type semiconductor region (4) and the n-type semiconductor region (2), wherein an n-doped semiconductor layer (21) of the n-type semiconductor region (2) is formed on one of the active layer (3 ) facing away from a p-doped semiconductor layer (11), wherein the n-doped semiconductor layer (21) and the p-doped semiconductor layer (11) form a tunnel junction (13), and wherein the p-doped semiconductor layer (11) an electrical contact layer (12) is adjacent, having a transparent conductive oxide. Optoelectronic semiconductor chip after Claim 1 wherein the p-type semiconductor layer (11) has Al _y1 Ga _1-y1 As with 0 ≦ y1 ≦ 0.3. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the p-doped semiconductor layer (11) is doped with carbon. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the p-doped semiconductor layer (11) has a dopant concentration of at least 1 * 10 ¹⁹ cm ^-3 . Optoelectronic semiconductor chip according to one of the preceding claims, wherein the p-doped semiconductor layer (11) has a dopant concentration of at least 1 * 10 ²⁰ cm ^-3 . Optoelectronic semiconductor chip according to one of the preceding claims, wherein the p-doped semiconductor layer (11) is between 3 nm and 50 nm thick. Optoelectronic semiconductor _chip according to one of the preceding claims, wherein the n-doped semiconductor _layer (21) Al _y2 Ga _1-y2 As with 0 ≤ y2 ≤ 0.3. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the n-doped semiconductor layer (21) is doped with silicon or tellurium. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the electrical contact layer (12) comprises ITO. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the electrical contact layer (12) is between 1 nm and 200 nm thick. Optoelectronic semiconductor chip according to one of the preceding claims, wherein a contact resistance between the p-doped semiconductor layer (11) and the electrical contact layer (12) is less than 1 * 10 ^-3 Ωcm ² . Optoelectronic semiconductor chip according to one of the preceding claims, wherein the n-type semiconductor region (2) is less than 5 microns thick. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the n-type semiconductor region (2) is less than 1 micron thick. An optoelectronic semiconductor chip according to any one of the preceding claims, wherein the n-type semiconductor region (2) is less than 500 nm thick.

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