EP2589072A2

EP2589072A2 - Interposer and method for producing holes in an interposer

Info

Publication number: EP2589072A2
Application number: EP11730223.2A
Authority: EP
Inventors: Oliver Jackl
Original assignee: Schott AG
Current assignee: Schott AG
Priority date: 2010-07-02
Filing date: 2011-07-04
Publication date: 2013-05-08
Also published as: JP6841607B2; DE102010025966A1; JP2019041133A; US20200045817A1; JP2016195270A; KR20160013259A; KR101598260B1; JP2013531380A; CN102971838B; US20130210245A1; US11744015B2; WO2012000685A2; KR20130040224A; WO2012000685A3; DE102010025966B4; CN102971838A; JP6208010B2; KR101726982B1

Abstract

Interposer for electrical connection between a CPU chip and a circuit board. A board-shaped base substrate (1) composed of glass has a coefficient of thermal expansion in the range of between 3.1 · 10^-6 and 3.4 · 10^-6 and holes (12) in a number that is in the range of between 10 and 10,000 cm^-2. There are holes (12) having diameters which can be in the range of between 20 μm and 200 μm. Conductor tracks (13) run on one board side, said conductor tracks in each case extending right into the holes (12) and through the latter to the other board side in order to form connection points for the chip.

Description

Interposer and method of making holes in an interposer

Field of the invention

The invention relates to interposer for electrically connecting the terminals of a CPU chip with a

Circuit board, further to methods that are used in a critical manufacturing step of the interposer.

Background of the Invention A CPU chip as a processor core typically has several hundreds of contact points spaced close to each other on its underside over a relatively small area. Because of this close spacing, these contact points can not be mounted directly onto a circuit board, the so-called motherboard. It is therefore a

Applied intermediate part, with which the

Contacting basis can be broadened. When

Intermediate part is often used an encapsulated with epoxy material glass fiber mat, which is provided with a number of holes. On the surface of the glass fiber mat run tracks that lead into the respective holes to fill them, and on the other side of the

Glass fiber mat up to the connection contacts of the

Lead processor cores. To accomplish this, both around the processor core and between the

Processor core and the glass fiber mat applied a backfill (underfill), which protects the lines and

CONFIRMATION COPY the processor core and the glass fiber mat mechanically

connects with each other. The processor core and the

Glass fiber mat, however, have different

Thermal expansions. Thus, the glass fiber mat has a coefficient of expansion of 15 to 17 × 10 ^-6 , while the silicon-based core processor has one

Thermal expansion factor of 3.2 to 3.3 x 10 ^"6. Thus, when heating occurs, there are differential expansions between the core processor and the

Glass fiber mat and thus to mechanical stresses

between these two components. This can happen

detrimental to the contact connections, especially if the two components are not connected to each other Then the contact points can break easily.

The use of the glass fiber mat has a further drawback associated with the mechanical drilling of the holes in the glass fiber mat. Of the

Hole diameter is limited to 250 to 450 m.

Another possibility for constructing and producing connecting structures which could be used in the manner of interposers is shown in WO 02/058135 A2. Wafer technology is applied with the production of holes and trenches in dielectric material,

For example, silica, and filling the holes and trenches with conductive layers. However, this method of making contact connections is very expensive. A similar technology is described in DE 103 01 291 B3

taught. It recesses are etched in substrates and filled by tracks made of metal, and also

Pass contacts through holes. This technique is complicated and expensive.

The US 2002/0180015 Al shows a module for a variety of chips, the semiconductor devices and a

Wiring substrate for applying the

Semiconductor devices has. The wiring substrate comprises a glass substrate having holes through

Sandblast treatment were formed. On the surface of the glass substrate, a wiring layer is formed.

Further, the glass substrate has a wiring and an insulation layer. It is aimed at the

To select the coefficient of thermal expansion of the glass substrate in the vicinity of the coefficient of silicon.

US 5,216,207 shows multi-layer ceramic circuit boards with conductors of silver. The layers are baked at low temperatures. The boards have a thermal expansion coefficient close to that of silicon.

US 2009/0321114 A1 shows a substrate unit for electrical testing with a multilayer

Ceramic substrate. Although the materials used have a coefficient of thermal expansion in the vicinity of

corresponding value of your invention, but are not pure glasses. US 7,550,321 Bl shows a substrate with a

Thermal expansion coefficient, which has a gradient in the thickness direction. The article "Femtosecond laser-assisted three-dimensional microfabrication in silica" from Optics Letters, Vol. 26, no. 5, March 1, 2001, pages 277 to 279 describes direct three-dimensional microproduction in one

Silicate glass. The production process takes place in two

Steps. First, the intended patterns by means of focused femtosecond laser pulses in the glass

mapped out. Subsequently, these patterns are etched.

General description of the invention

The invention has for its object to provide an interposer for electrical connection between a CPU chip and a circuit board, which is economical to manufacture, thereby enabling the production of micro holes in the order of 20 m and 200 μπι hole diameter and the interposer body similar thermal expansion to that of the CPU chip material.

With the new interposer, the following requirements should be fulfilled:

Many small holes (10 to 10,000) should be accommodated per interposer with close tolerances of the holes to each other. In this case, a hole spacing down to 30 μιη must be maintained. The hole diameter should be able to reach down to a size of 20 m. The

Ratio between thickness of the interposer and

Hole diameter, the so-called aspect, should be between 1 and 10. The center distance of the holes should be between 120 pm and 400 μπ \. The hole shape should be at the hole inlet and outlet conical or

crater-shaped, but in the Lochlaibungsmitte be as cylindrical as possible. The hole walls should be smooth (fire polished). If necessary, also a bead of a maximum of 5 mm bead height around the edge of the hole around arise.

The interposer according to the invention is characterized in that its plate-shaped base substrate is made of glass whose thermal expansion coefficient is in the range between 3.1 x 10 ^"6 and 3.4 x 10 ^{~. 6} chip boards based on silicon have a coefficient of expansion between 3.2 x 10 ^"6 and 3.3 x 10 ^{" 6.} Between interposer and CPU chip, therefore, no great mechanical stresses are to be expected due to different thermal expansion behavior

based.

The number of holes in the interposer will be after the

selected requirements and may be up to 10,000 holes per cm ² . A typical number of holes is in the range of 1000 to 3000. The hole center distance of the holes is in the range of 50 \ im and 700 μιη. In order to meet the requirements of miniaturization of components, there are holes whose diameter is in the range between 20 m and 200 m. To make the electrical connection between the CPU chip and its circuit board,

Conductors run on one of the plate sides of the interposer into and through the holes to form connection points for the CPU chip. The glass of the base substrate should contain an alkali content of less than 700 ppm. Such glass has a low thermal expansion coefficient as required and due to the high dielectric value very good signal insulating properties. Furthermore, the risk of contamination of silicon processors with alkalis is largely avoided.

For reasons of environmental protection contains the

Glass composition an arsenic or antimony content of less than 50 ppm. Interposer have a plate thickness that is below 1 mm, but not 30 μπι below. The number of holes of an interposer is chosen according to the needs and is of the order of 1000 to 3000 holes / cm ² . The invention is intended to interposer with

Micro holes below 100 μπι offer on the market. The holes are therefore packed tight, the center distance of the holes in the range between 150 μπι and 400 μιη can be. The hole edge distance of the holes but should not fall below 30 μιη. The holes need not all have the same diameter, it is possible that holes of different diameter in the plate-shaped

Base substrate are present. The ratio of

Glass plate thickness to the hole diameter, the so-called

Aspect can be selected in a wide range of 0.1 to 25, with an aspect ratio of 1 to 10 being preferred. The holes are generally slim cylindrically shaped, but can be at the hole entrance and

Hole exit be equipped with rounded-broken edges.

To accurately position holes whose diameter can be in the range between 20 μπι and 200 μιτι operated you get focused laser pulses in one

Wavelength range of the transparency of the glass, so that the laser rays penetrate into the glass and are not already absorbed in the outer layers of the glass. Laser radiation of very high radiation intensity is used to cause local, athermal destruction of the glass along filamentous channels. These

filamentous channels are then widened to the desired diameter of the holes, taking one

Serve dielectric breakthroughs, the

electrothermal heating and evaporation of the

Lead hole material, and / or the filamentous channels are widened by the supply of reactive gases. The holes provided can also be exactly marked by HF coupling material, which is printed dot-shaped on the base substrate. Such

Marked points are heated by RF energy in order to close the holes

Breakthrough resistance to electrical high voltage to lower and finally in these places too

reach dielectric breakthroughs. The

Breakthrough sites can be caused by supplied etching gas

be widened.

The production of the conductor tracks on the plate-shaped glass substrate and through the holes is carried out according to known process patterns and need not be further described here. Short description of the drawing

Embodiments of the invention will be described with reference to FIGS

Drawing described. Showing:

Fig. 1 is a schematic representation of a production of an interposer in longitudinal section and

Fig. 2 shows a second production. Detailed description

In a first method step, holes 10 on a plate-shaped glass substrate 1 are marked by focused laser pulses 41 emanating from an arrangement 4 of lasers 40. The radiation intensity of these lasers is so strong that local, athermal destruction occurs along a filamentary channel 11 in the glass.

In a second process step, the

filamentous channels 11 expanded into holes 12. It is possible to use opposing electrodes 6 and 7, which are supplied with high-voltage energy, which leads to dielectric breakthroughs through the glass substrate along the filamentary channels 11. These breakthroughs expand by electrothermal heating and

Evaporation of hole material until the process when reaching the desired hole diameter by switching off the

Energy supply is stopped. Alternatively or additionally, you can also the

dilate filamentous channels 11 by reactive gases, as shown by nozzles 20, 30, which direct the gas to the Lochungsstellen 10.

In the next process step, conductor paths 13 are applied to the perforation points 10 on the upper side of the glass plate 1, and the holes 12 are filled with conductive material 14 to complete on the underside of the plate the connections to the contact points of a CPU chip or the like. (For mounting on the

Motherboard will turn the glass plate 1.)

Fig. 2 shows a further possibility of the production of microholes. The holes 10 are marked by precisely printed RF coupling material. At these points 10 radio frequency energy is coupled by means of electrodes 2, 3, so that the coupling points themselves and the glass material between the top side

Warming coupling points and the bottom coupling points, resulting in a reduction of the

Dielectric strength of the material leads. When high voltage is applied, dielectric breakdowns occur along narrow channels 11. By further supplying high voltage energy, these narrow channels 11 can be widened to the size of the holes 12.

But it is also possible the expansion of the narrow

Channels 11 due to dielectric breakthroughs

to make reactive gas which is supplied through nozzles 20, 30.

Finally, conduction paths 13 are applied to the holes 12 on the top of the glass substrate, and the Holes are filled with conductive material 14 in order to produce, with turned glass plate 1, the connections for the CPU chip. It should be noted that interposers do not need to be made individually but glass substrate plates for one

Variety of interposers can be processed by cutting the large format glass substrate plates to recover the individual interposers. Formats of glass substrate plates with edge lengths from 0.2 m to 3 m (or smaller) can be processed.

Round disc formats can be up to 1 m in dimension

exhibit . embodiments

From conventional, apart from inevitable impurities substantially alkali-free raw materials glasses were melted in 1620 ° C in Pt / Ir crucibles. The melt was refined for one and a half hours at this temperature, then poured into inductive platinum crucible and stirred for 30 minutes at 1550 ° C for homogenization. The table shows fifteen examples of suitable glasses with their compositions (in% by weight based on oxide) and their most important properties. The refining agent Sn0 ₂ (Examples 1-8, 11, 12, 14, 15) or As ₂ 0 ₃ (Examples 9, 10, 13) with a proportion of 0.3 wt .-% is not listed. The following properties are specified:

- the thermal expansion coefficient ₂ o / 3oo (10 ^_6 / K) the density p (g / cm ³ )

- The dilatometric transformation temperature T _g (° C) according to DIN 52324

- the temperature at the viscosity 10 ⁴ dPas (referred to as T4 (° C)

- The temperature at the viscosity 10 ² dPas (referred to as T2 (° C), calculated from the Vogel-Fulcher-Tammann equation

- An acid resistance "HCl" as weight loss

(Abtragswert) of all-round glass slides of dimensions 50mm x 50mm x 2mm after treatment with 5% hydrochloric acid for 24 hours at 95 ° C (mg / cm ² ).

- a resistance "BHF" over buffered

Hydrofluoric acid as a weight loss

(Abtragswert) of all-round glass plates of dimensions 50mm x 50mm x 2mm after treatment with 10% NH ₄ F · HF for 20 min. at 23 ° C (mg / cm ² )

- the refractive power n _d

Examples:

Compositions (in% by weight based on oxide) and

essential properties of glasses according to the invention

1 2 3 4 5 6

Si0 ₂ 60, 0 60, 0 59, 9 58, 9 59, 9 61, 0

B ₂ 0 ₃ 7.5 7.5 7.5 8.5 7.5 9.5

A1 ₂ 0 ₃ 21.5 21.5 21.5 21.5 21.5 18, 4

MgO 2.9 2, 9 2.0 2.0 2.9 2.2

CaO 3.8 2.8 3.8 3.8 4.8 4.1

BaO 4.0 5.0 5.0 5, 0 3.1 4.5

ZnO - - - - - - α20 / 300 3, 07 3, 00 3.01 3, 08 3, 13 3, 11

(10 ^"6 / K)

ρ (g / cm ² ) 2.48 2.48 2.48 2.48 2.47 2.45

Tg (° C) 747 748 752 741 743 729

T 4 (° C) 1312 1318 1315 1308 1292 1313

T 2 (° C) 1672 1678 1691 1668 1662 1700 n _d 1, 520 1, 518 1, 519 1, 519 1, 521 1, 515

HCl 1, 05 n.b. 0.85 n.b. 1.1 n.b.

(mg / cm ² )

BHF 0, 57 0, 58 0, 55 0, 55 0, 56 0.49

(mg / cm ² )

7 8 9 10 11 12

Si0 ₂ 58, 5 62, 8 63, 5 63, 5 59.7 59.0

B ₂ 0 ₃ 7.7 8.2 10, 0 10, 0 10, 0 9.0

AI2O3 22, 7 16, 5 15, 4 15, 4 18, 5 17, 2

MgO 2.8 0.5 2.0 1.0 2.0

CaO 2.0 4.2 5, 6 6, 6 8,3 9,0

BaO 5.0 7.5 3.2 3.2 3.2 3.5

ZnO 1.0 - - - - -

O20 / 300 2.89 3, 19 3, 24 3, 34 3, 44 3.76

(10 ^"6 / K)

p (g / cm ^J) 2 50 2.49 2.42 2.43 2.46 2 50

Tg (° C) 748 725 711 719 714 711

T 4 (° C) 1314 1325 1320 1327 1281 1257

T 2 (° C) 1674 1699 nbnb 1650 1615 n _d 1, 520 1, 513 1, 511 1, 512 1, 520 1, 526

HCl n.b. 0, 30 0.89 n.b. n.d. 0, 72

(mg / cm ² )

BHF 0, 62 0.45 0.43 0.40 0, 44 0.49

(mg / cm ² )

nb = not determined

As the embodiments illustrate, the glasses have the following advantages:

- a thermal expansion ₂ o / 3oo between 2.8 x 10 ^"6 / K and 3.8 x ^{10" -6} / K, in preferred embodiments, ^ 3.6 x 10 ^"-6 / K, in particularly preferred embodiments, <3, 2 x 10 ^"6 / K, thus adapted to the expansion behavior of amorphous and increasingly polycrystalline silicon. - With T _g > 700 ° C a high transformation temperature, so a high temperature resistance. This is essential for the lowest possible production-related shrinkage

("Compaction") and for the use of glasses as

Substrates for coatings with amorphous Si layers and their subsequent tempering.

- With p <2.600 g / cm ³ a low density

- a temperature at the viscosity 10 ⁴ dPas

(Processing temperature V _A ) of a maximum of 1350 ° C, and a temperature at the viscosity 10 ² dPas of at most 1720 ° C, which means a suitable viscosity characteristic in terms of hot forming and Schmezlbarkeit.

- with n _d ^ 1.526 a low refractive index.

- a high chemical resistance documented i.a. by good resistance to buffered hydrofluoric acid solution.

The glasses have a high thermal shock resistance and good devitrification stability. The glasses are in the form of flat glasses with the various drawing methods, e.g. Micro-sheet down-draw, up-draw or overflow fusion

Process and in preferred embodiment, if they are free of AS2O3 and Sb ₂ 0 ₃ , also with the float process

producible. With these properties, the glasses are ideally suited for use as a substrate glass in the

Production of interposers.

The use of the base substrate of low alkali glass and having a coefficient of thermal expansion very close to that of the silicon material chip causes difficulties due to differential thermal expansion of the interposer and CPU chip largely avoided. If adjacent, interconnected material layers or plates heat only slightly different and the

Thermal expansion coefficient is little different, occur less mechanical stress between these bonded layers or plates, and there will be no dislocation or cracks between the layers or plates.

Interposer, which are densely occupied with holes over previous interposers, take smaller substrate sizes, whereby the extent of different strains and shrinkages of the layers or plates involved and thus the risk of discarding and thus the

Cracking between the layers or plates involved is further reduced.

Finally, cost reductions are also to be expected because (with reduced interposer size and hole size) less material on glass and on lead material for

Filling the holes must be used.

Claims

claims

Interposer for the electrical connection between a CPU chip and a circuit board,

with the following features:

a plate-shaped base substrate (1) made of glass with a first and a second plate side;

the base substrate (1) has a

Thermal expansion coefficient in the range between

3.1 x KT ⁶ / ° C and 3.4 x 10 ^-6 / ° C;

the base substrate has holes (12) across the sides of the sheet in a number ranging between 10 and 10,000 cm ² ;

there are holes (12) with diameters ranging between 20 pm and 200 pm;

the distance between the holes (12) measured from

Hole center to hole center, lies in the range between 50 pm and 700 pm;

on the first side of the plate

Conductor tracks (13) each extend into and through the holes (12) (14) on the second plate side to form connection points for the CPU chip.

Interposer according to claim 1,

wherein the glass of the base substrate contains an alkali content of less than 700 ppm.

Interposer according to claim 1 or 2,

wherein the glass of the base substrate is an arsenic or Contains antimony content of less than 50 ppm.

4. Interposer according to one of claims 1 to 3,

wherein the coefficient of thermal expansion is 3.2 x 10 -6.

5. Interposer according to one of claims 1 to 4,

wherein the plate thickness of the substrate (1) is in the range between 30 μιη and 1000 μτ.

Interposer according to one of claims 1 to 5,

the number of holes in the range between 1000 to

3000 cm ^"2 lies.

Interposer according to one of claims 1 to 6,

wherein the diameter of the holes (12) is at most 100 pm.

Interposer according to one of claims 1 to 7,

wherein the center distance of the holes (12) (12) is in the range between 150 ym and 400 μπι.

Interposer according to one of claims 1 to 8,

wherein the hole edge spacing of the holes (12) at least

30 pm.

Interposer according to one of claims 1 to 9,

wherein holes (12) of different diameters are provided in the plate-shaped base substrate (1).

Interposer according to one of claims 1 to

the following dimensional ratios are met become :

Hole center distance to hole diameter in the range of 1 to 10;

Hole edge distance to hole diameter in the range of 1 to 9;

Plate thickness of the substrate to hole diameter in the range of 0.1 to 25.

12. Interposer according to one of claims 1 to 11,

the hole edges between plate side of the

Base substrate and hole reveal are rounded-broken.

13. A method for producing holes in a

Interposer according to one of claims 1 to 12,

with the following steps:

a) providing the base substrate (1) to be punched out of glass;

b) aligning a multiple laser beam assembly (4) on predetermined Lochungsstellen (10) of the

Base substrate (1);

c) triggering focused laser pulses (41) in

a wavelength range between 1600 and 200 nm, in which the glass is at least partially transparent, and having a radiation intensity which results in local, athermal destruction of the glass along each filamentary channel (11); d) widening of the filamentary channels (11)

desired diameter of the holes (12).

14. The method according to claim 13,

wherein the widening of the filamentary channels (11) by electrothermal heating and evaporation of hole material due to dielectric breakthroughs. 15. The method according to claim 13,

wherein the widening of the filamentary channels (11) is effected by reactive gases.

Process for the production of holes in one

Interposer according to one of claims 1 to 12,

with the following steps:

a) double-sided printing of the base substrate (1) made of glass with HF coupling material, punctiform at intended Lochungsstellen (10);

b) moving the printed base substrate (1) into

a processing space flanked by plate-shaped RF electrodes (2, 3);

c) applying RF energy to the base substrate (1) which predominantly heats the dot-like applied RF coupling material until softening of the base substrate material occurs there;

d) generating high voltage between the electrodes (2, 3) to produce narrow channels (11) due to dielectric breakdowns from the RF coupling points.

17. The method according to claim 16,

wherein a widening of the narrow channels (11) as a result of dielectric breakthroughs to holes (12) by deep, reactive ion etching takes place.