WO1997003460A1 - Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip - Google Patents

Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip Download PDF

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Publication number
WO1997003460A1
WO1997003460A1 PCT/JP1996/001905 JP9601905W WO9703460A1 WO 1997003460 A1 WO1997003460 A1 WO 1997003460A1 JP 9601905 W JP9601905 W JP 9601905W WO 9703460 A1 WO9703460 A1 WO 9703460A1
Authority
WO
WIPO (PCT)
Prior art keywords
bare chip
wiring
board
purine
wiring board
Prior art date
Application number
PCT/JP1996/001905
Other languages
French (fr)
Japanese (ja)
Inventor
Takeshi Kagatsume
Original Assignee
Hoya Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP7/176061 priority Critical
Priority to JP17606195 priority
Application filed by Hoya Corporation filed Critical Hoya Corporation
Priority claimed from JP52748996A external-priority patent/JP2989271B2/en
Publication of WO1997003460A1 publication Critical patent/WO1997003460A1/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of H01L27/00 - H01L49/00 and H01L51/00, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]

Abstract

A bare chip mounted board on which electronic parts can be mounted at a high density. A bare chip (2) is mounted on a glass substrate (1) and various kinds of thin film electronic elements are formed on the substrate (1). The thin film electronic elements shown in the figure are TFT (3), a diode (4), a capacitor (5), and a resistor (6), all being covered with a protective film (7). The electronic elements are formed by lithography. A wiring layer is also formed by lithography. The bare chip (2) does not have any pad for electrode and electrode terminals are led out from the wiring layer on the lower surface of the chip (2) and directly connected to the connecting terminals of the substrate (1) through A1 wiring (8). When the glass substrate (1) is used as a printed wiring board in such a way, thin film electronic elements can be formed at a high density by lithography.

Description

Bright fine manual bare chip mounting board, a bare chip mounting board preparation and bare electrode forming method technology partial field

The invention various semiconductor components provided with Beachi' flop tower mounting board on the substrate, a method of manufacturing the bare chip mounting board, and to a electrode forming method of the bare chip is directly mounted on purine preparative wiring board, in particular the device bare chip mounting has reduced size board, method of manufacturing bare chip mounting board to the size and possible, and miniaturized Chi-up about electrodeless forming method of the bare chip to be mounted on the purine preparative wiring board . Background technology

It becomes smaller high performance of co Npyu evening device such as, reduction in size of the various boards are desired mounting the semiconductor switch-up. The baud de To miniaturize a child various semiconductor chips rather small is effective means. In general, a semiconductor chip of CPU chips are incorporated in the package, the package is mounted on purine Bok substrate. The semiconductor chip itself Ku label very small size of the package. Thus, lever to directly mounted on the substrate of the semiconductor chip, it is a child rather small the amount board that Habukeru the package. It should be noted that the semiconductor chip that are not included in such a package is referred to as a bare chip.

Recently, bare chip, which is good warranty (KGD: Known Good Die) has come to be shipped from the semiconductor main one force, also each species baud domain one force it has become possible to obtain a bare chip. A technique for implementing the direct purine preparative substrate bare chips is important.

As a technique for implementing a bare chip on purine Bok substrate, there is a wire bonding packaging method or full re-Chip method. Waiyabonde Lee ring system, an electrode pad disposed around the chip, a method for connecting a metal thin wire from the electrode pad on the wiring pattern. On the other hand, the full re-Chip method and the solder ball is provided called bumps on the chip electrodes, it is contacted to the wiring patterns by the bumps downward. Then, the electrical connection Ri by the and the child to melt the bump.

Using such techniques, MCM (multi 'chip' module) and the like have been commercialized.

However, in order to provide and go 'pump a wire bonding packaging, it must be provided very large electrode pad than the internal wiring. That is, since spiking mechanically the Wa I catcher in wire bonding ring system, should be taken rather large tolerance of position error at that time can not and child rather small the head. On the other hand, in the full re-Chip system, and you narrow the distance between the head of the solder between the risk increases to short-. Thus, there is a limit to miniaturization of the pad is difficult small and Kusuruko is base Achi' flop in the conventional manner. Therefore, the limit has been made to the miniaturization of the board mounting the bare chip.

Incidentally, there is a re-lithography one as a technique for forming an electronic component on the module substrate, it is also possible and densification child electronic parts and wiring pattern by using the re-lithography scratch. Their to, small and Kusuruko becomes possible to board if the wiring path coater emissions and a high density child. However, purine preparative substrate by conventional glass-epoxy like and sera mission-box like smoothness can not be obtained sufficiently in the surface, it can not be a high density child electronic components be used Li lithography over.

Moreover, implementing the direct purine preparative substrate bare chips, for reliability of the manufactured board, also occurs following problems.

The first problem with reliability, the Ru a glass epoxy substrate, alkali ions of the substrate is a child would migrate to the mounted bare chip. Migration of such Al force Li ions may cause malfunction, leading to reduction in reliability.

The second problem with reliability, Serra mission-box and Garasuepoki shea various semiconductor parts thermal expansion of the substrate is mounted with thermal expansion and differ significantly for (eg sheet re co down any) over time contact failure is likely NALCO and caused between the I Ri substrate and the semiconductor component to change. Inventions of disclosure

The present invention has been made in view of these points, the electronic components is a high density, and an object of the provide child bare chip mounting can by reliability rather forming board.

Another object of the present invention is extremely A small electrode, and the child provides a method for producing Beachi' flop mounting board as possible and bare chip and purine preparative wiring board and wiring child.

Et al is another object of the present invention is a child provide an electrode forming method of the bare chip of very small electrodes can and formed child on the bare chip.

In the present invention, in order to solve the above problems, in the bare chip mounting boards on which various semiconductor components is provided on a substrate, a purine preparative wiring board and the wiring layer is formed as a thin film electronic elements on a glass substrate, wherein implemented in purine Bok wiring board, a bare chip electrodes are directly connected to the wiring layer, is Beachi' flop mounting board, characterized that you have a provided.

Further, in the bare chip mounting boards on which various semiconductor components is provided on a substrate, a purine preparative wiring board in non-alkaline glass substrate with a thin film electronic device and wiring layer is formed, the purine preparative wiring base a bare chip which is mounted on the plate, the base Achippu mounting board, characterized that you have a provided.

Further, in the bare chip mounting boards on which various semiconductor components provided on a substrate, the thermal expansion coefficient of shea Li co down thin film electronic device on a glass substrate that approximates the purine preparative wiring and the wiring layer is formed a base plate, wherein the purine Bok wiring base § Chi-up mounted on the substrate, the bare chip mounting board, characterized that you have a provided.

Also, various in base § Chi Tsu manufacturing method flop mounting board for mounting the semiconductor component, the connected wiring layer sac Chi suited those parts within the semiconductor device in the state of exposing using a Li lithography over on the surface of the Beachi' flop formed, to form a by Ri electrode Li Sogurafu I one, Ri by a wiring layer for connecting to the electrode, the Li lithography foremost surface of purine bets wiring board using a glass substrate and, mounting the bare chip Ri by said electrodes and wiring child to the wiring layer on the purine preparative wiring board, a bare chip mounting board and said the this - de fabrication method is provided. Et al is, in electrodes forming method of bare chips are directly mounted on purine preparative wiring board, the surface of the base Achippu state where the wiring layers of the internal circuit is formed is covered with a protective film, before the position where taking out electrode serial protective film is removed Ri by the re lithography and foremost, the protective film to form an electrode metal Ri by the re lithography foremost position removed, the electrode forming method of the bare chip, wherein the call is provided that.

According to the bare chip mounting board shown above, high density thin film electronic devices are formed on the higher flat Namerado surface of the glass substrate. And, the Ri by the semiconductor element directly connected implemented child in a state of bare chips, the entire circuit of the purine bets wiring board becomes dense, various electronic circuits are formed on a very narrow area.

Also, by that it is a purine Bok wiring board in non-alkaline glass substrate with a thin film electronic device and wiring layer are formed, base mounted Achippu, TFT (Thin Film Transistor), diodes, resistors, capacitors, etc. thin film electronic device and rather this Togana the transition alkaline ions occurs between the substrate, reliable bare chip mounting board obtained.

Also, by that it is a purine Bok wiring board with a thin film electronic device and the wiring layer formed on a glass substrate having a thermal expansion coefficient is approximate to the sheet re co down, between the bare chip and the substrate to be mounted in the occurrence of contact failure due to aging can and child prevented, high base Achippu mounted baud de reliability.

Further, according to the manufacturing method of the bare chip mounting board shown above, the connected wiring layer sac Chi appropriate portions to the semiconductor device on the surface of the bare chip of the exposed state with the re Seo Rafi one, Li and forming an electrode by Seo photography one, the wiring layer order to connect to the electrode by the formation child by Li lithography foremost surface of purine bets wiring substrate using the glass substrate, the width of the internal wiring of the bare chip about the same size of the electrode and the wiring layer is provided for connecting the electrodes. Since the electrodes of the bare chip are obtained by implementing a bear chip by a wiring child in a wiring layer of purine bets wiring board purine preparative wiring board, it is possible to implement a bare chip in a very small area.

Et al is, according to the electrode forming method of the bare chip shown above, covers the surface of the bare chip state in which the wiring layer of the internal circuit is formed by the protective film, the protective film of the position to take out the electrode to re lithography one more removed, by the child form the electrode metal by Li lithography foremost protective film is removed position, without the electrode pads on the bare chip, that is provided directly connected to electrode terminals inside the wiring layer . Easy single a description of FIG surface 1 is bare chip mounted baud de sectional view of the present invention,

Figure 2 is a table showing the composition of a non-Al force Rigarasu which meet the requirements of thermal expansion,

Figure 3 shows the step of providing the electrode terminals in the bare chip figures, FIG. 4 showing a step of wiring the electrodes on the purine preparative wiring board (PCB),

Figure 5 is a view showing a step of mounting a bare chip purine preparative wiring board,

6 is an enlarged view of the junction between the purine preparative wiring substrate and the bare chip. BEST MODE FOR CARRYING OUT THE INVENTION

DETAILED DESCRIPTION OF THE PREFERRED embodiment of the present invention with reference to the drawings.

Figure 1 is a cross-sectional view of the bare chip mounting board of the present invention. On glass substrate 1, the bare chip 2 is mounted with various film electronic elements are formed.

Thin film electronic elements are shown, TFT 3, diode 4, condenser 5, and a resistor 6. Thin film electronic elements are covered with a protective film 7. These are formed Ri by the Re Sogurafu I one being utilized manufacture of the substrate of the LCD (liquid crystal display).

Bare chip 2 pad for electrode is not provided, the electrode terminals are provided directly inside the wiring chip. The electrode pin is A 1 wire provided Ri by the Re lithography foremost on the internal wiring of the chip.

Then, the glass substrate 1 on re Sogurafu foremost by Ri provided wiring layer, and A 1 wire electrode of the bare chip 2 is connected by direct secondary aluminum Yumu (A]) wiring 8.

Thus, by the this using a glass substrate 1 as a purine preparative wiring substrate, thereby enabling the shape formed of high density thin film electronic device according to Li Sogurafu I one is. Moreover, since the bare chip 2 is not provided pad is correspondingly small.

In particular, when a non-alkaline glass to the glass substrate 1, alkaline ions does not and child transition from the substrate to the thin-film electronic devices and semiconductor components. Therefore, rather than gunna malfunction child under the influence of alkali ion, reliability of the operation of the bare chip mounting board is maintained. In here, the non-alkaline glass is a generic name of glass in the glass component contains no alkali metal.

Furthermore, the closer the thermal expansion coefficient semiconductor components of the glass substrate 1, there is no and this contact failure occurs between the substrate and the semiconductor components due to aging. Therefore, the glass thermal expansion coefficient approximate to a semiconductor component, be used as the material of the glass substrate, thereby improving the reliability of operation of the bare chip mounting baud mode. The average linear thermal expansion coefficient of the sheet re con which is used as a material of the semiconductor component 3 4 x 1 0 -. And a this is a 7 Z ° about C, and because not to cause contact failure due to aging change, the substrate the average linear thermal expansion coefficient of 3 0~ 4 8 X 1 0 - 7 should be within the range of ° C (1 0 0~ when measured at a temperature range of 3 0 0 ° C).

Figure 2 shows the composition of a non-alkaline glass meets the requirements of the coefficient of thermal expansion.

It shows the three glasses in this FIG. The average linear thermal expansion coefficient of the first example is a 3 7 x 1 0 -7 / ° C, average linear thermal expansion coefficient of the second embodiment is 4 3 X 1 0 -7 / ° C, the third the average linear thermal expansion coefficient of the example is a 4 6 x 1 0 -7 / ° C. Thus, all three are fully satisfy the above conditions. That is, approximate thermal expansion coefficient to the coefficient of thermal expansion of the sheet re co down.

Incidentally, the glass shown in FIG. 2, also slightly changed the composition, 3 average linear thermal expansion coefficient of 0 - 4 8 X 1 0 - Huda. It is and this suppressed to within the range of C.

If changing the composition of the glass shown in the first example, "S i 0 2, B

2 0 3, A 1 2 〇 3, M g O, C a O, S r O, and B a O contained in total 9 5 mol% or more, the content of each component by mol%, S i 0 2 6 6 8% 2% or more or less, B 2 0 3 is less than 1 2% on 8% or more, A 1 2 0 3 or less 1 3% more than 9%, M g O is 1% or more 5%, C a 0 7% 3% or more or less, S r O is less than 3% in 1% or more, if B a 0 is a glass "in less than 3% in 1% or more, average linear thermal expansion coefficient falls within a range of 3 0~ 4 8 X 1 0 -7Z ° C.

The content of the optional components "mol% of varying the composition of the glass shown in the second example, S i 〇 2 5 5~ 6 5%, A 1 2 0 3 is 7-1 1% , P b 0 is 1 ~ 1 1%, M g 0 is 3~ 1 3%, C a 0 is 7~ 2 0%, Z n 0 is 3~ 1 3%, Z r 〇 2 power 0-3% , F 2 Chikaraku 0 3% a s 2 0 3 forces 0 5% S b 2 0 3 power, 'if glass "is 0 5% average linear thermal expansion coefficient of 3 0 4 8 X 1 0 - 7 fall within the scope of Bruno ° C.

Next, a method for manufacturing the bare chip mounting board shown in FIG. Manufacturing process is roughly divided into steps of providing an electrode terminal with no pad bare chip (Pas head-less bare chip), a step of wiring the electrodes on the purine preparative wiring substrate, and a pad-less bare chip purine Bok wiring board can and this divided into process of implementation.

Figure 3 illustrates a step of providing electrode terminals on the bare chip. Figure A shows a cross-sectional view of the bare chip of each process.

In step 1 (S 1), providing a bare chip 1 0 no pad. The bare chip 1 0 between the sheet re co down (S i) protective film 1 2 which is formed on the substrate 1 1, a thin film electronic device is formed. The thin film electronic device is composed of the wiring 1 4 a~ l 4 c of the internal circuit, the A 1 line 1 3 a~ l 3 c.

Incidentally, A] does not require a special treatment for connection with external wiring 1 3 a~ 1 3 c itself. That is, the conventional joint as compared with the electrode pad which is provided in the bare chip very small Kuteyoi. Is usually electrode pad been made in about 1 0 0 ^ m, the size of the A 1 line 1 3 a~ 1 3 c can also small Kusuruko to less than 2 m. In step 2 (S 2), forming a protective layer 1 5 of the protective film on the surface of the bare chip 1 0. The thickness in which to move the protective film 1 2 and the protective layer 1 5, taking into account the irregularities of the electrode junction purine preparative wiring board side, it is opened from the front and rear 5 zm 1 0 m in order before and after.

Step 3 In (S 3), performs re Seo chromatography using a wiring layer contactor Bok mask extraction drilled a hole in a position to take out the electrodes, A 1 line 1 3 a to l 3 protective layer 1 on c 5 providing holes 1 6 a ~ 1 6 c to. The position to be taken out of the electrodes may take any desired special restrictions, such as must be periphery of the chip.

In step 4 (S 4), the surface deposition of a metal such as aluminum or copper, and sputter-ring or eye luck, re lithography scratch using the wiring layer forming mask drilled a hole in a position to take out the electrode performed to form a 1 line 1 Ί a ~ l 7 c for connection. Then, to remove the protective layer 1 5 provided in step 2. The order of electrodes for connection to the remaining A 1 line 1 7 a ~ 1 7 c force purine preparative wiring board.

Figure 4 is a view showing a step of wiring the electrodes on the purine preparative wiring board (PCB). This process is performed in parallel with the higher E providing an electrode terminal to the bare chip. Figure A shows a cross-sectional view of a purine preparative wiring board 2 0 for each process.

In step 5 (S 5), the purine preparative wiring board 2 0, a thin-film electronic devices and A wiring 2 7 a ~ 2 7 f is formed by reactive lithography foremost glass substrate 2 1. Li lithography one are those used in the manufacture of LCD substrates than traditional. Thus, TFT 2 3 on the glass substrate 2 1, diode 2 4, capacitor 2 5, and the resistor 2 6 is formed. These thin-film electronic devices and A〗 wiring 2 7 a to 2 7 f is covered with a protective film 2 2.

In step 6 (S 6), eight 1 to line 2 7 Ji ~ 2 7 6 a protective film 2 2 are One covering, bare chip 1 0 hole 2 8 a to for connection (shown in FIG. 3) 2 open the 8 c. The position of the hole 2 8 a~ 2 8 c is, A 1 wiring bare chip 1 0 1 7 a~: a position to match the position of the I 7 c.

In step 7 (S 7), provided A 1 wiring 2 9 a~ 2 9 c for connection on A 1 wiring 2 7 c~ 2 7 e exposed from the hole. A 1 wiring 2 9 a~ 2 9 c This is the terminal for connecting the bare chip 1 0 (shown in FIG. 3).

Figure 5 is a view showing a step of mounting a bare chip purine preparative wiring board.

In step 8 (S 8), the bare chip 1 0 that was created in step 4 (FIG. 3), step 7 superimposed on purine preparative wiring board 2 0 that were created in (shown in FIG. 4). At this time, keep the surface of the Prin preparative A 1 wiring 2 9 of the wiring board 2 0 a to 2 9 c A 1 line 1 7 between the bare chip 1 0 a ~ 1 7 c is activated. Their to electrical positioning is performed such that the position of the purine preparative A 1 wiring 2 9 of the wiring board 2 0 a to 2 9 c and bare chip 1 0 A 1 line 1 7 a to l 7 c matches to contact. This ensures that the purine preparative wiring board 2 0 AI wiring 2 9 a to 2 9 c and bare chip 1 0 A 1 line 1 7 a ~ 1 7 c and is Ru bound by surface activation room temperature bond o

Surface activation room temperature bonding, since the bonding interface is a direct bonding without atomic level reactive layer can reversibly separated child. Such binding is referred to as reversible I Ntakoneku collection.

In step 9 (S 9), solidify around the fused A 1 lines 3 1-3 3 with an insulating resin 3 4.

6 is an enlarged view of the junction between the purine preparative wiring substrate and the bare chip. Bare chip 1 0 cross section in the vicinity of the electrode is Narutsu a plurality of layers. Layer is shown, the wiring of the upper Karachi-up internal circuit 1 4, a protective film 1 2. The wiring 1 4 is connected to A 1 lines 1 3, the AI ​​wire 1 3 is et surface is connected to A 1 line 1 7 activated. The thickness of the chip wiring 1 4 0. A 8 / m, A thickness of the wiring 1 7 5 rr! ~ Is a 1 O ^ m. 1 The purine preparative wiring board 2 0. 0 ~ 1. 2 m A 1 line width

2 7 is provided. The Beachi-up a connection to base out portion of the A 1 line 2 7 has holes drilled in the protective layer, A 1 wiring 2 9 whose surface is activated is provided. The A 1 wiring 2 9 by Ri reversible fin evening one connector tion to the this of adhering the A 1 line 1-7 base Achippu 1 0 to the position of the is performed. Incidentally, with respect to A 1 wiring 2 9, the previously formed metal bumps such as gold as a bare chip bonding, the reliability of the junction is further improved.

The purine preparative wiring board 2 0, Lee Ntafu Esu 2 0 a have been found provided, can be tied to a bus computer via the interface 2 0 a.

In the above example, it explains the those using aluminum wiring metal, in the wiring metal may be used copper or various other alloys in addition to aluminum.

As described above, Roh the purine Bok wiring board using a glass substrate. Tsu can and implement child dress base Achippu. In here, glass substrates for very high surface smoothness, it is a child that is responsible for high-density wiring with technology of re lithography scratch. Accordingly, the wiring that was in seven layers and eight layers in the substrate made of glass epoxy, it is a sufficiently cover this in degrees about two layers. Moreover, by using this re lithography over, it is a this to form a thin film electronic device of high integration density on a glass substrate.

In addition, Ri by the and the child to be unnecessary pad to the bare chip, it is a small Kusuruko the Beachi-up. For example, space for pad general bare chip is pad around is provided, pads of one side 1 0 0-1 5 0 〃 m square shape, a space formed in the periphery of the pad 4 is a 0 m. In here, the case where the width of the scan Bae one nest for the pad was 2 0 0 im, the proportion of the space for Nog head to the size of the bare chip is as follows.

If the chip size is 3. 5 mm 2, 2 2%.

If the chip size is 4. 0 mm, 1 9%.

If the chip size is 4 · 5 mm, 1 7%.

If the chip size is 5. 0 mm 2, 1 5%.

In this way, the effect of the package dress is rather come large the smaller chip size. Simultaneously with the this that the chip size is small can be downsized bare mounting board, a bare chip Te manufacturing process smell, will let out cut more chips from one substrate. In the above present invention, as described, for you to implement directly the bare chip purine preparative wiring board on which various thin film electronic elements formed on a glass substrate, and a child miniaturized bare mounting board it can.

Also, by that you use the purine bets wiring board free alkaline glass or thermal expansion coefficient, a glass substrate that approximates the sheet re con, possible to get a reliable bare chip mounting board It is Ru can. And such a purine Bok wiring other than ones described in the above description, S i O 2 5 6-6 4% by weight%, A 1 2 0 3 is 1. 8 to 2 to 4%, N a 2 0 power. 2 to 3% M g O power 2-6%, a Z n Chikaraku 2-1 1% composition, thermal expansion coefficient 3 1 0 0~ 3 0 0 ° Ji temperature zones glass 1 is 3 6 X 1 0 -7 ° C can also Mochiiruko.

Further, since they were taken out directly electrode from the internal wiring of the bare chip by re Sogurafu I one can and small Kusuruko to be al the pad is bare chip becomes unnecessary for the electrodes.

Claims

In 請 range 1 determined. Bare chip mounting boards on which various semiconductor components is provided on the substrate,
And purine preparative wiring board with a thin film electronic device and wiring layer are formed on a glass substrate,
A bare chip which the implemented in purine Bok wiring board, the electrode is connected to the serial to the wiring layer,
Bare chip mounting board, wherein a call with.
2. The Beachi-up, in any position of the internal wiring, substantially claim 1 bare chip mounting board according to the internal wiring of the same order of magnitude of the electrode is taken out, wherein the Iruko .
3. The purine DOO wiring board, said as a glass substrate, a bare chip mounting board according to claim 1, wherein that you are using a non-alk Rigarasu.
4. The purine Bok wiring board, said as a glass substrate, a bare chip mounting board according to claim 1, wherein the thermal expansion coefficient, characterized in that you are using a glass approximate to the sheet re Con.
. [Delta] wherein the purine Bok wiring board, wherein a glass substrate, 1 0 0 ~ 3 0 0 ° C average linear thermal expansion coefficient of 3 0 ~ 4 8 X 1 0 in the temperature range of - 7 / ° in the range of C bare chip mounting baud de of claim 4, wherein that you have used glass and feature.
6. In the bare chip mounting boards on which various semiconductor components is provided on the substrate,
Bare chips to free Al force Li glass substrate as the thin-film electronic devices and purine preparative wiring board and are formed wiring layer, and a bare chip mounted on the purine preparative wiring board, characterized that you have a It mounted on board.
7. The purine Bok wiring board, and with the glass substrate, shea Li co down and bare chip mounting baud de of claim 6, wherein the thermal expansion coefficient, characterized in that you are using a glass approximated.
8. The purine DOO wiring board, and with the glass substrate, 1 0 0~ 3 0 0 ° C average linear thermal expansion coefficient of 3 0 ~ 4 8 X 1 0 in the temperature range of - 7 of Z ° C bare chip mounting board according to claim 7, wherein that you have a glass in a range to FEATURE:.
9. In the bare chip mounting boards on which various semiconductor components is provided on the substrate,
And purine preparative wiring board and the wiring layer thin film electronic elements formed on a glass substrate having a thermal expansion coefficient is approximate to the sheet re-Con,
Bare chip mounting board to the Achippu base mounted on the purine preparative wiring board, characterized that you have a.
1 0. The purine DOO wiring board, prior to, and the d glass substrate, 1 0 0-3 0 0 average linear thermal expansion coefficient in a temperature range of ° C is 3 0~ 4 8 X 1 0 - 7 / ° bare chip mounting board of claim 9, wherein that you are using the glass in the range of C.
In 1 1. Beachi Tsu method of manufacturing flop mounting board for mounting the various semiconductor components,
The connected wiring layer sac Chi appropriate portions to the semiconductor device on the surface of the bare chip being exposed with Li source graph I over, thereby forming an electrode by reactive lithography over or main luck, the electrode a wiring layer for connecting to form Ri by the re lithography foremost surface of purine Bok wiring substrate using the glass substrate, the bare chip Ri by the wired to child said electrode to the wiring layer and the purine It is mounted on the door wiring board,
Method of manufacturing a bare chip mounting board, wherein a call.
1 2. The bare chip when mounting the purine DOO wiring board, the surface Ri FOR A FULL joining metal between activated, the electrodes of the bare chip to the wiring layers of the purine Bok wiring board bare chip mounting board manufacturing method according to claim 1 1, wherein the arcs connected.
In 1 3. Purine preparative wiring board electrodes forming method of bare chips are directly mounted to,
The surface of the bare chip state in which the wiring layer of the internal circuit is formed is covered with a coercive Mamorumaku,
The protective film of the location to retrieve the electrode was removed Ri by the Re lithography one,
To form a more electrode metal to Li lithography over or main luck to the position where the protective film is removed,
Electrode forming method of a bare chip which is characterized and this.
PCT/JP1996/001905 1995-07-12 1996-07-09 Bare chip mounted board, method of manufacturing the board, and method of forming electrode of bare chip WO1997003460A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7/176061 1995-07-12
JP17606195 1995-07-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52748996A JP2989271B2 (en) 1995-07-12 1996-07-09 Bare chip mounting board producing method and a bare chip method of the electrode forming the bare chip mounting board

Publications (1)

Publication Number Publication Date
WO1997003460A1 true WO1997003460A1 (en) 1997-01-30

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EP0900971A1 (en) * 1997-09-09 1999-03-10 Glasbau Hahn GmbH & Co. KG Illumination device with LED's mounted on a glass plate
US6377292B1 (en) * 1999-04-23 2002-04-23 Oki Data Corporation LED print head with reduced reflection of light leaking from edges of LED array chips
US6610934B2 (en) 2001-05-31 2003-08-26 Hitachi, Ltd. Semiconductor module and method of making the device
AT413170B (en) * 2003-09-09 2005-11-15 Austria Tech & System Tech Thin film arrangement has substrate in form of circuit board with insulating material base body, metal lamination as conducting coating forming base electrode and flattened at thin film component position
AT500259B1 (en) * 2003-09-09 2007-08-15 Austria Tech & System Tech Thin-layer assembly and method for producing such a thin-layer assembly
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Publication number Priority date Publication date Assignee Title
EP0900971A1 (en) * 1997-09-09 1999-03-10 Glasbau Hahn GmbH & Co. KG Illumination device with LED's mounted on a glass plate
US8103739B1 (en) 1998-08-20 2012-01-24 Gautier Taylor S Optimizing server delivery of content by selective inclusion of optional data based on optimization criteria
US6377292B1 (en) * 1999-04-23 2002-04-23 Oki Data Corporation LED print head with reduced reflection of light leaking from edges of LED array chips
US6610934B2 (en) 2001-05-31 2003-08-26 Hitachi, Ltd. Semiconductor module and method of making the device
AT413170B (en) * 2003-09-09 2005-11-15 Austria Tech & System Tech Thin film arrangement has substrate in form of circuit board with insulating material base body, metal lamination as conducting coating forming base electrode and flattened at thin film component position
AT500259B1 (en) * 2003-09-09 2007-08-15 Austria Tech & System Tech Thin-layer assembly and method for producing such a thin-layer assembly
US7551454B2 (en) 2003-09-09 2009-06-23 At & S Austria Technologie & Systemtechnik Aktiengesellschaft Thin-film assembly and method for producing said assembly

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