EP2526738A1 - Circuiterie pour faire fonctionner au moins une source lumineuse à semi-conducteur - Google Patents

Circuiterie pour faire fonctionner au moins une source lumineuse à semi-conducteur

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Publication number
EP2526738A1
EP2526738A1 EP11767401A EP11767401A EP2526738A1 EP 2526738 A1 EP2526738 A1 EP 2526738A1 EP 11767401 A EP11767401 A EP 11767401A EP 11767401 A EP11767401 A EP 11767401A EP 2526738 A1 EP2526738 A1 EP 2526738A1
Authority
EP
European Patent Office
Prior art keywords
current
converter
circuit
compensated
rectifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP11767401A
Other languages
German (de)
English (en)
Inventor
Felix Franck
Bernhard Siessegger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Osram GmbH
Original Assignee
Osram GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram GmbH filed Critical Osram GmbH
Publication of EP2526738A1 publication Critical patent/EP2526738A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/35—Balancing circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40—Details of LED load circuits
    • H05B45/44—Details of LED load circuits with an active control inside an LED matrix
    • H05B45/46—Details of LED load circuits with an active control inside an LED matrix having LEDs disposed in parallel lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the invention relates to a circuit arrangement for operating at least two semiconductor light sources.
  • the semiconductor light sources are operated in different operating strands and with the same current.
  • the invention is based on a circuit arrangement for operating at least two semiconductor light sources according to the preamble of the main claim.
  • the voltage transformers used are operated either hard-switching or with simple ZVS (Zero Voltage Switching). This has the disadvantage of poorer efficiency.
  • circuit arrangement for operating at least two semiconductor light sources comprising:
  • At least one switch wherein the electric energy converter outputs a pulsating DC voltage or an AC voltage
  • the current-compensated choke is connected between the switch and the at least two rectifiers,
  • At least two semiconductor light sources which are each connected between the output terminal of the associated rectifier and its reference potential, wherein the elec ⁇ cal energy converter is designed as a resonant converter with a resonant cell, and the stray inductance of the current-compensated choke is used as resonance inductance of this resonant cell.
  • the resonance cell preferably has a series connection of the leakage inductance of the current-compensated choke and at least one capacitance.
  • the capacitance is preferably connected to the reference potential.
  • the electrical energy converter is a Class E converter. This is a simple efficient converter topology for high frequencies. In another embodiment, the electrical energy converter is a half-bridge converter. This transducer topology can also be used for low frequencies and works with good efficiency. But it requires two scarf ⁇ ter, one of which is a so-called high-side switch, the reference potential of the second, the switch may at times differ materially.
  • the electrical energy converter is a multiresonant cell converter, which, like the above Class E converter, is characterized in that it has only a single active switch on its input side. Any such transducer other than the class E converter is also referred to as a single-to-DC DC converter. These cell transducers work very efficiently due to the resonant mode of operation.
  • the cell transducers exist in embodiments as deep-set (buck), boost, or step-up embodiments (buckboost or choke-in-line converters, ' cuk, zeta, SEPIC).
  • a resonance capacitor is connected in parallel with each of the power semiconductors included in the converter topology. This causes a significant switching discharge, so that the power semiconductor can work in ZVS mode, that switches without voltage.
  • Such transducers are typically referred to as multiresonant transducers operating in dual ZVS mode.
  • the active semiconductor switch is usually controlled with fixed frequency or on-time- oriented PWM
  • a multireso ⁇ nanter cell converter requires the control of its active switch by a special state-dependent and frequenzvariab- le PWM. The voltage across the active switch is observed and will not be turned on again until its voltage returns to zero for the first time after the last turn-off or for the first time to be at a minimum.
  • the resonant capacitors in parallel to the diodes on the output side of the cell converter firstly reliably limit their reverse voltage, secondly their inrush current and thirdly their turn-off and turn-on voltage gradients. Separate monitoring of such connected diodes is not necessary because they operate in "natural ZVS.”
  • Each multiresonal cell converter produces a defined and stable no-load output voltage even without regulation Fourth, these resonant capacitors increase the work area in parallel with the converter output diodes active switches can switch in correct ZVS, compared to otherwise equal cell transducers without them.
  • a quasi-parallel operation of a plurality of light-emitting diodes and / or a plurality of light-emitting diode strands is proposed by means of a common electric energy converter with a one-directional or short-circuiting rectifier per light-emitting diode strand, wherein the current intensities of the current flowing through the light-emitting diodes are approximately identical. It only has to be regulated to the current in a light emitting diode or in a string of light emitting diodes. For this purpose, a transducer is used which outputs a pulsie ⁇ Rende DC voltage or an AC voltage.
  • the concept can be applied to any direct-voltage converter topologies (high and / or low-level transformer topologies).
  • the dimming of individual light-emitting diodes is possible by means of a respective transistor connected in parallel with the light-emitting diode, which is driven by a pulse-width-modulated signal. All outputs of the converter are short-circuit proof due to the current regulation and current balancing.
  • the circuit is tolerant to deviations in the forward voltages of the light-emitting diodes.
  • the circuit principle can be used for any input voltage, and can be used, for example, from 6Vdc (flashlight), 12Vdc (automotive), 24Vdc (truck) up to 277Vac.
  • the circuit is entspre ⁇ adapt accordingly, and the optionally contained Trans ⁇ formator is also used for voltage adjustment and possibly also for the insulation in order to comply with safety standards, is used.
  • Fig.l the principle of using a current-compensated choke learning for balancing the two LED currents Iol and Io2,
  • FIG. 6 shows the omission of a rectification and, in the case of asymmetrical loading of the current source, discontinuous current flow through the light-emitting diodes
  • FIG. 7 shows the omission of a rectification and a symmetrical loading of the current source discontinuous current flow through the LEDs
  • Fig. 8a the symmetrization of several light-emitting diodes or
  • Fig. 8b the symmetrization of several light-emitting diodes or
  • Fig. 8e is an imple mentation form of the circuit variant B.
  • Fig. 8f the symmetrization of several light-emitting diodes or
  • Fig. 8g the symmetrization of several light-emitting diodes or
  • 10a shows a choke-down converter with current balancing tion and two outputs, each one not belonging to the actual converter topology
  • FIG. 10b shows the inductor-down converter with current balancing and two outputs according to FIG. 10a with ohmic determination of the LED current measurement value and comparator Cmpl for detecting a gap current in the converter inductance LI, FIG.
  • 10c shows a choke-down converter with current balancing and three outputs
  • FIG. 13 shows a particularly advantageous embodiment of the invention
  • 15 shows the increase of the output currents in the particularly advantageous embodiment of the choke-down converter with current balancing and two outputs by increasing the input voltage
  • 16a shows an up-down converter with two outputs based on a Cuk converter in a variant AI
  • 16b shows an up-down converter with two outputs based on a Cuk converter in a variant
  • 17a shows an up-down converter with two outputs based on a Cuk converter in a variant
  • 17b shows an up-down converter with two outputs based on a Cuk converter in a variant
  • 18b shows an up-down converter with two outputs based on a SEPIC converter in a second
  • Output circuit consisting of Lr, Crl and Cr2 rea ⁇ lmarin an AC power source in the arrangement similar to the circuit variant B without Lcm5 from FIG. 8c,
  • FIG. 20a shows a half-bridge inverter with short-circuiting rectifiers or unbalanced voltage doublers, (identical to FIG.
  • FIG. 20b shows another illustration of the half-bridge inverter with reverse-shorting rectifiers, wherein each current-compensated inductor is replaced by an equivalent circuit consisting of a transformer and two leakage inductances Ls, and wherein the leakage inductances act in series with the resonance inductor Lr.
  • Fig. 20c is an advantageous embodiment of the half-bridge inverter with reverse short-circuiting
  • Rectifiers in which all of the stray inductances Ls ⁇ take over the function of the resonant inductor Lr complete, and in the per rectifier input, a resonance capacitor is interpreted Toggle to develop the circuit for multiresonan- th half-bridge converter,
  • 21a shows a half-bridge inverter with three reverse blocking and three forward blocking rectifiers
  • FIG. 21a Another representation of the half-bridge inverter of Fig. 21a, each current ⁇ compensated choke is replaced by an equivalent circuit consisting of a transformer and two scattering ⁇ inductances Ls, and wherein the leakage inductance acting in series with the resonant inductor Lr 21b Fig. 21c, an advantageous development of the half-bridge inverter of Fig. 21b, in which the total ⁇ standardize the stray inductance Ls take over the function of the resonant inductor Lr completely, and wherein per input rectifier, a resonance capacitor is indicated to develop the circuit for multi-resonant half-bridge converter,
  • Fig. 21d an advantageous development of the half-bridge inverter of FIG. 21c, wherein the total ⁇ standardize the stray inductance Ls take over the function of the resonant inductor Lr completely serving solution with an additional transformer Tr, for galvanic isolation and / or for voltage selection .
  • 21e shows an advantageous development of the half-bridge inverter from FIG. 21d with primary-side current measurement
  • Fig. 21f is an advantageous development of the half-bridge inverter with loud reverse blocking
  • Rectifiers and the additional transformer Tr which is used for galvanic isolation and / or voltage adjustment, the transformer having two secondary windings nsl and ns2, which are poled in opposite directions,
  • FIG. 23 shows a pulse width modulation controller with operation at the gap boundary, wherein neither switching frequency nor on or off duration are constant
  • FIG. 24 shows a controller based on a current-mode control principle
  • 25 shows a further embodiment of a three-output throttle down converter with current and current zero crossing detection
  • 26 is a choke-boost converter with two outputs, in which the current-compensated choke must sit at a position of the transducer, which is not intended for ei ⁇ ne inductance, which is why a coupled with the converter input inductance additional ⁇ cherkysbegrenzungszweig is required
  • 28a shows the block diagram of a circuit arrangement for balancing the two load currents II and 12 by the self-adjusting DC voltage V0 across the capacitor CO in two reverse-shorting rectifiers with voltage doubling (circuit type WD) in series,
  • 28b shows the basic circuit diagram of a circuit arrangement for balancing the two load currents II and 12 by the self-adjusting DC voltage V0 across the capacitor CO in two reverse-short-circuiting rectifiers with current output
  • FIG. 28c shows the situation with type WD for the case Ii> 0, FIG.
  • FIG. 28e shows the situation with type WD for the case Ii ⁇ 0
  • FIG. 28f Selected current and voltage characteristics of the circuit according to FIG. 28a, FIG.
  • Fig. 28g the principle circuit diagram of a circuit arrangement for balancing of the two load currents II and 12 through which adjusting DC voltage V0 across the capacitor CO in the supply voltage path in a backward and a forward sper ⁇ rendem rectifier with a simple voltage output (type of circuit VD) connected in parallel
  • Fig 28h the situation with type VD according to FIG.
  • FIG. 28i shows the situation with type VD according to FIG. 28k for the
  • FIG. 28 shows the situation with type VD according to FIG. 28k for the
  • Fig. Shows the basic circuit diagram of a circuit arrangement for balancing of the two load currents 28k II and 12 through which adjusting DC voltage V0 across the capacitor CO, the voltage source between the chip and the reference potential is connected, in a backward and a forward sper ⁇ rendem rectifier with easy Voltage output (circuit type VD) in parallel,
  • 29a shows a circuit arrangement for balancing the
  • Fig. 29b shows a circuit arrangement for balancing the
  • Fig. 29c shows a circuit arrangement for balancing the
  • 29d shows a circuit arrangement for balancing the
  • Fig. 30a shows a circuit arrangement for balancing the
  • Fig. 30b shows a circuit arrangement for balancing the
  • Fig. 30c shows a circuit arrangement for balancing the
  • Fig. 30d shows a circuit arrangement for balancing the
  • Fig. 34 shows the possibilities A) to C) as "building blocks" of converters, wherein by means of two capacitors a direct current through the current-compensated choke learning is prevented
  • Fig. 35 shows the union of the possibilities A) to C)
  • FIG. 35 is the general view of the building block of FIG. 35.
  • FIG. 37 shows the circuit according to FIG. 2, with resonant cell CCC1 drawn in, FIG.
  • FIG. 38 shows a ZVS half-bridge converter which uses the leakage inductances of the current-compensated reactors
  • 39a shows the basic structure of the step-down converter or buck converter with indicated positions for ZVS-enabling resonance elements
  • 39b shows the basic structure of the boost converter or the boost converter with indicated positions for ZVS-enabling resonant elements
  • 54a shows a multiresonant inherently current-symmetrizing zeta converter in insulating form with a common negative pole of the outputs
  • 55a shows a multiresonant inherently current-symmetrizing SEPIC converter in completely insulating form with a divided block capacitor.
  • 55a shows a multiresonant inherently current-symmetrizing SEPIC converter in completely insulating form with a common blocking capacitor.
  • Fig. 1 shows the principle of the invention of the LED current balancing by means of a current-compensated choke, as they are used to attenuate common-mode noise so-called common mode interference in line filter.
  • the AC source supplies the current Ii, which is divided into two identical currents Icml and Icm2 by the current-compensated choke Lern. These are rectified by the rectifiers Rel and Re2.
  • the resulting direct currents lol and Io2 also have the same strength and feed the LEDs Dl and D2.
  • the DC currents lol and Io2 are inde ⁇ pendent that used in a very good approximation of the forward voltages Vol and Vo2 Diodes.
  • the voltage at the AC power source Vi adjusts itself according to the impressed current Ii and the rectifier arrangements used, including loads, ie light-emitting diodes.
  • Fig. 2 shows a concrete embodiment of the rectifier as unbalanced voltage doubler circuit.
  • other rectifier circuits such as a half-wave rectification, a balanced voltage doubler, or a multi-stage voltage multiplier circuit, also referred to as a cascade or Cockroft-Walton circuit, could be used.
  • Fig. 3a shows a further embodiment of the 2 Darge ⁇ presented in Fig. Circuit with widely varying loads at the two outputs are provided.
  • a light-emitting diode string consisting of two light-emitting diodes is now used at one output, whereas a single light-emitting diode at the second output can be temporarily short-circuited by means of the transistor Q1.
  • the control signal V can be realized via the pulse width modulator PWM dimming of the LED D2.
  • the power source is thereby with a sine wave generator with a frequency of 48 kHz and a series resistance of 50 Ohm realized.
  • the cases 1 to 3 are as shown in the table below. In cases 1 and 2, the transistor Q1 is turned off (0% duty cycle), whereas in case 3 the transistor is turned on (100% duty cycle).
  • the transistor Q1 is turned off (0% duty cycle)
  • case 3 the transistor is turned on (100% duty cycle).
  • a failure of a light emitting diode in such a circuit arrangement will be considered. If a light emitting diode with a short circuit, so all ande ⁇ ren LEDs from the circuit will continue to be operated at rated current, which is to be regarded as "optimal behavior in case of failure.” If, however, a light-emitting diode fails with an interruption, the voltage across this light-emitting diode rises to a multiple of the forward voltage and, moreover, all the other light-emitting diodes are operated with too low currents. Symmetrization is only partially given.
  • the high voltage over the defective light-emitting diode may otherwise be considered an advantage, as this is a detection of the defective light emitting diode greatly simplified and an automatic bridge this light emitting diode with ⁇ means of the existing anyway for dimming switch or Transistor allows.
  • ⁇ means of the existing anyway for dimming switch or Transistor allows.
  • FIG. 4 shows the section around the diode D2 from an extended circuit according to FIG. If the light emitting diode D2 by an interrupt, the comparator is on ⁇ due to the high voltage across D2, which is generated by the current-compensated choke, tilt, the set reset flip-flop when switching on the circuit, and thus Ql turn permanently.
  • Rectifier circuits Rel and Re2 including the included smoothing capacitors are omitted.
  • Fig. 6 shows such a circuit with light emitting diodes as a load. The result is a discontinuous current flow through the LEDs - only in the positive half-wave of the power source current flows through the two LEDs. In the negative half-cycle, the two LEDs lock.
  • the blocking voltage corresponds to the no-load voltage of the non-ideal current source.
  • Fig. 8a shows a first circuit variant A
  • Fig. 8b shows a second circuit variant B, in which manner the current-compensated reactors can be interconnected to supply a plurality of light-emitting diodes or light-emitting diode strands with the same currents.
  • Variant B has the advantage over variant A that, on the one hand, the number of outputs, if one requires the same current through all LEDs, need not be a power of 2 (at least if only 1: 1 chokes are to be used and the same Current through all light-emitting diodes demands) and on the other hand all current-compensated chokes must be designed for the same load current.
  • the current-compensated choke Lcm5 is optional and leads to a "ring closure", which improves the symmetrical distribution of the currents on the outputs.
  • ring closure improves the symmetrical distribution of the currents on the outputs.
  • FIG. 8c shows a concrete embodiment of FIG. 8b wherein the current-compensated inductor Lcm5 has been omitted and only simple half-wave rectifiers are used as rectifiers.
  • Fig. 8d shows a further specification of the scarf ⁇ tung variant B analog of Figure 8B, but without Lcm5, wherein an asymmetric doubler judge as DC and a half-bridge ZVS circuit is used for realizing the AC power source.
  • FIG. 8e Another embodiment of the circuit variant B according to FIG. 8b, but without Lcm5, is shown in FIG. 8e.
  • an asymmetrical doubler circuit is used as a rectifier and a class E converter for realizing the AC power source.
  • the Streuinduktivitä ⁇ th of the current-compensated chokes are used as resonant inductance.
  • FIG. 8f shows a variant C which is already known from the prior art, DE 10 2006 040 026 and WO 2005/038828 A2, for quay cathode lamps.
  • the variant C has the same advantages as the variant B, but n chokes are required.
  • Fig. 8a, 8b and 8f also allow different large flows through the light-rela ⁇ hung as light emitting diodes strands, but only a division of the LED currents in fixed Behaves ⁇ nissen is always possible. So are, for example, the current through the light emitting diode Dl and to the fifth through the light emitting diode D2 in Fig.
  • such an arrangement may in particular ⁇ sondere be advantageous for the operation of a plurality of light-emitting diodes of different types, for example, in a lamp, for example with a Combination of a warm white light source of high luminous efficacy through the combination of cold white light emitting diodes and red light emitting diodes, each with high luminous efficacy.
  • the circuit of Figure 10a is based on a choke-down converter consisting of an input capacitor Cl, a switching transistor Ql, a step-down inductor LI and a diode D3 to produce a pulsating direct current through the inductor LI.
  • This current is split by means of the current-compensated inductor Lcml on both rectifiers consisting of Dl, Cl and D2, C2 and finally provided to the two outputs of the LEDs Dil and D12.
  • One of the two light-emitting diode currents is thereby detected by means of the current measuring device Im and supplied to the control Crtl, which changes the duty cycle of the transistor Ql accordingly.
  • two outputs analogous to the above circuits, several outputs could be generated.
  • light-emitting diode strings could also be used instead of individual light-emitting diodes.
  • Fig. 10b shows a further development of the circuit of
  • FIG. 10 c shows a throttle-down converter with three outputs, wherein only the leakage inductances of the current-compensated throttles are used as storage chokes of the converter.
  • the current measuring means IMEA determines one of the output currents and provides an output current proportional to this and related to GND Messsig ⁇ nal.
  • the comparator Cmpl is used to detect the demagnetization of the current-compensated chokes Lcml and Lcm2.
  • the measurement signals In and F are supplied to the non Darge ⁇ easily control, which in turn generates therefrom the drive signal Dr for the power switch.
  • the control has been overridden and the transistor driven with a constant duty cycle of 50% and constant frequency in order to exclude effects by Regge ⁇ ment and the change of the duty cycle, and thus to examine the effect of balancing particularly simple can.
  • the switching frequency was varied in three series of measurements between 12, 24 and 48 kHz.
  • the input voltage was held constant at 10V and the load at the 2nd output changed, whereas at the 1st output (at 150 ohms) remained unchanged.
  • the choke LI has a value of 100 uH in this embodiment.
  • the current-compensated choke used is of the type EPCOS B82721-K2701-N20 with an inductance of 2x10 mH, a series resistance of 2x0.60 ohms and a rated current of 0.7A.
  • the curve 81 represents the function of the arrangement to the test - here the current-compensated choke has been replaced by two Wi ⁇ resistors, each 0.68 ohm, to illustrate what-balancing effect is achieved by the series resistance of the current-compensated choke alone.
  • FIG. 13 shows a particularly advantageous embodiment of the converter according to FIG. 10a.
  • the current measurement is evaluated by evaluating the voltage drop across the shunt Rs realized. More important, however, is the "saving" of the "actual buck converter choke” LI - instead, the two already existing leakage inductances Lsl and Ls2 of the current-compensated choke are used for this purpose. This measure also leads to a better symmetrization of the two output currents, as shown in FIG. 14.
  • FIG. 13 shows the transducer of FIG. 13 with current control disabled, as with all of the measurements given here, to show the extent to which the balancing of the output currents decreases with increasing output currents.
  • FIG. 15 shows the ratio of the two output currents Iol / Io2 above the mean output current (Iol + Io2) / 2. It can be seen that up to an average current of 350 mA, the "asymmetry" remains below 5%. This corresponds to half the rated current of 700 mA of the current-compensated choke used.
  • FIGS. 16 and 17 two inventive exporting ⁇ ⁇ insurance forms are sets Darge based on the Cuk converter concept.
  • the illustrated in FIGS 16a and 16b scarf ⁇ obligations use the capacitors C31 and C32 to a direct current flow, which would be established by the current-compensated choke due to the different output voltages to prevent.
  • the circuits of FIGS. 17a and 17b use the diodes D1 and D2 analogously to the realization in the throttle converters already described.
  • n capacitors and n diodes are required in the output circuits (C31, C3n and D31, FIG.
  • D3n D3n + 1 diodes
  • Figures 18a and 18b show two inventive from ⁇ EMBODIMENTS based on the SEPIC converter concept, wherein the Streuinduktivitä- th Lsl and Ls2 of the current-compensated choke L10 and L20 take in the embodiment of FIG. 18b, the object of the two throttles with.
  • FIG. 19 shows an embodiment of an inverter according to the invention, based on a switch-balanced half-bridge circuit with a resonant output circuit consisting of Lr, Crl and the optional Cr2, which realizes an alternating current source.
  • the half-bridge is zero-voltage switching. This alternating current source feeds an arrangement similarity ⁇ Lich disclosed in Fig. 8b through 8e.
  • Transistors Ql and Q2 have a fixed, time-invariant duty, ⁇ ie as not driven by a pulse width modulation. This is chosen so that Ql and Q2 are never simultaneously conductive. The duty cycles of the two transistors do not have to be the same size. Thus, Ql can have a duty cycle of 60% and Q2 a duty cycle of 35%.
  • the current control Ctrl uses the voltage drop across the resistor Rs to the desired target current through the light emitting diode D5, and thus set by all light emitting diodes, by changing the switching frequency of the transistors Ql and Q2. This target current may be set for example by a master controller of a lighting management system ⁇ (not shown).
  • rectifier circuits Rel to Re5 can not have a DC component. Therefore, only rectifier circuits make sense, which receive a pure alternating current at their input.
  • rectifier circuits used until LCM4 reliably prevents magnetic saturation of the current-compensated chokes ⁇ LCML.
  • rectifier cells based on the single-ended voltage doubler circuit as shown in FIG. 2 may be used.
  • Fig. 20b is another illustration of the inventive circuit according to Fig. 20a each current-compensated Dros ⁇ sel is replaced by an equivalent circuit consisting of a Trans ⁇ formator and two leakage inductances Ls.
  • the entirety of the leakage inductances Ls can completely take over the function of the resonance choke Lr, as is the case with the modified embodiment.
  • tion according to FIG. 20c represents.
  • the effect of the optiona ⁇ len resonant capacitor Cr2 is now achieved by the optional resonant capacitors CR21 to Cr25.
  • FIG. 21 a shows a modified variant of the circuit according to FIG. 19 or 20 a, which manages with reverse-blocking rectifier circuits.
  • the rectifier circuits are connected so that no DC component is caused in the current Ii, so that the DC current is ensured by the two capacitors Crl and Cr2.
  • Rel and Re4 are shown as half-wave rectifiers. In this case, Rel to Re3 and Re4 to Re6 have the same input current direction or polarity of the diodes used.
  • the advantage of this circuit variant is the symmetrical utilization of both half-oscillations provided by the bridge circuit and the property that only n-2 current-compensated chokes are required to provide n outputs and fewer diodes are required for the reverse blocking rectifier circuits than for the reverse-conducting rectifier circuits In addition, at a higher level of efficiency.
  • the circuit of FIG. 21a has the disadvantage that not all light-emitting diodes or light-emitting diode strands with the same connection, for example the cathode, can be placed on GND or the common reference potential, which leads to different effects when using similar light-emitting diodes be well cooled.
  • This is in particular ⁇ sondere in the case of high-power LEDs a big disadvantage.
  • the application of the circuit according to the figure 21a Therefore, in particular for low-power light-emitting diodes, such as radial light-emitting diodes, or arrays of these makes sense.
  • Fig. 21b shows another view of the circuit of Fig. 21a each current-compensated choke is replaced by an equivalent circuit consisting of a transformative ⁇ tor and two leakage inductances Ls.
  • the totality of the leakage inductances Ls can be the function of the resonance choke Lr completely take over, as this represents the modified Ausure ⁇ tion according to FIG. 21c.
  • the effect of the optiona ⁇ len resonant capacitor Cr2 is now achieved by the optional resonant capacitors CR21 and CR26. After the stray inductances of the current-compensated chokes are present anyway, a more cost-effective and more compact design can be realized in this embodiment.
  • 21d shows a further advantageous development analogous to the circuit arrangement according to FIG. 21c, but now with transformer Tr, which serves for electrical isolation and / or voltage adjustment. If appropriate, the leakage inductance of the transformer together with the entirety of the leakage inductances Ls completely assumes the function of the resonance choke Lr.
  • the current measurement signal is transferred in accordance with the secondary side to the primary-side part of the circuit by means of an opto-coupler circuit ⁇ Opto.
  • Fig. 21f shows a further advantageous development analogous to that of Fig. 21e, wherein the transformer Tr with two secondary windings nsl and ns2.
  • This circuit avoids the disadvantage that not all light-emitting diodes or light-emitting diode arrays with the same polarity can be designed with respect to the common reference potential, eg of the heat sink. Therefore, this circuit is particularly suitable for high-power LEDs.
  • the illustrated magnetic components can advantageously be integrated in a magnetic component, in particular in a ceramic component which is produced for example in LTCC technology.
  • the use of the stray inductances is particularly advantageous in the integration of a plurality of functionally different magnetic components in a magnetic component, since in comparison with conventional use of a plurality of discrete components, the integration results in comparatively large stray inductances and can now be used to advantage.
  • the construction of the current-compensated choke is advantageously to be realized in such a way that it has a defined leakage inductance and that the current-compensated choke does not saturate even at high current intensities.
  • constructions are ver ⁇ applies advantageously as AI are described in EP 0275499 Al and DE 36 21 573rd For use for lighting purposes, in particular an embodiment according to DE 3621573 AI appears advantageous.
  • DE 36 21 573 solves essentially the same task as EP 0 275 499 AI: It is presented the realization of a current-compensated inductor with large additional leakage inductance for the suppression of symmetrical interference.
  • EP 0 275 499 AI is in DE 36 21 573 does not use a separate "outer core" for each "outer” conductor, but only one outer core for all.
  • two air gapless ring cores are used for the current-compensated choke, wherein initially the first core is uniformly wound over the entire circumference in order to obtain a small external magnetic field. Then a second iron powder core of carbonyl iron is placed concentrically over this first ferrite ferrite core.
  • the second winding is wound through both ring cores having the same angular extension number and, optionally, a little thicker wire for moving ⁇ che copper resistances of the two windings.
  • a first embodiment of the control for the converter according to FIG. 10c is the pulse width modulation controller shown in FIG. He realizes a fixed-frequency Pulswei ⁇ width modulation.
  • This controller consists of the error amplifier Opl which generates the error signal Vea as a PID controller from the measured output current and the reference signal Vref associated with the reference current. This is compared in the PWM comparator Cmp2 with a ramp voltage.
  • PWM comparator Cmp2 In a conventional pulse width modulation controller outputs the generated signal P would be the gate driver DRV of the circuit breaker supplied ⁇ leads.
  • the additional logic FWC By means of the additional logic FWC, however, it is ensured that a demagnetization of the current-compensated chokes has taken place before the Q1 can be switched on again, ie if necessary, the on-time is cut off by the free-running signal F. If the actual PWM signal P goes to low, the RS flip-flop set by the falling edge. The RS flip-flop "notices", the circuit is in the demagnetization phase. would at this stage, the PWM signal back High ⁇ to, so would the AND gate a high will prevent the output Dr. Only when the demagnetization signal arrives in the form of a high of the measurement signal F, the FF is reset via the R input.
  • the timer Tmr is provided whose time value corresponds to the maximum conceivable demagnetization duration. If the FF longer than Zeitdau he ⁇ set, is the output of the timer on high and leads to an automatic resetting of the flip-flops. Engages the additional logic FWC, this means that the control loop is opened, and the actual controller Opl runs up to the limit so that a signal with maximum P ⁇ Tast is degree. However, this opening of the control loop and the associated deviation of the required output current from the setpoint is accepted in order to be able to ensure the balancing of the output currents.
  • the controller for the circuit of Fig also shown in Fig. 23 can. 10c are used, which ensures an operation on the DISCONTINUOUS (Boundary Conduction Mode), wherein neither Switching frequency still on or off duration are constant. In contrast to the above embodiment, it does not work with a constant switching frequency, but with a variable: As soon as the current through the inductor reaches zero, the transistor is switched on again.
  • the error amplifier and the pulse width comparator are realized as in FIG. 22 by means of Opl and Comp2. If a demagnetization of the chokes has taken place, the low-high transition of F causes the ramp generator Ramp to start generating a new ramp.
  • the timer Tmr is provided, the time value of which corresponds to the maximum conceivable demagnetization time. If the output is longer than this amount of time on low, a new ramp will generate ⁇ riert, and it will not wait for a low-high transition of F.
  • FIG. 24 shows a controller based on a current-mode control principle for the circuit according to FIG. 25.
  • This controller also implements an operation at the boundary boundary mode.
  • the control amplifier Opl produces at its output the signal Vea is compared with the refreshes ⁇ economic measured current value Im2. If the value of Im2 exceeds that of Vea, the high-to-low transition of P will cause the flip-flop to be reset and Q1 to be turned off. In the subsequent demagnetization phase, F initially remains high, since the current current value is greater than zero.
  • Fig. 25 illustrates another embodiment of a three output choke down converter.
  • the current measuring means IMEA is realized by a differential amplifier which lie ⁇ fert a the current to be measured learning proportional and related to GND measurement signal after the signal Im2 speaks the appropriately amplified and ground-based voltage drop across the shunt Rs corresponds.
  • the time average of the voltage drop across Rs corresponds to the time average of the sum of all LED currents.
  • the low pass LP is present.
  • the comparator Cmpl is used to detect the demagnetization of the current-compensated inductors Lcml and Lcm2.
  • the circuits according to FIGS. 22, 23 and 24 may be used
  • FIG. 26 shows a two-port throttle boost converter.
  • the actual boost converter consists of the storage inductor LI, the switching transistor Ql and the diodes Dl and D2.
  • the control takes place on one of the output currents.
  • a subordinate current control loop in the sense of a "current mode contol" are used, which pulls the switch current - detected by means of the resistor Rq - for control zoom ⁇ .
  • Lsl and Ls2 Leakage inductances of the current-compensated choke Lsl and Ls2 are undesirable in the boost converter because they lead to high voltage spikes when the transistor Ql is turned off: Lsl and Ls2 prevent the currents in the output circuits from 0 to the half current value of the inductor current by LI at the time of turn-off of the transistor can jump. Therefore, a snubber network should be provided, which limits the switch voltage. This may be implemented dissipatively in the form of an RDC network parallel to Q1, or as an optional terminal circuit for the transistor voltage of Ld and D3 and be non-dissipative.
  • the illustrated clamping circuit limits the switch voltage immediately after opening Ql to a value resulting from the ratio of the transformer formed by Ld and LI and the input voltage.
  • Ld and LI should be as well-coupled magnetic ⁇ table together. Assuming that the input voltage is 10V and Ld is twice as many turns as LI, the transistor voltage would be limited to a value of twice the input voltage, hence 20V, since then diode D3 starts conducting and the voltage on the transistor is stuck.
  • the buck converter In contrast to the buck converter, the buck converter has no restriction on continuous and continuous operation, at least as long as the stray inductances are negligibly small. Regardless of the operating mode is switched on while Ql is the current-compensated Demagnetized demagnetizer, the current through the stromkompen ⁇ - based throttle is thus zero and by the subsequent blocking of the two diodes Dl and D2 this condition is maintained until the next shutdown of Ql.
  • the Boost converter does not require any of the control circuits described above, because even if the converter operates continuously with respect to the inductor LI, it is always ensured, due to the topology, that the power distribution network is operated in discontinuous operation and consequently always demagnetization of the common mode chokes is given in the network.
  • FIG. 27 shows such a converter which, like the boost converter described above, includes an optional clamping circuit for the transistor voltage consisting of Ld and D3.
  • the current balancing is by the series circuit of a capacitor, an alternating current or alternating voltage source and two opposite of interconnected, backward lei ⁇ tender rectifier circuits, each including one or more series-connected light-emitting diodes, rea ⁇ larra.
  • Each of these circuits provides two common potential (eg, ground) related light outputs.
  • Figures 28a and 28b show embodiments of such circuitry.
  • the two figures show the circuit types WD and CD.
  • the circuit type WD is based on a voltage doubling circuit and the circuit type CD is based on a simple current smoothing circuit.
  • the operation of the circuit of Fig. 28a illustration ⁇ center the Figures 28c to 28e.
  • the assumption is made that all components are ideal, ie in particular the diodes behave as ideal switches.
  • the source Q works as a power source. If a positive current Ii is supplied by the source Q, then FIG. 28c shows the components relevant to the function: The current Ii flows through the diode Dil, then splits to Cll and Rl, and then via the ground connection drawn for the sake of easier understanding M, the diode D22 and the capacitor CO to flow back to the source.
  • the load R2 is ver provides ⁇ during this time range by the capacitor C2.
  • the magnitude of the current Ii> 0 has only an influence on the load current II, but not on 12.
  • FIG. 28d illustrates that the loads R1 and R2 are supplied with energy by the associated capacitors C1 and C2, respectively. After the capacitor voltages VI and V2 are positive, divides the respective capacitor voltage across the two diodes Dil and D12 or D21 and D22 and lock all diodes.
  • Fig. 28e correspondingly shows the relevant components in the case that the source Q provides a negative current.
  • the behavior of the two rectifiers is exactly the opposite: For Q, only GR2 is effectively present, whereas GR1 is not visible.
  • the magnitude of the current Ii ⁇ 0 has only an influence on the load current 12, but not on II.
  • FIG. 28f shows exemplary current and voltage curves of the circuit according to FIG. 28a
  • V12 (t) Vi (t) + V0 (t) + V22 (t).
  • the AC or AC voltage source is formed by the secondary winding of a transformer, as this is a particularly simple way to produce a potential-free source.
  • FIG. 28g shows the basic circuit diagram of a circuit ⁇ arrangement for balancing the two load currents II and 12 by the self-adjusting DC voltage V0 across the capacitor CO in the supply voltage path at a back ⁇ downward blocking rectifier GR1 and a forward blocking rectifier GR2 with a simple voltage output (circuit type VD) in parallel.
  • the capacitor CO suppresses a DC component in the supply current Ii. Since Vi is a pure AC voltage source, the sum of the voltage across the AC voltage source Vi and the voltage across the capacitor CO may contain a DC component. This proportion corresponds to the actual voltage difference of the two rectifiers GR1 and GR2. Since one rectifier blocks forward and the other rectifier blocks backwards, each rectifier is supplied with one half-wave of the alternating current Ii.
  • FIG. 28k shows the block diagram of a circuit arrangement for balancing the two load currents II and 12 by the self-adjusting DC voltage VO across the capacitor CO, which is connected between the voltage source and the reference potential, in a reverse and a forward blocking rectifier with a simple voltage output (circuit type VD) in parallel.
  • the operation of this circuit arrangement is equal to the operation of the circuit arrangement according to FIG. 28g.
  • the capacitor CO is inserted elsewhere in the current path, but this does not affect the operation.
  • Fig. 28h shows the phase diagram of Fig. 28k for the case Ii>
  • Fig. 28j the
  • a transformer having a plurality of secondary windings, and in particular for very different loads or light-emitting diodes additional current-compensated reactors, which balance the secondary currents with each other,
  • the primary side of the transformer is controlled by one of the usual power electronic circuits, such as a half-bridge, full bridge, push-pull or Class E converter.
  • this is a switch-relieved circuit that uses the ZVS or ZCS principle.
  • inductive components transformers, current-compensated chokes or a combination of such components
  • circuit type CD the required inductances (e.g., LI, L2 in Figure 2b) may also be integrated (e.g., with the required transformer).
  • balancing capacitors e.g., CO
  • LTCC LTCC
  • the rectifier switch can be designed as a synchronous rectifier, in particular, the already existing in the circuit transformers for driving the semiconductor switches of the synchronous rectifier can be used.
  • FIGS. 29a, 29b, 29c and 29d and FIGS. 30a, 30b, 30c and 30d show a circuit configuration in which a ZVS-powered half-bridge supplies a plurality of light-emitting diodes or light-emitting diode strings with the same current in all cases.
  • the capacitor Cr2 may be present.
  • FIGS. 29a, 29b, 29c and 29d according to the above Enumerated in item a) uses a plurality of transformers, whereas the figures 30a, 30b, 30c and 30d depending Weil ⁇ a circuit according to point b) indicates.
  • the circuits according to FIGS. 29a, 30a are based on the circuit type WD (analogous to FIG.
  • FIGS. 29b, 30b are based on the circuit type CD (analogous to FIG. 28b).
  • Figures 29c and 30c show circuits on the circuit type VD analogous to FIG. 28k ba ⁇ Sieren, whereas the FIG 29d is a mixed form, wherein each group of two .. to a secondary winding of a transformer Tri Tr3 connected rectifier respectively according to one of described above, the group of transformer TRI according to the circuit type CD, the group of transformer TR2 after the
  • Circuit type WD and the group of transformer TR3 to the circuit type VD.
  • Fig. 30d the situation is analogous to Figure 29d, only a common transformer is used with a primary winding and three secondary windings, in which the group at the first secondary winding (counted from above) to the circuit type CD, the group at the second secondary winding according to the circuit type WD, and the group working on the third secondary winding according to the circuit type VD.
  • light-emitting diodes or light-emitting diode strands were shown as the load of the rectifier GR, which lie with the cathode at GND. This need not necessarily be the case - it can also be the anode at appropriate
  • Circuit adaptation to be placed on GND This could be particularly advantageous if the housing of the LEDs used in each case ver ⁇ tied with the anode of the LED chip, since then all the LED housings are placed on a common electrically connected to ground heat sink can, which leads to a particularly good cooling of the LEDs.
  • Fig. 31 shows a circuit configuration in which a transfor ⁇ mator with two secondary windings) is used for the operation of light-emitting diodes 4 outputs corresponding to the point b in the above list.
  • Trl2 By means of the current-compensated choke Trl2 the symmetrization of the two secondary currents is ensured.
  • the elec tronic switches ⁇ Sil be controlled reasonable to S41 with a PWM signal.
  • Table 1 below shows the ratios at 0% or 100% duty cycle of the switches.
  • the resistors Rl to R4 are for current measurement, but not required for the actual function. The following components were used:
  • Trl2 Current-compensated choke EPCOS B82721-K2701-N20, 2xl0mH, 2xOR60 typ. RDC
  • Fig. 32 shows the "front" part of the circuit of Fig. 31, however, a class-E converter is now considered generator. This has to dispense with the advantage of having a single Leis ⁇ tung transistor Ql and also is this with ZVS (Zero Voltage Switching) Contrary to the usual disadvantage of the class E converter one with others
  • Nonlinear behavior cause a flattening of the drain oscillation, so that a transistor with less
  • Power distribution network which contains one or more current-compensated chokes in a basic interconnection of FIG.
  • the additional capacitors prevent a DC current flow through the current-compensated chokes, so that the current-compensated chokes are flown through only by alternating current which, at least in each zero crossing of the current allows a voll Dicki ⁇ ge demagnetization of the throttles, which for their operation is crucial.
  • transducer structures are used which do not have a DC current path through the current-compensated inductor, ie the arithmetic mean values of the currents Icm1 and Icm2 in FIG. 1 are zero due to circuit-engineering measures.
  • at least two capacitors are used in each case in series with one of the three terminals of the current-compensated choke as DC-blocking components. That means the realization according to the invention. tion has one of the possibilities shown in Fig. 34 A) to C) as part of the converter.
  • the resonant cells shown in Fig. 34 contain at least 2 capacitors, may be part of the AC or rectifier and can perform next to the DC-blocking function more functions in the associated AC or rectifier.
  • the capacitor In a half-bridge inverter, the capacitor may have the role of the resonance capacitor.
  • this capacitor In rectifiers of the type of unbalanced doubler or cascade circuits, this capacitor is the input capacitor or the first capacitor of the thrust column.
  • FIG. 35 The combination of possibilities A) to C) from FIG. 34 is shown in FIG. 35, wherein the current-compensated inductor through the equivalent circuit consists of two fixedly coupled (with a coupling factor of one) inductances Ltl and Lt2 and the two leakage inductances Lsl and Ls2 is shown.
  • the two capacitors C 1 to C 3 can be dispensed with, without the inherent direct current freedom being influenced by the two windings of the current-compensated throttle. This freedom from DC current is not influenced by further, arbitrarily insertable in the circuit condensers ⁇ .
  • Fig. 35 shows optional capacitors Cr (dashed), the example against
  • capacitors are shown grounded. These capacitors are advantageously resonance capacitors which, together with the leakage inductances Ls1 and Ls2, act and can be used, for example, for switching relieving within the converter.
  • any components in series with the windings of the current-compensated choke and the capacitors can be switched.
  • the series connection of the windings of one or more further current-compensated chokes makes sense, if the converter should have more than two outputs.
  • Fig. 36 shows a practical case of a very general building block.
  • FIG. 37 shows the circuit according to FIG. 2, which also contains the resonant cell structure. This was drawn for illustration and labeled CCC1.
  • circuits according to FIGS. 3 and 5 are based on the same circuit principle, these also contain the corresponding configuration.
  • converters which contain such a configuration are, in addition to the half-bridge converters shown in FIG. 8d, also the class E converters indicated in FIG. 8e.
  • FIG. 38 shows a ZVS half-bridge converter which uses the leakage inductances of the current-compensated reactors as resonance inductance.
  • FIGS. 39a, 39b and 39c show the basic circuits of a step-down converter or buck converter (FIG. 39a),
  • a boost converter or boost converter (Fig. 39b) and a Cük converter (Fig. 39c).
  • the latter can produce output voltages whose magnitude can be smaller or larger than its instantaneous input voltage.
  • All three topologies belong to the group of single-switch DC-DC converter. Shown in each case is their hard-switching variant, whose inverter switches are controlled by known pulse width modulation methods. Not shown in each case are the details for controlling the inverter switch Ql or Sl and the controller structure, which returns certain output variables for driving the inverter.
  • the current measuring resistor RS is indicated.
  • the stray inductances form the inductive part of a resonant circuit, which is tuned to the Be ⁇ drive frequency.
  • Each current-compensated choke also has a non-compen ⁇ overbased scatter fraction, based on this fact, the OF INVENTION ⁇ dung.
  • the circuit arrangement is further develop according to the Fig. 39c for a plurality of light emitting diodes strands insert the current ⁇ compensated choke where the Cuek converter required as a condition for zero voltage switching an inductor, eg at the location of Induktivi ⁇ ty LCML.
  • the stray inductances of the at least one current-compensated choke are used to produce resonant circuits, which make it possible to operate the power switch switchboard ⁇ relieved within the converter circuits.
  • the above-mentioned common inverter basically consists of only one electronic circuit breaker and at least one storage inductor.
  • the Leis ⁇ processing circuits may contain an uncontrolled anti-parallel diode (inverse diodes), and is driven by means of a special frequency variable, and state-dependent PWM.
  • the abovementioned current-compensated choke is expressly not to be regarded as a storage inductance.
  • the inventively more rectifier contain as many diodes as light-emitting diode strands are provided. So with N light-emitting diode strings exactly N rectifier diodes can be found.
  • the number of already mentioned memory inductances in Buck, Boost or Drosselin topology is also exactly N, in Cuk, SEPIC or
  • all converters presented here operate in all their branches in "Double ZVS Multiresonant Conduction Mode.”
  • Advantageous in this mode of operation is the resonant switching relief of all switching edges of all participating rectifier diodes and the switch-on edge of the inverter switch three transducers with current output (Buck, Cuk and Zeta) are omitted for feeding light-emitting diodes of the otherwise conventional output filter capacitor, which in particular facilitates the controllability of a possible higher-level lighting system.
  • the resonance cell comprises, in addition to the at least one current-compensated choke, at least N capacitors in series with the terminals of the current-compensated choke.
  • the current-compensated choke is always inserted where, in the transition of a hard-switching CCM into a multiresonant double ZVS single-switch converter, the additional resonance inductance is connected.
  • the series capacitors to the left or right thereof are either already present in the intended converter topology, or they are also newly added as N resonance capacitors in each case parallel to one of the N rectifier diodes. If so not directly apparent, the series connection to the current-compensated choke remains in this configuration.
  • the capacity of this new N "rectifier capacitors" is respectively approximately the same.
  • it is parallel to the inverter switches, a further resonance capacitor, the so-called inverter capacitor, connected in.
  • the capacity ratio between this Wech ⁇ selrichterkondensator and the sum of all N rectifier capacitors forms an important design criterion for this multi-resonant converter ,
  • N rectifier diodes within the considered transformer topologies for N current-symmetrizing outputs, at least N storage inductances are always present, as already described above.
  • block or filter capacitors are used, which can then charge differently to the different output voltages per branch.
  • the multiresonant transducers are not operated with constant, but with variable frequency to control the output power, which in turn contributes to the improvement of their EMC.
  • Fig. 40 shows a multi-resonant Cük converter expanded as described above.
  • the circuit according to FIG. 39c has been expanded by the resonance elements C1, C1 and C21, which are located parallel to the zero-voltage switched switch S and the diodes D10 and D20.
  • the resonance elements C1, C1 and C21 which are located parallel to the zero-voltage switched switch S and the diodes D10 and D20.
  • Inductors for resonance circuits which accomplish the relieves ⁇ te switching, as a current-compensated choke in the form of the two leakage inductances Lsl and Ls2 are formed.
  • Block capacitors C10 and C20 form a resonant cell with Lcml.
  • the following table shows an example dimensioning and the operating data, which correspond to the current and voltage curves according to Figure 3:
  • Fig. 42 shows a multiresonant SEPIC converter with two inherently symmetrizing outputs.
  • the corresponding multiresonant zeta converter is shown in FIG. 43.
  • corresponding capacitances are to be connected in parallel to all switches (ie transistors and diodes), so that the resonant cell with the corresponding resonant circuits for ⁇ together with the leakage inductances of the current-compensated inductor the switching relief results.
  • Fig. 44 shows a Class E converter with hard-switching rectifier diodes at the output. These were also added by adding parallel capacities into a corresponding multi-resonance Class E converter according to FIG. 45.
  • Rectifier diodes In contrast to the Cük converter in the Class E converter, the inverter capacitor Cl and a resonant matching network in front of the rectifier, which is exactly out of resonance here, have always been fixed circuit components, which is why rectified from an approximately ideal sinusoidal out, which is natural ⁇ Lich can happen in both polarities. It is not visible that in the class E converter, the capacitors CIO and C20 have much smaller capacitances than in the Cük converter, since in the former they are supposed to act as resonance elements, in the latter "only” as blocking capacitors.
  • FIG. 46 shows the multiresonant, inherently current-symmetrizing buck converter or step-down converter
  • FIG. 47 shows the corresponding boost converter or step-up converter
  • FIG. 48 finally shows the corresponding inductance converter.
  • FIG. 49 shows a multiresonant Cük converter with 4 inherently current-symmetrizing outputs in tree connection of the three current-compensated reactors.
  • the current load between LCML ... LCM3 is balanced on average, but "see" the two central output branches definitely more series inductance than that in ⁇ the outside. This can be resolved by the points C and D and the points e and F are respectively short-circuited by the two connections between G and C as well as between H and F may be omitted and, then, however, be noted that LCML is faced with the dual power Bela ⁇ tung current-compensated compared to the two nachge ⁇ switched Chokes Lcm2 and Lcm3 Fig.
  • the ratio between the capacitances of Cll and C21 must also be 3: 5, that between the capacitances of the blocking capacitors CIO and C20 can be 3: 5, that between the filter inductances L10 and L20 can conversely be 5: 3.
  • FIG. 52 shows the insulating variant of the choke inverse converter, the multiresonant inherent current-symmetrizing flyback converter.
  • FIGS. 53a and 53b show corresponding Ciik converters
  • FIGS. 54a and 54b show insulating multiresonant zeta converters
  • FIG. 55 shows the insulating multiresonant zeta converters
  • Cük- Due to its topological symmetry of Cük- takes converter according to Figure 53a and 53b a special position: they can only by splitting its blocking capacitor CIO, C20 in a primary-side C9 and in the secondary-side CIO, C '20 and by inserting a transformer Tl precisely at this newly formed nodes are isolated. Therefore, only in Cük converter in its insulating form, the two components C9 and Tl newly added. However, only there Tl is claimed purely AC moderate. Theo ⁇ cally to SEPIC and Zeta were isolated as well. With the SEPIC, however, a circle of transformer secondary winding, block C and storage coil would then emerge.

Landscapes

  • Dc-Dc Converters (AREA)
  • Circuit Arrangement For Electric Light Sources In General (AREA)
  • Led Devices (AREA)

Abstract

L'invention concerne une circuiterie pour faire fonctionner au moins deux sources lumineuses à semi-conducteur, présentant : - un convertisseur d'énergie électrique pourvu d'au moins un commutateur, le convertisseur d'énergie électrique fournissant une tension continue pulsée ou une tension alternative, - au moins deux branches de fonctionnement dont chacune présente un redresseur non conducteur ou court-circuitant dans un sens de courant, et pourvu d'une borne d'entrée, d'une borne de sortie et d'un potentiel de référence, - lesdites branches de fonctionnement étant couplées au convertisseur d'énergie électrique, - au moins un self de mode commun qui est monté entre le commutateur et lesdits au moins deux redresseurs, au moins deux sources lumineuses à semi-conducteur qui sont respectivement montées entre les bornes de sortie du redresseur associé et son potentiel de référence, le convertisseur d'énergie électrique étant conçu comme un convertisseur à résonance doté d'une cellule à résonance, et l'inductance de fuite du self de mode commun étant utilisée comme inductance à résonance de cette cellule à résonance.
EP11767401A 2010-09-29 2011-09-23 Circuiterie pour faire fonctionner au moins une source lumineuse à semi-conducteur Withdrawn EP2526738A1 (fr)

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DE102010041632A DE102010041632A1 (de) 2010-09-29 2010-09-29 Schaltungsanordnung zum Betreiben mindestens zweier Halbleiterlichtquellen
PCT/EP2011/066606 WO2012041783A1 (fr) 2010-09-29 2011-09-23 Circuiterie pour faire fonctionner au moins une source lumineuse à semi-conducteur

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CN (1) CN103155703A (fr)
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WO2012041783A1 (fr) 2012-04-05
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