EP2409327A1 - Vertikal kontaktiertes elektronisches bauelement sowie verfahren zur herstellung eines solchen - Google Patents
Vertikal kontaktiertes elektronisches bauelement sowie verfahren zur herstellung eines solchenInfo
- Publication number
- EP2409327A1 EP2409327A1 EP10712326A EP10712326A EP2409327A1 EP 2409327 A1 EP2409327 A1 EP 2409327A1 EP 10712326 A EP10712326 A EP 10712326A EP 10712326 A EP10712326 A EP 10712326A EP 2409327 A1 EP2409327 A1 EP 2409327A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- contact
- insulating layer
- opening
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
Definitions
- the invention relates to an electronic component which is vertically contactable, i. which is contactable via bonding and / or solder contacts, which are above those active areas of the device, which are contacted by the corresponding contacts.
- the invention also relates to a method for producing such a device with vertical contacting.
- Discrete electronic semiconductor devices In the production of electronic semiconductor devices, the production costs are reduced, inter alia, by miniaturization of the surface geometry / chip geometry, since the number of components increases for a given wafer or substrate surface due to the miniaturization.
- Discrete electronic semiconductor devices usually have two or more contacts for electrical contacting, which are wired into housings or modules by means of different technologies, such as bonding, soldering and / or flip-chip technology.
- the location and placement of the contacts is different. Due to the position and placement of the contacts basically two groups of electronic semiconductor devices can be formed.
- the electronic semiconductor components in which the contacting takes place both on the front side and on the rear side of the component (“vertical component”.)
- the term is to be distinguished from a "vertical contact”, which is possible with vertical and lateral components is.)
- the required area of the contact zone in the active region of a component is many times smaller than the bonding surface or soldering area required for contacting, via which the component is wired, for example, to a housing.
- the bonding surfaces or soldering surfaces for wiring the component therefore occupy unusable substrate or wafer area.
- This problem comes into play.
- One way to reduce the size of the component or reduce the unusable area is to place the bonding surfaces or pads not laterally to the active zone, but, with corresponding technology, directly over the active zone of the component, provided the active zone has one sufficiently large area.
- an electronic semiconductor component normally has a large number of identical individual components which are connected in parallel at the substrate or wafer level.
- the parallel connection of the individual components is effected by the corresponding connection and connection of the respective contacts.
- several hundred individual components can be interconnected to form a single component. Due to the interconnection of the individual components, the area of the active zone increases. This results in a size of the active surface which is suitable and usable for bonding surfaces or soldering surfaces on the active zone.
- the leads cross the contacts of the device. That is, that the contact distance to the line must be so large that there is no electrical breakdown. The distance or breakdown is determined by the dielectric layers.
- this layer must be very thick
- An electronic component according to the invention initially has a contact surface which lies in a contact plane.
- the contact surface may be, for example, the surface of an active zone or an upper surface of a metallization or layer on such an active region of a semiconductor device be.
- the contact surface is that region or surface to which an electrical contact is to be made via a bonding contact and / or a solder contact.
- the electronic component further has an insulating layer which lies on, above or above the contact surface and / or the contact plane. Defining a direction perpendicular to the contact surface as above, this means that the insulating layer is located higher than the contact surface. It is possible, but not necessary, for the insulating layer to also be arranged over a part of the contact surface, which means that a vertical projection of the insulating layer onto the contact plane falls on a part of the contact surface. However, the insulating layer may also end just above the edge of the contact surface and be present only where it is not above the contact surface.
- At least one stabilizing layer is now arranged on and / or above the at least one insulating layer according to the invention.
- the stabilizing layer is preferably arranged directly on the insulating layer.
- At least one opening is provided which extends through the insulating layer and the stabilizing layer to the contact surface. These openings thus correspond to openings in the insulating layer and openings arranged in the stabilizing layer over this.
- a passage direction of the opening is preferably perpendicular to the contact surface.
- the device according to the invention furthermore has at least one bonding contact and / or a soldering contact which extends above and / or on the stabilizing layer and extends through the at least one opening up to the contact surface and contacts and electrically contacts it.
- the bonding contact or soldering contact thus covers at least a portion of a surface or upper side of the stabilizing layer and also covers the contact surface at least in some areas.
- An underside of the bonding contact or of the solder contact facing the contact surface preferably follows the surface of the immediately underlying layers, i. the surface of the stabilizing layer, the sidewalls inside the opening and the contact surface.
- At least one bonding wire or a solder wire can then be attached to a surface of the bonding contact or of the solder contact facing away from the contact surface.
- the arrangement according to the invention makes it possible to place bonding surfaces or soldering surfaces of an electronic component over an active zone, ie the contact surface.
- the insulating layer ensures insulation between the contact surface or active zone and the bonding surfaces or the soldering surfaces.
- the opening allows through-contacting of the contact surfaces, for example on an active zone, to the associated bonding surfaces or soldering surfaces through the insulating or dielectric layer and the stabilizing layer.
- the stabilizing layer ensures the mechanical stability necessary is to attach bonding wires or solder wires to the bonding surfaces or solder pads can.
- Both the insulating layer and the stabilizing layer can layer systems with a
- the insulating layer is arranged over the contact surface at least in regions, at least one passivation layer or a passivation layer system is arranged between the insulating layer and the contact surface, which particularly preferably completely separates the contact surface from the insulating layer
- the said opening also extends in this case through the passivation layer or the passivation layer system, so that the bonding contact or solder contact is in contact with the contact surface.
- the passivation layer is preferably arranged directly on the contact plane or contact surface, and / or the insulating layer directly on the passivation layer or the contact plane or surface.
- the stabilization layer is preferably arranged directly on the insulating layer.
- the bonding contact or soldering contact is preferably arranged directly on the underlying stabilization layer, opening wall and / or contact surface.
- a layer thickness of the insulating, ie dielectric layer is preferably ⁇ 100 nm, preferably ⁇ 120 nm, more preferably ⁇ 200 nm, particularly preferably 300 nm and / or ⁇ 600 nm, preferably ⁇ 500 nm, particularly preferably ⁇ 400 nm.
- the at least one opening is designed so that its cross-sectional area and / or its diameter, starting from the contact surface, increases upward, preferably strictly monotone and continuous.
- the walls of the opening can be inclined at an angle with the contact plane of ⁇ 90 ° to the outside.
- the walls are in this case funnel-shaped and / or the flanks of the opening can be positive or have a positive profile.
- the cross-sectional area of the opening increases towards the top, it can be ensured that the opening is completely filled with the material of the bonding contact or of the soldering contact when the bonding contact or the soldering contact is made, or a laminar bonding contact or soldering contact on one Wall of the opening is applied, without forming between the wall and the bonding contact or soldering holes.
- the cross-sectional area of the opening may be circular, rectangular, square or in other shapes.
- a hardness of the material of the stabilizing layer is greater than a hardness of the material of the insulating layer. This ensures that the stabilizing layer leads to an overall more stable layer system than would be the case without a stabilizing layer with only the insulating layer.
- Possible materials of the dielectric layer or of a dielectric layer system are inorganic materials such as SiN, SiO 2 , metal oxides, metal nitrides, Al 2 O 3 , TiO 2 , TiO 3 on the one hand, but also organic and / or polymer-based materials such as benzocyclobutenes (US Pat. BCB).
- BCB has the advantage that it is present as a solution / liquid and, for example, a photoresist can be spin-coated onto the samples and then baked. So you can relatively easily produce several micrometers thick high-quality dielectric and insulating layers. You do not need any complex equipment for deposition, such as for SiO 2 or SiN.
- Structuring / etching is preferably carried out analogously to the other dielectric layers.
- Another advantage of the BCB is that it has a planing effect due to the application and the general properties of the BCB. Every height difference in the process topology is smoothed after the BCB process. Because BCB is elastic, it does not generate internal stresses.
- the problem with the use of polymer-based materials for the dielectric layer is that they are mechanically less stable than inorganic materials, which makes it difficult or impossible to attach the bonding wires or soldering wires to the bonding surfaces or soldering surfaces.
- a good connection between bonding wire or solder wire and bonding surface or bonding pad (soldering surface or solder pad) presupposes that the wires are applied to the bonding layer or soldering layer with a sufficiently high pressure. Is the insulating layer plastically deformable, as with polymer-based materials the case is, then the connection between wire and surface is only incomplete or not at all.
- the stabilization layer according to the invention solves this problem.
- the stabilizing layer is applied, which is preferably made of a harder material than the insulating layer.
- the application can be carried out directly after the thermal stabilization of the plastically deformable material.
- the deposition temperature of the stabilizing layer may exceed a curing temperature of the insulating layer.
- the stabilizing layer may comprise or consist of, for example, SiN and / or SiO 2 .
- a passivation layer which may be present may also comprise or consist of SiN and / or SiO 2 .
- the electronic component according to the invention is a semiconductor device.
- the invention is applicable to all known semiconductor devices. However, it is particularly preferably applicable to semiconductor components which have at least one nitride of a group III substance, particularly preferably GaN, since these are used primarily in power electronics, where numerous components are contacted in parallel in a space-saving manner by means of the vertical contacting according to the invention can be.
- the device according to the invention may be a component with one, two, three or more contacts.
- Each contact corresponds to a contact surface which can be contacted by a respective bonding contact and / or soldering contact. But it can also a plurality of contact surfaces are contacted by means of a common bonding contact and / or soldering contact, if they have the same function or should be electrically connected.
- Each contact surface preferably has its own opening in the layers arranged above the contact surface.
- Particularly advantageous component of the invention may be a diode having two contacts or contact surfaces, which are contacted via two electrically insulated from each other bonding contacts and / or solder contacts.
- the device according to the invention can also be a transistor with three contacts, namely drain, gate and source, which are contacted in each case via a separate bonding contact or soldering contact.
- the insulating layers of the device may be fabricated via one or more of the following processes: chemical vapor deposition (CVD), plasma assisted chemical deposition (PECVD), mechanical processes such as sputtering, sputtering, or other thermal processes, such as sputtering. Evaporation or other, as well as by spin coating or spraying. A possibly existing passivation layer can also be applied by means of these methods.
- CVD chemical vapor deposition
- PECVD plasma assisted chemical deposition
- mechanical processes such as sputtering, sputtering, or other thermal processes, such as sputtering.
- Evaporation or other as well as by spin coating or spraying.
- a possibly existing passivation layer can also be applied by means of these methods.
- the openings described are preferably produced prior to the application of the bonding contacts or solder contacts.
- Such openings may be selected by the stabilizing layer and the insulating layer particularly preferably by one or more methods selected from the methods reactive ion etching, physical removal of the corresponding the layer, inductively coupled plasma etching and / or evaporation of the corresponding material by means of laser light.
- a profile is produced, which ensures that the openings can be filled or coated in particular at their side surfaces without gaps with the bonding or soldering contact.
- the profile of the holes for this should be a positive profile, i. that the hole diameter increases from below the opening to beyond the opening.
- Opening wall with a corresponding coating with the material of the bonding or soldering contact on the surface of the stabilizing layer is in electrical contact and is preferably formed continuously with this.
- the described profile of the openings with non-perpendicular sidewalls can be adjusted by suitable choice of the process parameters, such as the appropriate choice of gas, pressure, gas flow, acceleration voltage, RF power and / or inductively coupled plasma power.
- Multi-stage etching processes are particularly suitable for the production of such openings, wherein after etching of the uppermost layer, the underlying layer is etched in such a way that during this step the upper layer is etched Further etched layer is etched, so that upon further penetration of the etching process in the layer system, the uppermost layers are etched the most and each one higher up layer is etched further than a layer further down. In this way, an opening is formed whose opening area decreases downwards.
- certain parameters of the process may be varied to achieve the desired functionality of the insulating layer and the stabilizing layer.
- plant-specific variations of production parameters such as gas flows, gas partial pressures, ICP powers, RIE powers, process temperatures, etc. are possible.
- composition of gases used it is also possible to vary the composition of gases used, provided that the results achieved in the process are comparable.
- the reactive compo- te of the molecules, such as fluorine in the varied gases available more (eg rejection of CF 4 to C x F y), and in a similar manner in the plasma, preferably at a comparable RF Performance, process temperature and gas pressure, into its individual components (in this case, carbon and fluorine) can disassemble.
- the passivation layer can be deposited and then patterned. Subsequently, the dielectric layer, e.g. from BCB, and then the stabilizing layer are applied. Thereafter, the openings can be etched.
- the passivation layer is first deposited but not patterned. Subsequently, the dielectric Layer and the stabilizing layer applied. Thereafter, the openings are made through all three layers, for example, etched.
- the openings can be produced by means of a three-stage dry etching process, which first etches the stabilization layer, then the insulating (dielectric) layer and finally the passivation layer.
- the manufacturing process can also be realized by using individual processes.
- the described profile of the openings can be produced in a number of independent individual processes, for example by individually structuring and etching each individual applied layer.
- these layers can be patterned by means of temporarily applied, for example lithographically structurable, layers for layout specification with subsequent etching of the layer and the stabilizing layer in a corresponding manner.
- the temporary masking layer is removed before the application of the overlying layer of the semiconductor component.
- the layers of the component according to the invention are themselves photosensitive, as is the case, for example, with BCB.
- the layers themselves can be structured by means of lithography processes.
- the insulating layer may have photosensitive BCB, which is then patterned by means of lithography.
- the stabilizing layer is applied, for example, of SiN over the entire surface and temporarily applied a lithographically structured photoresist. In a dry etching process, the stabilizing Layer are etched so that suitable inclined opening walls result.
- the device according to the invention may preferably have a two-port device or a three-port device, such as a two-port device. a diode or a transistor. It may, however, also be a complex semiconductor device, e.g. used in power electronics. It is particularly advantageous to realize group III nitride-based diodes and transistors. Especially for the realization of energy-efficient systems, Group III nitride-based Schottky diodes and transistors which have the structure according to the invention have a low power loss and thus distinct advantages. Such diodes and transistors may e.g. in high-frequency switched-mode power supplies, in efficient inverters in hybrid drive technology or in solar technology.
- FIG. 1 shows a laterally contacted component in which the bonding surfaces or soldering surfaces are arranged laterally to an active zone
- FIG. 2 shows a vertically contacted component in which two bonding surfaces are arranged above an active zone
- FIG. 3 shows a cross section through two embodiments of a layer system as used in the component according to the invention can come
- FIG. 4 shows a component according to the invention with three
- FIG. 1 shows a laterally contacted electronic component in which an active zone 6 is contacted by means of a first bonding and / or soldering surface 1 and a second bonding and / or soldering surface 2, which are arranged next to the active zone 6. Because the bonding surfaces 1 and 2 can not be arranged above the active zone 6, the total area of the component on a substrate 5 is determined by the sum of the bonding surfaces 1 and 2 and the surface of the active zone 6. In the example shown, bonding and soldering contacts can be realized analogously.
- an electrical contact is established through the contacts 3a and 3b.
- an electrical contact is established by means of the contact surfaces 4a and 4b.
- the contact surfaces 3a, 3b, 4a, 4b terminate at a side edge of the corresponding bonding surface 1 or 2 and contact a contact surface of the active zone 6 from above.
- the contacts of a bonding surface 1 with those contacts of the bonding surface 2 are arranged nested.
- FIG. 2 shows an alternative contacting of an active zone 6 via bonding pads 1 and 2, as can be used in the component according to the invention.
- the bonding surfaces 1 and 2 cover the active zone 6 at least in regions.
- the bonding surfaces 1 and 2 are thus at least partially over the active zone 6 is arranged.
- the area claimed by this arrangement on a substrate 5 and thus the area or size of the component per se can be made considerably smaller than in the example shown in FIG.
- An arrangement as shown in FIG. 2 requires a vertical contacting technique which makes it possible to electrically connect the active zone 6 under the bonding surfaces 1 and 2 to the bonding surfaces 1 and 2.
- the component can be designed according to the invention.
- FIG. 3 shows two embodiments of a layer system, as may be present in the device according to the invention.
- a layer system is first shown in which a passivation layer 7 is initially arranged over a contact surface 6, on which in turn directly a dielectric insulating layer 8 is arranged.
- a stabilizing layer 9 is arranged on the insulation layer 8 then immediately a stabilizing layer 9 is arranged.
- the passivation layer 7 and the stabilization layer 9 is a SiN layer, while the dielectric layer 8 is a polymer layer of BCB.
- Other materials for the passivation layer 7 and the stabilization layer 9 may be, for example, SiO 2 .
- the insulating layer 8 may comprise, for example, inorganic materials such as SiN, SiO 2 , metal oxides, metal nitrides, Al 2 O 3 , TiO 2 and / or TiO 3 .
- an opening 13 is now generated in the examples shown in Figure 3, which may be formed for example by reactive ion etching, physical removal of the material, inductively coupled plasma etching, evaporation by laser light or the like.
- walls are 11 the opening in the left partial image perpendicular to the contact surface 6, while they have a positive profile in the right partial image, so with the contact plane, in which the contact surface 6 is located, an angle ⁇ 90 ° to the outside.
- the contact surface 6 is not directly the surface of an active zone 12, but rather a metal layer 6 is arranged on the surface of the active zone 12, the surface 6 facing away from the active zone 12 represents the contact surface.
- both the passivation layer 7 and the insulating layer 8 and the stabilization layer 9 adjoin the opening 13 so that these three layers occur on the wall 11 of the opening.
- the wall 11 of the opening 13 in the right partial image is formed only by the material of the stabilization layer 9 and the insulating layer 8, but the insulation layer 8 on the wall 11 of the opening 13 also forms the opening 13 in the passivation layer 7 passes through and reaches tomaschineticiansoberflache 6.
- the insulation layer 8 is present between the edge of the passivation layer 7 facing the opening 13 and the opening 13.
- Fabrication of layers 7, 8 and 9 is for example by means of chemical vapor deposition (CVD), plasma assisted chemical deposition (PECVD), mechanical processes, such as sputtering,
- CVD chemical vapor deposition
- PECVD plasma assisted chemical deposition
- mechanical processes such as sputtering
- FIG. 4 shows a component according to the invention in which three contact surfaces 6a, 6b and 6c are contacted. Above the contact surfaces 6a and 6c, as shown in the right-hand part of FIG. 3, a passivation layer 7, on top of which an insulation layer 8 and then a stabilization layer 9 are arranged.
- the structure of the layer system corresponds to that shown in the right part of Figure 3.
- the opening 13 is designed so that the cross-sectional area of the opening 13 increases towards the top.
- a bonding contact 10 is now deposited on the layer system. This bonding contact 10 extends over a surface of the stabilization layer 9 facing away from the contact surface 6a and into the openings
- the device according to the invention can now be contacted from outside via the bonding contact 10.
- one or more bonding wires can be applied to that surface of the bonding contact 10 facing away from the contact surfaces 6a, 6c.
- the contact 6b is contacted at another location of the component.
- the manufacturing process here is the same as the other contacts.
- the following is an example of a deposition of the insulating layer 8 are set forth.
- the example relates here to an AlGaN / GaN-based electronic component on silicon-sapphire or silicon carbide substrates, which is passivated with a silicon nitride layer.
- the manufacturing process shown is to be understood as an example and other manufacturing processes are conceivable.
- the silicon nitride at a temperature of 340 0 C, a pressure of 0.6 mTorr, a power of 40 W, and gas flows of 71 sccm silane and 900 sccm nitrogen in an Oxford Plasmalab 80 Plus PECVD plant deposited ,
- a dry etching step the deposited layer is patterned.
- openings are made at a pressure of 25 mTorr, an ICP power of 500 W, an HF power of 20 W, a SF 6 flow of 40 sccm and an O 2 flow of 6 sccm etched.
- a resin (BCB, Cyclotene) is spun at 4000 (or 2000 or 6000) revolutions and baked at 70 0 C on a hot plate.
- the resin is thermally stabilized in an oven at 250 ° C. for 60 minutes.
- a pressure of 0.6 mTorr, a power of 40 W, and gas flows of 71 sccm of silane and 900 sccm nitrogen in an Oxford Plasmalab is applied to the resin 80 Plus PECVD Plant deposited.
- the achieved layer thickness is between 200 and 500 nm.
- the above layer thicknesses allow a sufficient mechanical stability, which allows the attachment of bonding wires with sufficient tensile strength.
- the first step involves etching in an ICP system at a pressure of 25 mTorr, an ICP power of 500 W, an RF power of 20 W, an SF 6 flux of 40 sccm, and an O 2 flux of 8 scctn ,
- the resin is then etched with the following parameters: the pressure is 30 mTorr, the ICP power 1000 W, the RF power 50 W, a SFg flow 10 sccm and an O 2 flow 50 sccm.
- This etching process ensures that the openings have positive flanks and thus no areas arise that are shaded in the following metallization step. As a result, the side walls of the openings can be completely vapor-deposited with metal and completely filled with metal by electrodeposition. These metallization steps simultaneously produce the bond pads.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102009014237 | 2009-03-20 | ||
PCT/EP2010/001792 WO2010105853A1 (de) | 2009-03-20 | 2010-03-22 | Vertikal kontaktiertes elektronisches bauelement sowie verfahren zur herstellung eines solchen |
Publications (1)
Publication Number | Publication Date |
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EP2409327A1 true EP2409327A1 (de) | 2012-01-25 |
Family
ID=42289085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP10712326A Withdrawn EP2409327A1 (de) | 2009-03-20 | 2010-03-22 | Vertikal kontaktiertes elektronisches bauelement sowie verfahren zur herstellung eines solchen |
Country Status (4)
Country | Link |
---|---|
US (1) | US20120038058A1 (de) |
EP (1) | EP2409327A1 (de) |
JP (1) | JP5732035B2 (de) |
WO (1) | WO2010105853A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US8964260B2 (en) * | 2012-10-17 | 2015-02-24 | Samsung Electronics Co., Ltd. | Method of controlling scan speed of scanner including automatic document feeder and scanner performing the same |
US9214423B2 (en) | 2013-03-15 | 2015-12-15 | Semiconductor Components Industries, Llc | Method of forming a HEMT semiconductor device and structure therefor |
KR102044244B1 (ko) * | 2016-12-13 | 2019-12-02 | (주)웨이비스 | 질화물계 전자소자 및 그 제조방법 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050082685A1 (en) * | 2003-10-20 | 2005-04-21 | Bojkov Christo P. | Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61203654A (ja) * | 1985-03-07 | 1986-09-09 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100335591B1 (ko) * | 1992-09-10 | 2002-08-24 | 텍사스 인스트루먼츠 인코포레이티드 | 집적회로디바이스의액티브회로영역상의와이어본딩방법및집적회로디바이스 |
JP4330919B2 (ja) * | 1997-03-14 | 2009-09-16 | 株式会社東芝 | マイクロ波集積回路素子 |
US6159754A (en) * | 1998-05-07 | 2000-12-12 | Intel Corporation | Method of making a circuit edit interconnect structure through the backside of an integrated circuit die |
TW445616B (en) * | 1998-12-04 | 2001-07-11 | Koninkl Philips Electronics Nv | An integrated circuit device |
JP3387083B2 (ja) * | 1999-08-27 | 2003-03-17 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6646347B2 (en) * | 2001-11-30 | 2003-11-11 | Motorola, Inc. | Semiconductor power device and method of formation |
TW503496B (en) * | 2001-12-31 | 2002-09-21 | Megic Corp | Chip packaging structure and manufacturing process of the same |
US7294565B2 (en) * | 2003-10-01 | 2007-11-13 | International Business Machines Corporation | Method of fabricating a wire bond pad with Ni/Au metallization |
US20060065989A1 (en) * | 2004-09-29 | 2006-03-30 | Thad Druffel | Lens forming systems and methods |
US7473943B2 (en) * | 2004-10-15 | 2009-01-06 | Nanosys, Inc. | Gate configuration for nanowire electronic devices |
TWI245345B (en) * | 2005-02-17 | 2005-12-11 | Touch Micro System Tech | Method of forming a wear-resistant dielectric layer |
TWI253735B (en) * | 2005-02-21 | 2006-04-21 | Advanced Semiconductor Eng | Chip structure and manufacturing process thereof |
US7521287B2 (en) * | 2006-11-20 | 2009-04-21 | International Business Machines Corporation | Wire and solder bond forming methods |
US7601628B2 (en) * | 2006-11-20 | 2009-10-13 | International Business Machines Corporation | Wire and solder bond forming methods |
-
2010
- 2010-03-22 WO PCT/EP2010/001792 patent/WO2010105853A1/de active Application Filing
- 2010-03-22 EP EP10712326A patent/EP2409327A1/de not_active Withdrawn
- 2010-03-22 US US13/257,029 patent/US20120038058A1/en not_active Abandoned
- 2010-03-22 JP JP2012500155A patent/JP5732035B2/ja active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050082685A1 (en) * | 2003-10-20 | 2005-04-21 | Bojkov Christo P. | Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion |
Non-Patent Citations (1)
Title |
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See also references of WO2010105853A1 * |
Also Published As
Publication number | Publication date |
---|---|
US20120038058A1 (en) | 2012-02-16 |
JP2012521082A (ja) | 2012-09-10 |
WO2010105853A1 (de) | 2010-09-23 |
JP5732035B2 (ja) | 2015-06-10 |
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