EP2409327A1 - Vertically contacted electronic component and method for producing same - Google Patents

Vertically contacted electronic component and method for producing same

Info

Publication number
EP2409327A1
EP2409327A1 EP10712326A EP10712326A EP2409327A1 EP 2409327 A1 EP2409327 A1 EP 2409327A1 EP 10712326 A EP10712326 A EP 10712326A EP 10712326 A EP10712326 A EP 10712326A EP 2409327 A1 EP2409327 A1 EP 2409327A1
Authority
EP
European Patent Office
Prior art keywords
layer
contact
insulating layer
opening
characterized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP10712326A
Other languages
German (de)
French (fr)
Inventor
Ingo Daumiller
Ulrich Heinle
Mike Kunze
Dmitry Nikolaev
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MicroGan GmbH
Original Assignee
MicroGan GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE102009014237 priority Critical
Application filed by MicroGan GmbH filed Critical MicroGan GmbH
Priority to PCT/EP2010/001792 priority patent/WO2010105853A1/en
Publication of EP2409327A1 publication Critical patent/EP2409327A1/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3171Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049Nitrides composed of metals from groups of the periodic table
    • H01L2924/050414th Group
    • H01L2924/05042Si3N4
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12032Schottky diode

Abstract

The invention relates to an electronic component, having at least one contact surface, which is located in a contact plane, at least one insulating layer, which is above the contact plane, at least one stabilizing layer, disposed on the insulating layer, for increasing a mechanical stability of the component and at least one bonding and/or soldering contact, wherein the insulating layer and the stabilizing layer have at least one opening, which opens towards one surface of the stabilizing layer, which faces away from the contact surface, and which extends through the stabilizing layer and the insulating layer to the contact surface, and wherein the bonding and/or soldering contact extends across the stabilizing layer and touches the contact surface through the opening.

Description

Vertical-contacted electronic component as well as methods for producing such

The invention relates to an electronic component, which is vertically contacted, ie which is contactable via bonding and / or pins which are above those active areas of the device which are contacted by the corresponding contacts. The invention also relates to a method for producing such a component with vertical contacting.

In the manufacture of semiconductor electronic components, the production cost can be reduced, inter alia, by miniaturization of the surface geometry / chip geometry, since the number of components is increased at a given wafer or substrate surface due to the miniaturization. Discrete electronic semiconductor elements have two or more contacts using a variety of technologies such as bonding, soldering and / or flip-chip tech- nology, are wired in the housing or in modules. For making electrical contact usually

Depending on the type of the electronic semiconductor component, the location and placement of the contacts varies. Due to the location and placement of contacts two groups can be formed of electronic semiconductor devices generally. First, the semiconductor electronic components in which the contacting of both the front and on the back of the device Instead place ( "vertical component". However, the term should be distinguished from a "vertical contacting" the possible vertical and lateral components is.) and on the other components which have to be realized due to the specific nature of the HaIb- conductor material and / or function as a lateral embodiment and in which the contacts in one plane, eg on the front of the component lie (lateral component) ,

In general, the required area of ​​the contact zone in the active region of a device is many times smaller than the bonding surface required for making contact or soldering surface over which the device with, for example, is wired a housing. Thus, the bonding surfaces or soldering surfaces for wiring the device prove unusable substrate or Waferflä- che. Particularly in electronic semiconductor devices with lateral arrangement of the contacts of this problem comes into play. One way to reduce the non-usable area of ​​the component size or reduction is to place the bonding surfaces or soldering pads not laterally to the active zone, but, with appropriate technology, directly above the active region of the device, provided that the active zone has a sufficiently large area.

For example, in power electronics typically includes an electronic semiconductor device to a plurality of identical individual components, which are connected in parallel on the substrate or wafer plane. The parallel circuit of the individual components is carried out by the corresponding connection and comparison circuit of the respective contacts. In this way, several hundred individual components can be connected to form a single component. Due to the interconnection of the individual components, the area of ​​the active region increases. This results in a size of the active surface, which are suitable for bonding pads or lands on the active zone and usable.

Vertical contacts have been applied according to the prior art devices (for example diodes or transistors) in which a high current (for example, 10 A to 100 A) at low voltages is switched (to about 200 V). Due to the high current as low as possible ohmic losses through the supply lines are necessary. Due to the fact that the vertical

Contact via the active device sits extremely short lead lengths (determined by the number of vias) possible.

In this method, the supply lines (or bond pads) cross the contacts of the device. This means that the distance must be large contact line that there is no electrical breakdown. The distance or aperture is determined by the dielectric layers.

At low voltages, this is not very problematic and there is a Standardpassivie- coding is used as a rule of SIN.

At high voltages, this layer must be very thick

are (greater than 2 microns). This brings many problems. For example, large strains and cracks in the component may occur.

Object of the present invention is the

Disadvantages of the prior art to overcome and in particular to enable a simple, reliable production, while ensuring sufficient mechanical stability, especially withstand the loads occurring during bonding or soldering.

This object is achieved by the electronic component according to claim 1 and the method of manufacturing an electronic component according to claim 11. Advantageous further developments of the electronic component and the method according to the invention are given in the respective dependent claims.

An electronic component according to the invention firstly has a contact surface which lies in a contact plane. The contact surface may be for example the surface of an active region or a surface of a metallization or layer on such an active zone of a semiconductor device. In general, the contact surface area or those that surface to which a bonding pad and / or a solder contact an electrical contact is to be made.

The electronic device further includes an insulating layer, on, above or above the contact surface and / or the contact plane. If one defines a direction perpendicular to the contact surface as above, this means that the insulating layer above as the contact surface is arranged further. Possible, but not necessary, it is that the insulating layer is also disposed over a portion of the contact surface, which tet importance that a vertical projection of the insulating layer is incident on the plane of contact to a part of the contact surface. However, the insulating layer may also end just above the edge of the contact surface and are present only where it is not above the contact surface.

On and / or above the at least one insulating layer is now according to the invention arranged at least a stabilizing layer. The stabilizing layer is preferably disposed directly on the insulating layer.

an opening according to the invention is at least provided which extends through the insulating layer and the stabilizing layer through to the contact surface. These openings thus correspond to openings in the insulating layer and here via openings arranged in the stabilizing layer. A passage direction of the opening is preferably perpendicular to the contact surface. The erfindungsgemäßε device further comprises at least one bond pad and / or a solder pad, the above and / or extends to the stabilizing layer and extending through and the at least one opening to the contact surface of these contacts and electrically contacted.

The bonding pads or solder contact thus covering at least a portion of a surface or Obersei- te the stabilizing layer and further covers at least partially the contact surface. A facing contact surface of the underside of the bonding contact or the Lötkontaktes preferably follows the surface of the immediately underlying layers, ie, the surface of the stabilizing layer, the side walls inside the opening as well as the contact surface.

facing away from one of the contact surface of the bonding surface contact or the Lötkontaktes can then at least be mounted a bonding wire or a solder wire.

The inventive arrangement makes it possible to bond surfaces or soldering pads of an electronic component on an active region, the contact surface that is to be placed. The insulating layer ensures an insulation between the contact surface and the active zone and the bonding surfaces or to the soldering surfaces. On the other hand, the opening enables a via of the contact surfaces, for example on an active region, to the corresponding bonding pads or solder surfaces by the insulating or dielectric layer and the stabilizing layer. The stabilizing layer provides the mechanical stability, which is necessary in order to attach wire bonds or solder wires to the bonding surfaces or soldering pads.

Both the insulating layer and the stabilizing layer can sierende layer systems with a

its plurality of layers. but they can also each have only one layer or.

is advantageously, especially when the insu- lating layer is arranged at least in regions over the contact surface between the insulating layer and the contact surface of at least a passivation layer or a passivation sandwiched system that particularly preferably the contact surface completely insulated from the

Layer separates. Said opening extends in this case through the passivation layer or the Passivierungsschichtsystem therethrough, so that the bond pads and solder contact is in contact with the contact surface.

Preferably, the passivation layer is arranged directly on the contact layer or the contact surface and / or the insulating layer directly on the passivation layer or the contact layer or surface. In addition, the stabilizing layer is preferably disposed directly on the insulating layer.

The bonding pads or solder contact is preferably arranged directly on the underlying said stabilization layer, aperture wall and / or contact surface.

A layer thickness of the insulating, dielectric layer that is preferably ≥ 100 nm, preferably ≥ 120 nm, particularly preferably ≥ 200 nm, particularly preferably 300 nm and / or ≤ 600 nm, preferably ≤ 500 nm, more preferably ≤ 400 nm.

Preferably, the at least one opening is designed so that their cross-sectional area and / or their diameter, starting from the contact surface increases towards the top, preferably strictly monotonous and continuous. For this purpose the walls of the opening at an angle with the plane of contact of <90 ° may be inclined outwardly. The walls are in this case so funnel-shaped and / or the edges of the opening may be positive or have a positive profile.

Characterized in that the cross-sectional area of ​​the opening at the top increases can be ensured that, for producing the bonding contact or the Lötkontaktes the opening is completely filled with the material of the bonding contact or the Lötkontaktes, or a layer-shaped bonding or solder contact at a wall of the opening is applied, without the formation of holes between the wall and the bonding pads or solder contact.

The cross-sectional area of ​​the opening may be circular, rectangular, square or shaped in other forms.

Preferably, a hardness of the material of the stabilizing layer is greater than a hardness of the material of the insulating layer. This ensures that the stabilizing layer results in an overall stable layer system than would be the case without stabilizing layer with only the insulating layer. Possible materials of the dielectric layer or a dielectric layer system, are inorganic materials such as SiN, SiO 2, metal oxides, Metallnitri- de, Al 2 O 3, TiO 2, TiO 3 on the one hand, but on the other hand, organic and / or polymer-based materials such as benzocyclobutene ( BCB).

BCB has the advantage that it is present as a solution / liquid and can be such as a spin-coated photoresist to the sample and then baked. So you can relatively easily produce several microns thick high quality dielectric and insulating layers. No expensive equipment is required for the deposition, such as in SiO 2 or SiN. The

Patterning / etching is preferably carried out analogously to the other dielectric layers. Another advantage of the BCB that it has a plana- risierende effect due to the application and the general characteristics of the BCB. Each difference in height in the process topology is smoothed after the BCB process. Since BCB is elastic, it does not create internal stresses.

A problem with the use of polymer-based materials for the dielectric layer that are mechanically less stable than inorganic materials, which sword attachment of the bonding wires or solder wires to the bonding pads or solder surfaces ER or impossible. A good connection between the bonding wire or solder and bond pad or bond pad (soldering or solder pad) is namely requires that advertising applied with a sufficiently great pressure on the bonding layer or the solder layer the wires. the insulating layer can be plastically deformed, as is the case with polymer-based materials, the connection between the wire and surface is only partially or not at all about.

The inventive stabilization layer dissolves DIE ses problem. About the possibly plastically deformable material of the insulating layer, the stabilizing layer is applied here, which is preferably made of a harder material than the insulating layer. The application can be carried out in this case directly after the thermal stabilization of the plastically deformable material. In this case, the deposition of the stabilizing layer exceed a curing temperature of the insulating layer.

The stabilizing layer may comprise, for example, or SiN and / or SiO 2 consist thereof. Also, a possibly existing passivation layer SiN and / or SiO 2 comprise or consist thereof.

Preferably, the electronic component is in accordance with the invention, a semiconductor device. The invention is applicable for all known semiconductor devices. Particularly preferred, however it is applicable to semiconductor devices having at least one Nit rid of a group III-substance, especially preferred because find GaN, these electronics, especially in the power application where contacted parallel space-saving numerous components by means of the inventive vertical contact can be.

The inventive component can be a component with one, two, three or more contacts. In this case, one contact corresponds to a contact surface which can be contacted by a respective bond pad and / or solder contact. but it can also be contacted a plurality of contact surfaces by means of a common bonding contact and / or Lötkontaktes if they have the same function or to be electrically connected. Each contact surface is preferably a separate opening to the arranged above the contact surface layers.

Particularly advantageous component of the invention may be a diode with two contacts or contact surfaces which are contacted via two electrically insulated from each other bonding pads and / or pins. The device according to the invention may also be a transistor with three contacts, namely, drain, gate and source which are contacted each with its own bond pad or solder contact.

The insulating layers of the device may particularly preferably via one or more of the fol- constricting processes are prepared: Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), mechanical methods such as sputtering, sputtering, or other thermal processes, such as evaporation or others, as well with- means of spin coating or spraying. Also, a possibly existing passivation layer can be applied by these methods.

During manufacture of the present invention preferably Bauele- mentes the openings described before application of the bonding pads or solder contacts are made. Such openings may be prepared by the stabilizing layer and the insulating layer particularly preferably by means of one or several - rer method selected from the methods of reactive ion etching, physical removal of the corresponding layer, inductively-coupled plasma etching and / or evaporation of the corresponding material by means of laser light.

, A profile is in the generation of the openings as described above, preferably generated which ensures that the apertures can be filled without gaps in particular on their side surfaces with the bonding or solder contact or coated. the profile of the holes should this be a positive profile as described, ie, that the hole diameter increases from below the opening to above the opening.

After completion of the openings they are filled with the material of the corresponding bond or Lötkontaktes or it will be the side surfaces of the apertures and its bottom, which is usually formed by the contact surface coated with the material of the contact, wherein the coating of the

Wall opening communicates with a corresponding coating with the material of the bonding or Lötkontaktes on the surface of the stabilizing layer and in electrical contact preferably is formed continuously therewith.

The described profile of the openings with non-vertical sidewalls can be adjusted by suitable choice of the process parameters, such as the appropriate choice of the gas, the pressure of the gas flow, the acceleration voltage, the RF power and / or the performance of an inductively-coupled plasma. Are particularly suitable for the preparation of such openings multi-stage etching process, wherein the underlying layer is etched in such a way after etching the uppermost layer, that during this step, the upper layer is further gεätzt so that upon further penetration of the etching process in the layer system which lie at the top layers are etched most and each represents a lying above layer is further etched as a lying below layer. This creates an opening, the opening area decreases downwards.

In the preparation of certain parameters of the process can be varied to reach the desired functionality of the insulating layer and the stabilizing layer. are possible here in particular plant-specific variations in manufacturing parameters such as gas flows, gas partial pressures, ICP services, RIE services, process temperatures, etc. Also, it is possible to vary the composition used gases, provided that the results obtained in the process are comparable. Here, it is particularly advantageous if the reactive compo- te of the molecules, such as fluorine, in the varied gases available more (eg rejection of CF 4 to C x F y), and in a similar manner in the plasma, preferably at a comparable RF power, process temperature and gas pressure (in this case carbon and fluorine) into its individual components can be disassembled.

For the preparation of the system according to the invention, the passivation layer may first be deposited and then patterned. Subsequently, the DIE lectric layer, for example made of BCB, and then the stabilization layer can be applied. After that, the openings can be etched.

However, preferred is a method where first deposited, the passivation layer, but is not structured. Subsequently, the dielectric layer and the stabilizing layer are applied. Thereafter, the openings are made through all three layers, for example etched. It can zesses carried out the production of the openings by means of a three-stage dry etching, the first layer of the stabilization, then the insulating (dielectric) layer and finally the passivation layer etch.

The manufacturing process can also be realized through the use of individual processes. The described profile of the openings can be produced in several independent individual processes, for example, by each individual layer applied individually patterned and etched. Thus, it can be patterned by temporarily applied, for example lithographically strukturierfähiger layers for the layout specification with subsequent etching of the layer and the stabilizing layer as after application of the insulating layer in a corresponding manner. The temporary masking layer is removed prior to application of the overlying layer of the semiconductor component.

It is also possible, moreover, that the Schich- th component of the invention themselves are photosensitive, as is the case for example with BCB. In this case, the layers may be itself structured by means of lithography method. For example, for generating a suitable aperture with a suitable profile, the insulating layer having photosensitive BCB which is then patterned by means of lithography. In the next step, the stabilizing layer is applied over the whole area, for example, SiN and temporarily applying a lithographically phisch structured photoresist. In a dry etching process, the stabilizing layer can be etched so now that suitable inclined opening walls result.

The device according to the invention may preferably be a two-terminal device or a three-port device, such as a diode or a transistor. It can also be a complex semiconductor device a- about how it is used for example in power electronics. Group- Ill nitride based diodes and transistors can be particularly advantageous to realize. Specifically, for the realization of energy-efficient systems show group-III nitride-based Schottky diodes and transistors which have the structure according to the invention a low power loss and thus significant advantages. Such diodes and transistors can be used for example in high-frequency switching power supplies, in-efficient inverters in the hybrid drive technology, or in solar technology.

The invention with reference to some figures should be exemplified.

It shows

1 shows a lateral-contacted component, wherein the bonding surfaces or soldering pads are arranged at the side of an active zone,

Figure 2 is a vertically-contacted component, in which two bond pads disposed over an active zone,

3 shows a cross section through two EMBODIMENTS a layer system such as may be used in the inventive device, and

Figure 4 shows an inventive device with three

Contacts.

1 shows a lateral-contacted electronic component in which an active zone is contacted 6 by means of a first bonding and / or soldering surface 1 and a second bonding and / or soldering surface 2, which are arranged adjacent to the active zone. 6 Because the bond pads 1 and 2 are not can be disposed above the active region 6, the total area of ​​the component is determined on a substrate 5 by the sum of the bonding surfaces 1 and 2 and the surface of the active zone. 6 In the example shown, each bonding and solder can be realized analogously.

Between active region 6 and the Bondfiäche 1, an electrical contact through the contacts 3a and 3b is prepared. Between active region 6 and the bonding surface 2, an electrical contact means of the contact surfaces 4a and 4b is produced. The contact surfaces 3a, 3b, 4a, 4b, terminate at a Seitenkan- te of the respective bonding area 1 or 2 and contacting a contact surface of the active region 6 from above. In the example shown, the contacts of a bonding area 1 with those contacts of the bonding surface 2 are arranged nested.

Figure 2 shows an alternative contacting an active zone 6 via bonding surfaces 1 and 2, as they can be used in the inventive device. Here, the bonding areas 1 and 2 cover the active region 6 at least in regions. The bond pads 1 and 2 are thus at least partially disposed over the active region. 6 It will be appreciated that the claimed by this arrangement on a substrate surface 5, and thus the area or size of the device can be designed to be much lower than in the example shown in Figure 1. However, an arrangement as shown in Figure 2 requires a vertical contacting technique, which makes it possible to 6 bind comparable to the bonding surfaces 1 and 2, the active region under the bonding areas 1 and 2 electrically. To this end, the component can be designed according to the invention.

Figure 3 shows two embodiments of a layer system, as it may be in the inventive device. In the left image, a layer system is initially shown, wherein on a contact surface 6, a passivation layer 7 is disposed first, on which in turn a dielectric insulating layer 8 is arranged directly. On the insulating layer 8, a stabilizing layer 9 is then immediately disposed. In the example shown, the passivation layer 7, and the stabilization layer 9 is a SiN film, while the dielectric layer 8 is a layer of BCB polymer. For example, SiO 2, other materials for the passivation layer 7, and the stabilization layer 9 may be. The insulating layer 8 may have, for example, inorganic materials such as SiN, SiO 2, metal oxides, metal nitrides, Al 2 O 3, TiO 2 and / or TiO. 3

In the layers 7, 8 and 9, an opening 13 is now generated in the example shown in Figure 3 examples, which may be, for example, by reactive ion etching, physical removal of the material, inductively-coupled plasma etching, evaporation by laser light or formed similarly. Here, the walls 11 of the opening in the left image perpendicular to the contact surface 6, while having a positive profile in the right image, so with the contact plane in which the contact surface is 6, an angular angle <90 ° to include outwardly. In the example shown, the contact surface 6 is not directly the surface of an active region 12, rather, a metal layer 6 is arranged on the surface of the active region 12 whose surface facing away from the active zone 12 6 illustrates the contact surface.

In the left embodiment of FIG 3, both the passivation film 7 and the insulating layer 8 and the stabilization layer boundaries 9 so that these three layers occur at the opening 13 on the wall 11 of the opening. In contrast, the wall 11 of the opening 13 in the right partial image is solationsschicht only by the material of the stabilization layer 9 and the I-8 is formed, but The insulation results layer 8 on the wall 11 of the opening 13 and the opening 13 in the passivating layer 7 passes through and extends to the Kontaktierungsoberflache. 6 The insulation layer 8 is in this case thus in front of the opening 13 between the facing edge of the passivation layer 7 and the opening. 13

A preparation of the layers 7, 8 and 9, for example by means of chemical deposition (CVD), plasma enhanced chemical deposition (PECVD), mechanical methods such as sputtering,

Sputtering, and others, in particular thermal process, such as evaporation and the like, as well as by means of spin coating or spraying possible. Each of the layers 7, 8 and 9 may comprise a single layer or a multilayer system. Figure 4 shows an inventive device in which three contact surfaces 6a, 6b and 6c can be contacted. Figure 3 are provided above the contact surfaces 6a and 6c, in the right part shown, initially, a passivation layer 7 thereon an insulating layer 8 disposed thereon and a stabilizing layer. 9 The structure of the layer system corresponding to that shown in FIG 3 in the right part. Here too, the opening 13 is configured so that the cross-sectional area of ​​the opening 13 increases toward the top. In the device shown in Figure 4, a bond pad is then deposited on the layer system 10th This bond pad 10 extends through one of the contact surface 6a facing away from the surface of the stabilizing layer 9 as well as in the openings

13 into it, so that it completely covers 6a and 6c inner walls 11 of the openings 13 and the contact surfaces. The inventive component is now contactable via the bond pad 10 from the outside. For this purpose, one or more bond wires 10 are attached, for example on that the contact surfaces 6a, 6c of the bonding surface facing away from the contact.

The contact 6b is contacted at a different location of the Bauele- mentes. The manufacturing process is the same as with the other contacts here.

Hereinafter, a deposition of the insulating layer 8 is to be exemplified. The example here concerns a AlGaN / GaN-based electronic component on silicon-sapphire or silicon carbide substrates, which is passivated with a silicon nitride layer. The manufacturing process is shown as exemplary, and other manufacturing processes are possible. The silicon nitride is deposited at a temperature of 340 0 C, a pressure of 0.6 mTorr, a power of 40 W, and gas flows of 71 sccm of silane and 900 sccm nitrogen in an Oxford Plasmalab 80 Plus PECVD system in a first step , Using a dry etching the deposited layer is patterned. In an Oxford Plasmalab 100 ICP system are openings at a pressure of 25 mTorr, an ICP power of 500 W, an RF power of 20 W, a SF 6 sccm -flow of 40 and an O 2 -FIuSS of 6 sccm etched.

Subsequently, a resin (BCB, Cyclotene) is at 4000 (or 2000 or 6000) spun rpm and baked on a hot plate at 70 0 C. The resin is thermally stabilized C for 60 minutes in an oven at 250 0th

To increase the mechanical stability of a silicon nitride layer at a temperature of 340 0 C, a pressure of 0.6 mTorr, a power of 40 W, and gas flows of 71 sccm of silane and 900 sccm nitrogen in an Oxford Plasmalab is applied to the resin 80 Plus PECVD Plant deposited. Depending duration of the process the layer thickness is achieved between 200 and 500 nm.

The above layer thicknesses allow for a sufficient mechanical stability, the wires attaching bond allows a sufficient tensile strength.

The following is a possibility for the preparation of the opening 13 will be described as an example.

Using a two-step dry etching process in a Oxford Plasmalab 100 ICP unit contact openings are first etched in the silicon nitride layer and then into the resin. In the first step 2 flow is etched from 8 scctn sccm in an ICP system at a pressure of 25 mTorr, an ICP power of 500 W, an RF power of 20 W, a SF 6 -FIuSS of 40 and an O , 10 sccm and an O 2 flow 50, the pressure is 30 mTorr, the ICP power 1000 W, the RF power 50 W, a SF-flow sccm: In the second step, the resin is then etched using the following parameters.

Through this etching process ensures that the openings have positive edges and thus no areas arise which are shadowed in the following metallization step. Characterized the side walls of the openings can be fully vaporized with metal and are completely filled by electrodeposition with metal. These metallization bonding pads are produced simultaneously.

Claims

claims
1. An electronic component with at least one lying in a plane of contact
Contact surface, at least one above the contact plane arranged insulating layer, at least one disposed on the insulating layer stabilizing layer to increase mechanical stability of the device, and at least one bond and / or solder contact, wherein the insulating layer and the stabilized sierende layer having at least one opening, opens the top of the stabilizing layer facing away in one of the contact surface and extending through to the contact surface extends through the stabilizing layer and the insulating layer, and wherein the bond and / or solder contact extends over the stabilizing layer and the opening contacts the contact surface.
2. The electronic component according to the vorhergehen- claim, characterized in that the insulating layer is at least partially disposed over the contact surface, and that a passivation layer between the insulating layer and the contact surface is arranged at least, wherein the opening through the passivation layer extends.
3. Electronic device according to one of the preceding claims, characterized in that a cross-sectional area of ​​the opening in the direction from the top of the stabilizing layer to the contact surface decreases towards, preferably strictly monotonically reduced.
4. Electronic device according to one of the preceding claims, characterized in that the bonding and / or
A soldering contact the opening completely fills up or is formed as a layer on at least a part of an inner wall of the opening and at least a part of the contact surface.
5. Electronic device according to one of the preceding claims, characterized in that a hardness of the stabilizing layer is larger than a hardness of the insulating layer.
6. Electronic device according to one of the preceding claims, characterized in that the passivation layer SiN and / or having SiO 2 and / or that the insulating layer comprises one or more materials selected from organic materials,
Having benzocyclobutenes, SiN, SiO 2, metal oxides, metal nitrides, Al 2 O 3 TiO 2 and / or TiO 3 or consists thereof.
7. The electronic component according to one of the before mentioned claims, characterized in that the electronic component is a semiconductor device which has preferably a nitride of a group III substance, particularly preferably GaN or consists thereof.
8. Electronic device according to one of the preceding claims, characterized in that the electronic
component having two, three or more contact surfaces, wherein an opening is disposed over each of the contact surfaces, which preferably extends perpendicular to the corresponding contact surface, and that several
Contact surfaces are touched by a common bond and / or solder contact or that all contact surfaces are affected by its own, preferably insulated from each other, bonding and / or Lötkon- contacts.
9. Electronic device according to one of the preceding claims, characterized in that the or the bond and / or solder contacts each bond and / or solder surfaces which are arranged parallel to the surface of the respective contact surface areas on the respective contact surface.
10. The electronic component according to one of the before mentioned claims, characterized in that the electronic component is a diode or a transistor.
11. A method for manufacturing an electronic component according to any preceding arrival claims, characterized in that first of which is applied at least one insulating layer over the contact plane, after which is applied to at least a stabilizing layer and then the at least one opening is produced.
12. The method according to the preceding claim, characterized in that at least one de passivieren- layer is applied before application of the insulating layer.
13. Method according to the preceding claim, characterized in that the passivating layer is structured before application of the insulating layer.
14. The method according to claim 12, characterized in that the passivating layer is not patterned prior to applying the insulating layer and that the opening through all the applied layers is produced after the stabilizing layer has been applied.
15. The method according to any one of the preceding claims, characterized in that the at least one insulating layer made of a curable plastically deformable material and which is applied to at least a stabilizing layer having a deposition temperature in excess of a curing temperature of the insulating layer.
16. The method according to any one of claims 11 to 15, characterized in that the at least one insulating layer and / or the at least one stabilizing layer by means of chemical deposition (CVD), plasma enhanced chemical deposition (PECVD), by means of a mechanical method, by means of sputtering, sputter tern, is deposited by evaporation, spin-coating and / or spraying.
17. The method according to any one of claims 11 to 16, wherein the at least one opening by means of a
is prepared process which removes successive material, and wherein the material removal upper side of the component facing away from a plane of contact is initiated and carried so leads is that it in the direction perpendicular to the
progresses surface and that during the removal of material at greater depth of material is removed in a smaller depth of the resulting opening, so that a cross-sectional area of ​​the opening with increasing depth in the direction of the plane of contact decreases.
18. The method according to any one of claims 11 to 17, characterized in that the at least one opening produced by means of reactive ion etching, physical removal schem, inductively-coupled plasma etching and / or evaporation by means of laser light.
EP10712326A 2009-03-20 2010-03-22 Vertically contacted electronic component and method for producing same Pending EP2409327A1 (en)

Priority Applications (2)

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PCT/EP2010/001792 WO2010105853A1 (en) 2009-03-20 2010-03-22 Vertically contacted electronic component and method for producing same

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