EP2394399A1 - Unité de sécurisation de fonction pour systèmes de communication - Google Patents

Unité de sécurisation de fonction pour systèmes de communication

Info

Publication number
EP2394399A1
EP2394399A1 EP10704529A EP10704529A EP2394399A1 EP 2394399 A1 EP2394399 A1 EP 2394399A1 EP 10704529 A EP10704529 A EP 10704529A EP 10704529 A EP10704529 A EP 10704529A EP 2394399 A1 EP2394399 A1 EP 2394399A1
Authority
EP
European Patent Office
Prior art keywords
unit
communication
counter
event
counter value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP10704529A
Other languages
German (de)
English (en)
Inventor
Thomas Peichl
Jürgen SCHERSCHMIDT
Jörn SCHRIEFER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Continental Teves AG and Co OHG
Original Assignee
Continental Teves AG and Co OHG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Continental Teves AG and Co OHG filed Critical Continental Teves AG and Co OHG
Publication of EP2394399A1 publication Critical patent/EP2394399A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/764—Masking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60W—CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT
    • B60W50/00—Details of control systems for road vehicle drive control not related to the control of a particular sub-unit, e.g. process diagnostic or vehicle driver interfaces
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/267—Reconfiguring circuits for testing, e.g. LSSD, partitioning
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40032—Details regarding a bus interface enhancer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
    • H04L12/4135—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD] using bit-wise arbitration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40267—Bus for use in transportation systems
    • H04L2012/40273—Bus for use in transportation systems the transportation system being a vehicle

Definitions

  • the invention relates to a communication system according to the preamble of claim 1, a method for synchronization according to the preamble of claim 8 and the use of the communication system in motor vehicles.
  • the invention has the object to provide a communication system and a method for synchronization, which enables synchronous communication between at least two communication units in a relatively cost-effective manner and / or which allows a relatively high system security with respect to communication between communication units of the system.
  • the communication system and the method are designed in particular to increase the reliability in an electronic system.
  • the first and the second communication event are preferably defined as a communication event which occurs at least in the communication between the first and the second communication unit.
  • the counter memory unit is preferably designed and / or is preferably controlled so that the change of the counter value according to the defined first manner by a defined step size by means of a mathematical operation.
  • the mathematical operation is understood to mean an addition or multiplication or a more complex operation, and the increment, for example, the value by which the counter value is incremented or decremented, particularly preferably the value one or the value which is multiplied by the counter value.
  • the counter memory unit is preferably designed and / or is controlled so that in each communication event between communication units of the communication system, such as the first and the second communication unit, the counter value of the counter memory unit is changed in the defined first manner.
  • the first communication event is defined such that each communication event between communication units of the communication system is treated at least as a defined first communication event.
  • the counter memory unit is designed as a counter unit and / or is driven, wherein the change of the counter value according to the defined second manner as a setting process or reset operation or reset operation of the counter unit is pronounced. In this setting or reset or reset operation, the counter value in particular to a defined value, particularly preferably the value "0", reset.
  • the first communication unit preferably has at least one first and one second data storage unit and is configured such that at least when the first defined communication event occurs, the current date of the first data storage unit is written to the second data storage unit and the counter value of the counter storage unit is changed according to the defined first way ,
  • the first communication unit preferably has at least one first and one second data storage unit and is designed so that after the occurrence of a defined trigger event, in particular a defined third communication event or an internal trigger event, the current date of the first data storage unit is written to the second data storage unit and , particularly preferred, the counter value - A -
  • the counter memory unit is changed according to the defined second way.
  • the then stored data of the first and second data storage unit are compared in a transfer unit. The comparison result of this comparison is used as status information.
  • the first communication unit is designed so that in the course of at least the second defined communication event between at least first and second communication unit, the current date of the second data storage unit is transmitted from the first communication unit to the second communication unit.
  • the second communication unit as a master unit and at least the first communication unit are designed as a slave unit and are connected to each other by a bus system.
  • the first communication unit is preferably designed as a sensor unit and / or actuator unit, which in particular detects at least one measured variable and provides at least one measured variable datum.
  • the second communication unit is preferably designed as an electronic control unit, in particular as an electronic control unit of a motor vehicle brake system and / or a motor vehicle driving dynamics control system. It is preferred that the counter memory unit is designed and controlled in such a way that the counter value can be used as a time stamp and / or that the counter value forms or delivers a time dimension for the synchronization of the communication system.
  • the reference event is preferably defined as the, in particular successful, writing operation of the date of the first data storage unit into the second data storage unit.
  • the third defined communication event is preferably defined as a data request or "sample command" of the second communication unit at least to the first communication unit, in particular to all further communication units of the communication system.
  • the internal trigger event is preferably defined as the exceeding or falling below of a measured value or parameter in the first communication unit.
  • the second defined communication event expediently comprises a data access of the second communication unit at least to the first communication unit, in which the current counter value and the date currently stored in the second data storage unit, in particular in common, are transmitted or sent from the first communication unit to the second communication unit.
  • the first communication unit is designed as a sensor and / or actuator unit and at least a first status information processing module comprising a status memory unit in which status information of said first communication unit is stored in the form of a status datum, said first status information processing module further comprising a masking memory unit connected to said status memory unit and a status processing element connected to said mask memory unit, said first status information processing module is configured such that at least one status information of the status data is selected by the masking memory unit and the resulting selective status data is processed by the status processing element such that it provides a short status data on the output side which has a shorter data word length than the selective status data.
  • the masking memory unit preferably comprises a logic circuit or a selection circuit with which the input-side status data is linked to the bit mask stored in the masking memory unit, whereby the selective status data is generated.
  • This logic circuit or selection circuit comprises, in particular, an AND logic circuit, which is particularly preferably designed so that each bit of the status data is ANDed with one bit of the bit mask.
  • the first status information processing module preferably additionally has a short status storage unit connected to the status processing element, in which the short status data is written.
  • the first communication unit preferably comprises an interface unit which is connected to the output of the status processing element or to the output of the short status memory unit of the first status information processing module and connected to the masking memory unit of the first status information processing module such that it changes and / or stores the bit mask stored in the mask memory unit can override, whereby the selection of the status types over which the interface unit information in the form of the short-status data are provided, can be adjusted.
  • the short-status storage unit is alternatively preferably integrated in the interface unit.
  • the interface unit is also connected to the status storage unit of at least the first status information processing module and configured to write to this status storage unit, whereby a test status data can be written in the status storage unit.
  • the interface unit in particular has a test unit which is designed such that it independently provides test data or forwards and / or processes test data, particularly preferably test data which are provided by a second communication unit.
  • the communication unit expediently or alternatively preferably has at least one signal processing unit. unit, which in particular generates and / or provides a test module additionally or alternatively to the test unit of the interface module.
  • the first communication unit preferably additionally has at least one second, redundant status information processing module, which is configured substantially in accordance with the first status processing module and is likewise connected to the interface unit in substantially the same way.
  • the first communication unit is preferably part of a communication system and connected to at least one second communication unit, wherein the interface unit of the first communication unit is configured to send to the second communication unit the short status data of the first and / or the second status information processing module and / or one or both can transmit this data derived overall short-term date.
  • the interface unit of the first communication unit is in particular configured to write a test status data received from the second communication unit directly or in a modified form into the status memory unit of the first and / or second status information processing module and then at least one of the resulting short status data and / or a total short status data derived therefrom transmits to the second communication unit.
  • the communication unit itself, al- so without numbering is expediently always meant the first communication unit, which is designed as a sensor and / or actuator unit.
  • the status memory units of the first and the second status information processing module are expediently connected and / or controlled such that the respective status data of these two status memory units are configured as mutually inverted data words, at least with respect to status information provided by the communication unit itself.
  • the masking memory units of the first and second status information processing modules are connected and / or driven in such a way that the respective bit masks of these two masking memory units are designed as mutually inverted data words.
  • the inventive method is preferably further developed in that the first communication unit has at least one first and one second data storage unit, wherein after the occurrence of a defined trigger event, in particular a defined third communication event or an internal trigger event, the current date of the first data storage unit is written to the second data storage unit and the counter value of the counter memory unit is changed in accordance with the defined second manner, and wherein after the occurrence of the defined second communication event, the current date of the second data storage unit is transferred at least from the first communication unit to the second communication unit or is sent.
  • a defined trigger event in particular a defined third communication event or an internal trigger event
  • the method is expediently further developed in that for transmitting status information from the first communication unit, which is designed as a sensor and / or actuator unit, to at least the second communication unit the first communication unit has at least one first status information processing module with a status memory unit, in which status information of the first Communication unit are deposited in the form of a status date, wherein at least one status information of this status data of the first status information processing module is selected by means of a masking memory unit, after which the resulting selective status data is processed by a status processing element and this status processing element provides a short status data having a data word length shorter than the selective status data ,
  • the method for transmitting status information is preferably further developed in that the at least one short status data item is transmitted to the second communication unit via an interface unit. Thereafter, it is particularly preferred that the second communication unit interprets the short status data, whether the short status data contains information that the second communication unit is to respond thereto, after which in the event that the presence of such information to which the second communication unit is to respond is detected , the second communication unit at least the status data of the first and / or the second status information processing module requests or reads and / or the second communication unit is automatically in another operating mode, in particular in an emergency mode, offset.
  • the second communication unit is very particularly preferably designed such that it contains information for interpreting the at least one short-status data and / or the overall short-term data.
  • the invention also relates to the use of the communication system in motor vehicles, in particular in a motor vehicle brake system and / or in a motor vehicle dynamics control system.
  • FIG. 1 shows an embodiment of a communication system with a first and a second communication unit, wherein the first communication unit is designed as a sensor unit and comprises a counter memory unit, and
  • 1 shows an exemplary, reliable communication system comprising a first communication unit 1, for example designed as a pressure sensor unit, which is connected by means of data transmission link 3 to a second communication unit 2, which is designed as an electronic control unit ECU.
  • Sensor unit 1 in this case has two sensor sensors SEI, SE2, for example, two pressure sensor elements on. These are connected to an analog / digital converter ADC which, for example, provides two digital pressure values P1, P2 and two digital temperature values T1, T2 per measurement.
  • This analog / digital converter ADC is connected to a signal processing unit 4, for example as a digital signal processor DSP, by means of a multiplexer Mux.
  • At least one further signal line is supplied to the signal processing unit 4 by means of the multiplexer Mux.
  • the sensor unit 1 For the main information or pressure information P1, P2, which the sensor unit 1 is to deliver to the control unit 2, the sensor unit 1 has a first and a second, serial data storage unit MemA and MemB for synchronization.
  • the main information for example two digital pressure values P1, P2 and two digital temperature values T1, T2 are written into the first data memory unit MemA used as buffer memory / intermediate memory.
  • First data storage unit MemA is always overwritten.
  • signal processing unit 4 automatically writes into the first data storage unit MemA when new data is present.
  • Sensor unit 1 has a counter memory unit 7, in which a counter value (message counter) MSG CNT is stored, which corresponds to a time stamp or time dimension for a synchronous communication within the communication system. At least for a first communication event, for example in each communication event between the first and second communication unit, the counter value is changed in a defined first manner. This is done, for example, by driving on the part of the interface unit logic, 6.
  • Counter memory unit 7 is designed as a counter unit and the control according to the first manner is defined by example as incrementing the counter value by 1.
  • a successful write from MemA to MemB after the trigger event is defined as a reference event after which the counter value of the counter memory unit 7 or counter unit is changed in a defined second manner, which exemplifies a "reset”. or a reset of the counter value to the value "0.”
  • the control unit 2 thus triggers the data transmission with the third communication event in order to select the current data at the exact request time in each case - the current date of the first data memory MemA is written into the second data memory MemB.
  • This data from MemB is then provided after a, as a second communication event defined data access of the ECU, together with the current counter value via the interface unit 6, logic of the driver unit 5, which transmits these data via the data transmission link 3 to control unit 2.
  • Signal processing unit 4 also provides status information stat, which are supplied to a first and a redundant second status information processing module 8 and 9, which are connected to the interface unit logic, 6. These two status information processing modules 8, 9 enable an efficient or resource-saving transmission of status information from the sensor unit 1 to the control unit 2.
  • Sensor unit 1 additionally has a central Memory unit Meml on, which is for example designed as an EEPROM unit and in which defined operating parameters of the sensor unit are stored.
  • This central storage unit Meml is also connected to the signal processing unit 4 and the interface unit logic.
  • the memory unit MemA and MemB comprise, for example, one register for each main information data P1, P2, T1 and T2.
  • the central storage unit Meml optionally includes hardware identification information ID which the control unit ECU can query, and by means of which sensor unit 1 can be uniquely identified. As a result, for example, the use of an unscheduled sensor unit in conjunction with a specific control unit can be avoided.
  • control unit ECU compares the pressure values P1 and P2 detected by the pressure sensor elements SE1 and SE2 and provided by the signal processing unit 4 for plausibility checking. It can not be ruled out that the analog / digital converter ADC and / or the signal processing unit 4 influence the pressure signals in a similar, undesired manner. For this reason, the pressure values P1 and P2 are represented or coded in different ways, for example as data that are mutually inverted-coded or by a relative offset, for example. which the control unit 2 is known.
  • test data are provided to test signal lines through which the control unit 2 can check whether, for example, filter parameters or other signal processing functions of the signal processing unit 4 are functioning correctly.
  • the control unit 2 predetermines these test values at runtime or initializes a BIST (build in seif test) implemented completely in the sensor unit 1 with appropriately stored test vectors or test data, this or the output data of the control unit 2 assigned to it being known.
  • BIST build in seif test
  • the pressure values Pl and P2 are plausibilized in the control unit 2, in particular directly after the processing of test data, for example by means of a print model or by means of a specific thresholds / differential thresholds.
  • This plausibility check of at least the pressure values P 1 and P 2 can be performed, for example, on a "brake system level" if the communication system described here is part of a motor vehicle brake system and the sensor unit 1 detects brake pressure values and the control unit 2 is designed as the electronic control unit of the brake system.
  • the timebase of the timestamp or the current one Counter value is known to both the sensor unit 1 and the control unit ECU. This time stamp enables the detection of possible sample / timing and / or synchronization errors, in particular with regard to the data transmission via data transmission link 3.
  • Data transmission link 3 comprises by way of example only a single data transmission line.
  • the data storage units MemA, MemB is optionally exemplified by a transfer unit transfer comprising a logic circuit with which the data of the memory MemA directly before the transfer of the data of the buffer memory MemA in the memory MemB compared with the data of the memory MemB directly after just this transmission become. The result is written in a status register transfer status.
  • the transfer unit transfer has a test logic circuit with which the logic circuit is tested. The transmission of the data from MemA to MemB and / or the transfer unit are additionally checked, for example, by the transmission of test data from MemA to MemB.
  • a status memory unit 10 for example, a masking memory unit 11, a status processing element 12 and, for example, a short status memory unit 13, which may alternatively be shown in the interface unit 6, logic is / are integrated.
  • the status memory unit 10 is in each case supplied with a status data stat, for example by the signal processing unit 4, not shown here, and stored in the status memory units 10. These provide the status data stat to each of the masking memory unit 11, in which a bit mask is stored and in which the status data stat is ANDed with the respective bit mask, whereby the bit mask selects defined status bits or status information.
  • the masking memory unit 11 in each case has a logic circuit, not shown, or a selection circuit.
  • This logic circuit or selection circuit comprises, in particular, an AND logic circuit, which is designed, for example, such that each bit of the status data is AND-linked to one bit of the bit mask in each case.
  • the resulting selective status data sel-stat is processed in state processing element 12 so that a short status data k-stat is provided which has a shorter data word length than the selective status data selstat.
  • the state processing element 12 is arranged to sel-stat OR the individual bits of the selective status data.
  • the short-status data k-stat is stored in the short-status storage unit 13 and provided to the interface unit 6.
  • the short-status data k-stat comprises, for example, due to the exemplary OR operation of the individual bits of the selective status data only one bit, which contains information about whether one or more, so if at least one of Status bits which are selected by the masking memory unit have the value "1."
  • the short status data k-stat of each status information processing module 8, 9 or a common overall short-term data is sent to the second communication unit (not shown here), which identifies the occurrence of an error or an undesired one Status, then interface unit 6 reads out one or both of the status storage units and sends the respective complete status data to the second communication unit 12.
  • Interface unit 6 is designed and connected to masking memory unit 12 so that read and write access are possible When changing or writing the bit mask, the selection of the individual status bits of the status data can be specified.
  • the interface unit 6 has, by way of example, a test unit, not shown, which is designed such that it independently provides test data or forwards and / or processes test data, particularly preferably test data provided by a second communication unit. These test data are respectively written into the status memory processing unit of the status information processing modules 8, 9 by the interface unit and the result is evaluated with regard to the expected result. Thus, the operation of the status information processing modules 8, 9 can be tested.
  • the status information processing modules 8, 9 do not have short status storage units, Instead, the respective short-status data k-stat is made available to the interface unit, which is configured to combine these two short-status data k-stat and generates a total short-term data derived therefrom, which is transmitted to the second communication unit by way of example.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • General Health & Medical Sciences (AREA)
  • Medical Informatics (AREA)
  • Computing Systems (AREA)
  • Health & Medical Sciences (AREA)
  • Mechanical Engineering (AREA)
  • Transportation (AREA)
  • Automation & Control Theory (AREA)
  • Human Computer Interaction (AREA)
  • Small-Scale Networks (AREA)
  • Combined Controls Of Internal Combustion Engines (AREA)
  • Debugging And Monitoring (AREA)
  • Regulating Braking Force (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

L'invention concerne un système de communication comportant au moins une première et une deuxième unité de communication (1, 2), la première unité de communication (1) comprenant une unité d'enregistrement de compteur (7) dans laquelle une valeur de compteur (MSG_CNT) est enregistrée. La première unité de communication (1) est conçue de telle manière qu'au moins en cas de survenue d'un premier événement de communication défini, la valeur de compteur de l'unité d'enregistrement de compteur (7) est modifiée d'au moins une première manière définie. Au moins après survenue d'un événement de référence défini, la valeur de compteur de l'unité d'enregistrement de compteur (7) est modifiée d'au moins une deuxième manière définie. Au cours d'un deuxième événement de communication défini, la première unité de communication (1) transmet la valeur de compteur courante de l'unité d'enregistrement de compteur (7) directement ou indirectement à la deuxième unité de communication (2).
EP10704529A 2009-02-03 2010-02-03 Unité de sécurisation de fonction pour systèmes de communication Ceased EP2394399A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009007200 2009-02-03
PCT/EP2010/051322 WO2010089331A1 (fr) 2009-02-03 2010-02-03 Unité de sécurisation de fonction pour systèmes de communication

Publications (1)

Publication Number Publication Date
EP2394399A1 true EP2394399A1 (fr) 2011-12-14

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EP10702866.4A Active EP2394400B1 (fr) 2009-02-03 2010-02-03 Unité de traitement d'état configurable pour systèmes de capteurs/actionneurs
EP10704529A Ceased EP2394399A1 (fr) 2009-02-03 2010-02-03 Unité de sécurisation de fonction pour systèmes de communication

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Country Status (6)

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US (2) US8718894B2 (fr)
EP (2) EP2394400B1 (fr)
KR (1) KR101612983B1 (fr)
CN (1) CN102369694B (fr)
DE (2) DE102010001560A1 (fr)
WO (2) WO2010089331A1 (fr)

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TWI579862B (zh) * 2015-10-28 2017-04-21 華邦電子股份有限公司 記憶體裝置
JP6455939B2 (ja) * 2016-09-27 2019-01-23 株式会社デンソーテン 通信方法
DE102017218336A1 (de) * 2017-10-13 2019-04-18 Continental Automotive Gmbh Schaltungsanordnung mit einem Mikroprozessor und einem Spannungserzeugungs-Schaltkreis

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Also Published As

Publication number Publication date
KR101612983B1 (ko) 2016-04-15
CN102369694A (zh) 2012-03-07
WO2010089332A1 (fr) 2010-08-12
WO2010089331A1 (fr) 2010-08-12
CN102369694B (zh) 2015-01-28
EP2394400B1 (fr) 2018-07-18
DE102010001563A1 (de) 2010-08-05
DE102010001560A1 (de) 2010-09-23
US20120079218A1 (en) 2012-03-29
KR20110124273A (ko) 2011-11-16
US8706981B2 (en) 2014-04-22
EP2394400A1 (fr) 2011-12-14
US8718894B2 (en) 2014-05-06
US20110296433A1 (en) 2011-12-01

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