EP2313338A2 - Procédé de réalisation d'un composant, procédé de réalisation d'un système de composants, composant et système de composants correspondants - Google Patents

Procédé de réalisation d'un composant, procédé de réalisation d'un système de composants, composant et système de composants correspondants

Info

Publication number
EP2313338A2
EP2313338A2 EP09779687A EP09779687A EP2313338A2 EP 2313338 A2 EP2313338 A2 EP 2313338A2 EP 09779687 A EP09779687 A EP 09779687A EP 09779687 A EP09779687 A EP 09779687A EP 2313338 A2 EP2313338 A2 EP 2313338A2
Authority
EP
European Patent Office
Prior art keywords
membrane
component
conductive layer
substrate
manufacturing step
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09779687A
Other languages
German (de)
English (en)
Inventor
Torsten Kramer
Stefan Pinter
Hubert Benzel
Matthias Illing
Frieder Haag
Simon Armbruster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2313338A2 publication Critical patent/EP2313338A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C99/00—Subject matter not provided for in other groups of this subclass
    • B81C99/0075—Manufacture of substrate-free structures
    • B81C99/008—Manufacture of substrate-free structures separating the processed structure from a mother substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/093—Conductive package seal

Definitions

  • the invention is based on a method for producing a component according to the preamble of claim 1.
  • a first porous layer is formed in the semiconductor device, and wherein in a second step, a cavern under or from the first porous layer in the
  • Semiconductor device is formed, wherein the cavern has an access opening.
  • the semiconductor carrier comprises a membrane, a cavern located at least below the membrane and a first doping
  • the membrane preferably has an epitaxial layer and is arranged on stabilizing elements, which are in particular formed as webs above at least a portion of the cavern.
  • the inventive method for producing a component has the advantage that the electrically conductive first conductive layer arranged in the cavern region and / or on the second side, which in Also referred to below as the back, by means of a Surface surface wafer process (OMM) is to be prepared, so that advantageously a backside coating of relatively thin membranes with the first conductive layer is made possible.
  • OMM Surface surface wafer process
  • this coating can be produced relatively inexpensively due to the use of a standard method in a surface wafer process.
  • Particularly preferred is thus an electrical contacting of the device from the back of the device and / or a relatively efficient removal of process heat on the back of the device allows.
  • membrane in the sense of the present invention is in no way limited to sensor membranes, but rather comprises any layer which is preferably a
  • Semiconductor material has, is aligned substantially parallel to the main extension plane and / or is formed comparatively thin perpendicular to the main extension plane.
  • the first conductive layer is also arranged on a first side of the membrane remote from the substrate perpendicular to the main extension plane, wherein preferably the first conductive layer on the first side is partially electrically conductive with the first conductive layer on the second side is connected and / or that in the second manufacturing step, the first conductive layer is patterned.
  • a contacting of the first side, hereinafter also referred to as the front side, from the rear side of the membrane is particularly advantageous so that, for example, electrical, electronic and / or micromechanical structures on the front side can be electrically contacted from the rear side.
  • Cavern region is provided in the first manufacturing step with support structures for supporting the membrane, wherein in the second manufacturing step, the first conductive layer is at least partially disposed on the support structures.
  • the membrane is particularly advantageously stabilized, so that on the one hand a much thinner Membrane to produce and back to cover with the first conductive layer and on the other hand, the resolution in lithographic processes on the membrane is significantly increased in subsequent manufacturing steps, as a bending of the membrane is prevented.
  • the support structures make it possible to contact the front side via the first conductive layer on the support structures.
  • the support points prevent first conductive layers on the front side and / or first conductive layers on the back side and / or first conductive layers from being merged with first conductive layers on the rear side, so that the first conductive layer advantageously has a plurality of contact regions which are not electrically connected to one another and thus preferably a parallel wiring of the membrane is made possible.
  • the membrane in a third production step, is separated from the substrate, wherein the membrane is preferably torn from the substrate and wherein particularly preferably by vibrational excitation of the substrate, the membrane and / or the support structures, a breakage of the support structures is brought about.
  • the detachment of the membrane from the substrate makes it possible to manufacture the component in a wafer composite, wherein the components are separated by the detachment of the membrane from the substrate or from the wafer composite.
  • a sawing process is preferably saved so that particularly no contamination of the component and of the remaining wafer composite by sawing particles is produced.
  • a microelectronic circuit and / or a micromechanical structure is produced in the membrane and / or on a first side of the membrane facing away from the substrate, and / or in a second substep the first manufacturing step, the access opening is etched into the cavern area.
  • the membrane comprises a single-crystal semiconductor material, in particular a monocrystalline silicon, so that advantageously a semiconductor integrated circuit can be produced in the membrane, which can be contacted from the rear side of the membrane.
  • a membrane made of polysilicon for the realization of micromechanical structures in the membrane is provided. Particularly advantageous components can be realized, which have a considerably lower thickness compared to the prior art perpendicular to the main extension plane.
  • a first insulation layer to be arranged on the membrane, the cavern region and / or the support structures in a third production step, wherein the third production step is preferably carried out before the second production step.
  • the first conductive layer is patterned by means of shadow masking and in particular by means of spray coating, preferably in a first sub-step of the second manufacturing step, a photoresist is applied to the first conductive layer, in a second sub-step of the second Manufacturing step, the photoresist is exposed, in a third step of the second step of the photoresist is developed and in a fourth step of the second step, the first conductive layer or the photoresist is etched.
  • a structuring of the first conductive layer is thus particularly advantageously possible, so that in particular a plurality of interconnects insulated from one another in the first conductive layer and in particular a plurality of mutually insulated electrical contacts between the front and the back can be realized by means of the first conductive layer.
  • a second conductive layer in particular a galvanic layer, is arranged on the first conductive layer.
  • the conductivity is thus increased and the reduced electrical resistance compared to the power line only in the first layer in a significant way.
  • the efficiency is significantly increased by such a backside metallization.
  • a wafer composite with a substrate, a plurality of cavern regions and a plurality of membranes is provided, wherein in the third production step at least one membrane for separating the membrane from the wafer composite is dissolved out.
  • Another object of the present invention is a method for producing a component assembly with a device according to the invention, wherein in a fifth manufacturing step after the third manufacturing step, the component on a further component and / or on a support element, in particular on a circuit board and / or in a
  • the device and in particular the integrated circuit and / or the micromechanical structure by means of the first and / or the second conductive layer are electrically contacted.
  • the first conductive layer on the back is a blunt soldering, bonding and / or bonding of the device to the other component and / or the support element similar to an SMD component (Surface Mounted Device) in an SMT process (Surface Mounting Technology) in a particularly cost-effective manner, since no further contacting steps for electrical contacting of the device are necessary.
  • the contact regions are electrically conductively arranged directly on connection surfaces and / or conductor tracks of the further component and / or of the carrier element.
  • Another object of the present invention is a component, wherein the component has the membrane, wherein in the cavern region and in particular on the second side, the first conductive layer is arranged.
  • the component preferably has a comparatively thin membrane, wherein at the same time owing to the arrangement of the first conductive layer on the rear side an efficient dissipation of heat through the first conductive layer and / or electrical contacting of the component from the rear side can be realized ,
  • the first conductive layer is also arranged on the first side, wherein preferably the first conductive layer comprises at least one electrically conductive contact between the first side and the cavern region and in particular between the first side and the second side.
  • electrical contacting of structures on the front side of the component or of the membrane from the rear side is particularly advantageously possible, so that the component can be applied in an electrically conductive manner, for example directly on connecting surfaces of a carrier element, after separation as an SMD component.
  • the membrane has a microelectronic circuit and / or a micromechanical structure which can be contacted, in particular, by means of the at least one electrically conductive contact from the cavern region and / or from the second side.
  • the component thus preferably comprises an integrated microchip and / or a sensor and particularly preferably a rotation rate, acceleration and / or pressure sensor.
  • Another object of the present invention is a component arrangement, wherein the component disposed on the further component and / or on the carrier element and in particular soldered, glued and / or is bonded, wherein the carrier element preferably comprises a printed circuit board and / or a housing.
  • the component is electrically contacted and controlled in a comparatively simple manner.
  • the component is arranged substantially congruently, in particular perpendicular to the main extension plane, on the further component, and particularly preferably another electrically conductive contact of the further component is electrically conductively connected to the corresponding electrically conductive contact of the component.
  • another electrically conductive contact of the further component is electrically conductively connected to the corresponding electrically conductive contact of the component.
  • Figures 1a and 1b is a schematic side view and a schematic
  • Figure 2 is a schematic side view of a second precursor structure for
  • 3a and 3b show a schematic side view and a schematic plan view of a third precursor structure for producing a component according to the first embodiment of the present invention
  • Figure 4 is a schematic side view of a fourth precursor structure for
  • FIG. 5 shows a schematic partial side view of a fifth precursor structure for
  • FIG. 6 shows a schematic side view of a sixth precursor structure for producing a component according to the first embodiment of the present invention
  • Figure 7 is a schematic partial side view of a seventh precursor structure for
  • Figure 8 is a schematic side view of a wafer composite with two
  • Figure 9 is a schematic side view of an eighth precursor structure for
  • FIG. 10 shows a schematic side view of a component arrangement according to the first embodiment of the present invention
  • FIG. 10 shows a component arrangement according to a first embodiment of the present invention
  • Figure 11 is a schematic side view of a component arrangement according to a second embodiment of the present invention.
  • FIGS. 1 a and 1 b show a schematic side view and a schematic plan view of a first precursor structure for producing a component according to a first embodiment of the present invention, the first fabrication step for partially producing the basic structure 1 'being partly based on FIGS. 1 a and 1 b.
  • FIG. 1 a is a sectional view of FIG. 1 b along a first section line 102.
  • the first precursor structure has a partial base structure V in a wafer composite 300 with further partial base structures 1 ", the partial base structure V comprising a substrate 4, a membrane 3 and a cavity region 2 wherein the membrane 3 is arranged substantially parallel to a main extension plane 100 of the substrate 4 and wherein between the substrate 4 and the membrane 3, the cavity region 2 is arranged.
  • the cavern region 2 also has support structures 5, which extend perpendicular to the main extension plane 100 and for supporting the membrane 3, the membrane 3 on a second side 3 ", hereinafter also referred to as the back 3" of the membrane 3 and / or the device 1, connect to the substrate 4, so that in the cavern region 2 a plurality of parallel to the main extension plane 100 through the support structures 5 separate caverns 2 'are formed.
  • the shape, number and position of the support structures 5 can be selected as desired, wherein preferably at least one support structure 5 'has a diameter substantially equal to the thickness of the membrane 3 perpendicular to the main extension plane 100. It can be seen from FIG.
  • the first precursor structure is used in surface micromachining (OMM), preferably in an APSM process (Advanced Porous Silicon Membrane) or in a known sacrificial layer process, for example with sacrificial oxide and polysilicon structures, similar to a CMB process (Controlled Metal Build Up) .
  • OMM surface micromachining
  • APSM Advanced Porous Silicon Membrane
  • CMB Controlled Metal Build Up
  • the substrate 4 and the membrane 3 preferably comprise a silicon and particularly preferably a monocrystalline silicon.
  • FIG. 2 shows a schematic side view of a second precursor structure for producing a component 1 according to the first embodiment of the present invention, FIG. 2 partially illustrating the first production step for partially producing the basic structure V, and wherein the second precursor structure is substantially identical to FIG the first precursor structure illustrated in Figure 1 a, wherein in the first manufacturing step to the Front 3 'of the membrane 3, a structured trench mask 8 is arranged, which covers the integrated circuit 7 in particular.
  • the trench mask 8 comprises in particular a structured lacquer or an oxide layer, such as TEOS.
  • FIGS. 3 a and 3 b show a schematic side view and a schematic plan view of a third precursor structure for producing a component according to the first embodiment of the present invention, the third precursor structure corresponding to a basic structure 1 "'for producing the component 1, wherein the third precursor structure identical to the second precursor structure illustrated in FIG. 2, the third precursor structure being etched at the open locations of the structured trench mask 8 in the first production step so that the membrane 3 is connected to the substrate 4 only via the support structures 5 underneath the membrane 3 and Cavern area 2 has access openings 200 in the direction of the front side 3 '
  • Trechmaske 8 hidden structures and elements are shown in dashed lines in Figure 3b for the sake of clarity.
  • FIG. 4 shows a schematic side view of a fourth precursor structure for producing a component 1 according to the first embodiment of the present invention, wherein FIG. 4 essentially corresponds to a sectional view of FIG. 3b along a second section line 103, wherein a third production step is illustrated with reference to the fourth precursor structure is applied, wherein on the third precursor structure, an insulating layer 80 is applied, which covers both the membrane 3 on the front side 3 'and the trench mask 8, as well as support structures 5, on the back 3 "of the membrane 3, on side regions 3"' are arranged perpendicular to the main extension plane 100 between the front and back 3 ', 3 "of the membrane 3 and on the substrate 4 in the cavern areas 2 in caverns 2' with access openings 200.
  • FIG. 5 shows a schematic partial side view of a fifth precursor structure for producing a component 1 according to the first embodiment of the present invention, the partial side view comprising an enlargement of a portion of the fourth precursor structure illustrated in FIG fifth precursor structure is substantially identical to the fourth precursor structure, wherein based on the fifth precursor structure, a second and a fourth manufacturing step are illustrated, wherein in the second manufacturing step at least partially on the insulating layer 80, a first conductive layer 6 is arranged and wherein in the fourth manufacturing step at least partially on the first Conduction layer 6, a second conductive layer 6 'is arranged.
  • the first conductive layer 6 ' is arranged at least partially on the front side 3', on the rear side 3 ", on the side regions 3 '", on the support structures 5 and on the substrate 4.
  • the first conductive layer 6 comprises a multiplicity of first partial conductive layers, which are electrically insulated from one another and preferably in the region of each bonding pad an electrically conductive connection between a first partial conductive layer on the back 3 "and a first partial conductive layer on the front 3 'via a first partial conductive layer at the corresponding side regions 3 "'include.
  • the first metal layer is preferably electrically conductively connected to the integrated circuit 7 on the front side 3 'and functions to electrically contact the integrated circuit 7 on the front side 3' from the rear side 3 "
  • the second production step comprises, for structuring the first conductive layer 6, particularly preferably a first partial step, wherein a photoresist is applied to the first conductive layer 6, a second partial step, wherein the photoresist is exposed, a third substep, wherein the photoresist is developed and a fourth substep, wherein the first conductive layer 6 or the photoresist is etched.
  • the second conductive layer 6 ' is at least partially coated on the first conductive layer 6, the substrate 4 and / or the membrane 3 deposited by eiens galvanic process.
  • the first and / or second conductive layer 6, 6 ' preferably comprise a metal.
  • FIG. 6 shows a schematic side view of a sixth precursor structure for producing a component 1 according to the first embodiment of the present invention, the sixth precursor structure being completely identical to the fourth precursor structure illustrated in FIG. 4, FIG. 6 essentially, however, being a sectional view of FIG. 3b along a third cutting line 104 and not along the second cutting line 103 according to FIG. 4
  • the third production step for applying the insulation layer 80 to the third precursor structure is likewise illustrated with reference to the sixth precursor structure, wherein, in contrast to FIG. 4, no bond pads are arranged in the edge region of the membrane 3, but the membrane 4 is provided at the edge via a support structure 5 ''.
  • the insulation layer 80 is therefore only shown on the front side 3' of the membrane 3 in FIG. on the trench mask 8, in the side region 3 "'of the membrane 3, arranged on an outer side 500 of the support structure 5 exposed to the front side 3' and on the substrate 4 exposed towards the front side 3 '.
  • FIG. 7 shows a schematic partial side view of a seventh precursor structure for producing a device according to the first embodiment of the present invention, wherein the seventh precursor structure is completely identical to the fifth precursor structure illustrated in FIG. 5, but FIG. 7 shows the fifth precursor structure shown along the third intersection line 104 and not along the second cutting line 103, the second and fourth manufacturing steps for applying the first and second conductive layers 6, 6 'to the fourth and seventh precursor structures being likewise illustrated by the seventh precursor structure, wherein, in contrast to FIG.
  • the fifth and seventh precursors include the device 1 according to the first embodiment of the present invention.
  • FIG. 8 shows a schematic side view of a wafer composite 300 with a component 1 according to the first embodiment of the present invention, a third production step being illustrated in FIG. 8, the membrane 3 or the component 1 according to the first embodiment being illustrated by the substrate 4 separated and thus removed from the wafer composite 300.
  • the membrane 3 or the component 1 with a tool 202 of the Substrate 4 or the wafer composite 300 "picked" or broken off, the support structures 5 break through.
  • This breaking of the support structures 5 is preferably assisted by a swinging movement of a pickup head of the tool 202, the swinging movement particularly preferably involving an ultrasonic vibration in an x, y and / or z direction and / or torsional vibration in an x, y and / or or z-level.
  • FIG 9 shows a schematic side view of an eighth precursor structure for producing a component arrangement 10 according to a first embodiment of the present invention, a fifth production step being illustrated with reference to the eighth precursor structure, the component 1 preferably being mounted on a carrier element by the tool 202 illustrated in FIG 9 in the form of a printed circuit board, preferably a ceramic or LCP (Liquid Crystalline Polymers) plate, is arranged.
  • a carrier element 9 strip conductors 205 are arranged, wherein on the strip conductors 205 Lot 204 is arranged.
  • the component 1 For electrical contacting and mechanical fixing of the component 1 with the carrier element 9, the component 1 is placed on the carrier element 9 in such a way that via the solder 204 an electrically conductive and mechanically loadable connection between the conductor tracks 205 or connecting surfaces of the conductor paths 205 and the corresponding Bonding pads of the device 3, wherein the bond pads, the first and / or the second conductive layer 6, 6 'and / or the partial conductive layer on the back 3 "of the membrane 3, is produced Alternatively, the component 1 is immersed in a soldering bath in the fifth production step and the bonding pads are soldered to the conductor tracks 203.
  • the component 1 is glued to the printed conductors 203 by means of a conductive adhesive
  • the conductive adhesive preferably on the R Back of the device 1 and / or on the carrier element 9 is particularly preferably applied by screen printing, pad printing and / or by dispensing.
  • FIG. 10 shows a schematic side view of a component arrangement 10 according to the first embodiment of the present invention, wherein the component arrangement 10 shows the component 1 according to the first embodiment 1 arranged on the carrier element 9, wherein the component arrangement 10 an electrically conductive contact between the integrated circuit 7 on the relatively thin membrane 3 and the interconnects 205 of the carrier element 9 by means of the first conductive layer 6, the second conductive layer 6 ', the partial conductive layer and / or a bonding pads on the back 3 "of the membrane 3, wherein the first conductive layer 6, the second conductive layer 6 ', the partial conductive layer and / or the bonding pad on the back 3" of the membrane 3 by means of a soldered joint mechanically resilient and electrically conductive with the conductor tracks 205 are connected.
  • FIG. 11 shows a schematic side view of a component arrangement 10 according to a second embodiment of the present invention, wherein the second embodiment is substantially identical to the first embodiment shown in Figure 10, wherein on a side facing away from the carrier element 9 of the device 1, a further component V is arranged on the component 1 such that between the further component V and the carrier element 9, the component 1 is arranged congruently with the further component V perpendicular to the main extension plane 100.
  • the further component V is preferably identical in construction to the component 1, with further first conductive layers 60, further second conductive layers 60 ', further partial conductive layers and / or further bond pads on the further back 3' of the further component 1 'with further bond pads, bond pads, partial conductive layer, first conductive layers 6 and / or second conductive layers 6 'on the front side 3' of the device 1 electrically conductive and mechanically strong in particular via conductive connecting elements 400 are connected, so that both the device 1, and the further component V of the carrier element 9 from contactable It is conceivable to expand the component arrangement 10 according to the second embodiment by a plurality of further components 1 'and thus to arrange a stack of a multiplicity of congruently arranged further components 1' perpendicular to the main extension plane 100 one above the other.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Micromachines (AREA)
  • Pressure Sensors (AREA)
  • Measuring Fluid Pressure (AREA)
  • Semiconductor Memories (AREA)
  • Transducers For Ultrasonic Waves (AREA)

Abstract

La présente invention concerne un procédé de réalisation d'un composant, une première étape du procédé de réalisation consistant à fournir une structure de base comprenant un substrat, une membrane et une zone de cavité. Selon l'invention, la membrane est disposée sensiblement parallèlement à un plan d'extension principale du substrat, la zone de cavité est disposée entre le substrat et la membrane, et la zone de cavité présente une ouverture d'accès. Une deuxième étape du procédé de réalisation consiste à appliquer au moins partiellement une première couche conductrice dans la zone de cavité et en particulier sur un second côté de la membrane, orienté vers le substrat perpendiculairement au plan d'extension principale.
EP09779687A 2008-07-18 2009-06-09 Procédé de réalisation d'un composant, procédé de réalisation d'un système de composants, composant et système de composants correspondants Withdrawn EP2313338A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008040521A DE102008040521A1 (de) 2008-07-18 2008-07-18 Verfahren zur Herstellung eines Bauelements, Verfahren zur Herstellung einer Bauelementanordnung, Bauelement und Bauelementanordnung
PCT/EP2009/057106 WO2010006849A2 (fr) 2008-07-18 2009-06-09 Procédé de réalisation d'un composant, procédé de réalisation d'un système de composants, composant et système de composants correspondants

Publications (1)

Publication Number Publication Date
EP2313338A2 true EP2313338A2 (fr) 2011-04-27

Family

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Family Applications (1)

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EP09779687A Withdrawn EP2313338A2 (fr) 2008-07-18 2009-06-09 Procédé de réalisation d'un composant, procédé de réalisation d'un système de composants, composant et système de composants correspondants

Country Status (6)

Country Link
US (1) US20110169107A1 (fr)
EP (1) EP2313338A2 (fr)
CN (1) CN102099281B (fr)
DE (1) DE102008040521A1 (fr)
TW (1) TWI534068B (fr)
WO (1) WO2010006849A2 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008041942A1 (de) * 2008-09-10 2010-03-11 Robert Bosch Gmbh Sensoranordnung, Verfahren zum Betrieb einer Sensoranordnung und Verfahren zur Herstellung einer Sensoranordnung
DE102009046081B4 (de) * 2009-10-28 2021-08-26 Robert Bosch Gmbh Eutektische Bondung von Dünnchips auf einem Trägersubstrat
DE102009046800B4 (de) 2009-11-18 2024-08-14 Robert Bosch Gmbh Verfahren zur Herstellung einer Vielzahl von Dünnchips und entsprechend gefertigter Dünnchip
US9266721B2 (en) 2010-11-23 2016-02-23 Robert Bosch Gmbh Eutectic bonding of thin chips on a carrier substrate
US8628677B2 (en) * 2011-03-31 2014-01-14 Fujifilm Corporation Forming curved features using a shadow mask
US8989070B2 (en) 2012-07-02 2015-03-24 Intel Corporation Apparatus and method to efficiently send device trigger messages
US10833832B2 (en) 2016-06-22 2020-11-10 Intel Corporation Communication device and a method for full duplex scheduling
DE102018222730A1 (de) 2018-12-21 2020-06-25 Robert Bosch Gmbh Mikromechanisches Bauteil und Herstellungsverfahren für ein mikromechanisches Bauteil
US11911904B2 (en) * 2020-07-15 2024-02-27 Micron Technology, Inc. Apparatus and methods for enhanced microelectronic device handling

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030222335A1 (en) * 2002-05-30 2003-12-04 Matsushita Electric Industrial Co., Ltd. Circuit component, circuit component package,, circuit component built-in module, circuit component package production and circuit component built-in module production
US20050084998A1 (en) * 2003-10-21 2005-04-21 Horning Robert D. Methods and systems for providing MEMS devices with a top cap and upper sense plate
US20060273430A1 (en) * 2005-03-24 2006-12-07 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177661A (en) * 1989-01-13 1993-01-05 Kopin Corporation SOI diaphgram sensor
KR100243741B1 (ko) * 1996-12-27 2000-02-01 김영환 반도체 소자의 제조방법
US6142358A (en) * 1997-05-31 2000-11-07 The Regents Of The University Of California Wafer-to-wafer transfer of microstructures using break-away tethers
IL133453A0 (en) * 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
FI115500B (fi) * 2000-03-21 2005-05-13 Nokia Oyj Menetelmä kalvoanturin valmistamiseksi
DE10032579B4 (de) 2000-07-05 2020-07-02 Robert Bosch Gmbh Verfahren zur Herstellung eines Halbleiterbauelements sowie ein nach dem Verfahren hergestelltes Halbleiterbauelement
US6936491B2 (en) * 2003-06-04 2005-08-30 Robert Bosch Gmbh Method of fabricating microelectromechanical systems and devices having trench isolated contacts
DE102004036032A1 (de) 2003-12-16 2005-07-21 Robert Bosch Gmbh Verfahren zur Herstellung eines Halbleiterbauelements sowie ein Halbleiterbauelement, insbesondere ein Membransensor
KR101217157B1 (ko) * 2005-10-20 2012-12-31 엘지디스플레이 주식회사 액정표시장치용 어레이 기판 및 그 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030222335A1 (en) * 2002-05-30 2003-12-04 Matsushita Electric Industrial Co., Ltd. Circuit component, circuit component package,, circuit component built-in module, circuit component package production and circuit component built-in module production
US20050084998A1 (en) * 2003-10-21 2005-04-21 Horning Robert D. Methods and systems for providing MEMS devices with a top cap and upper sense plate
US20060273430A1 (en) * 2005-03-24 2006-12-07 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes

Also Published As

Publication number Publication date
TWI534068B (zh) 2016-05-21
US20110169107A1 (en) 2011-07-14
TW201016594A (en) 2010-05-01
CN102099281A (zh) 2011-06-15
WO2010006849A3 (fr) 2010-12-29
WO2010006849A2 (fr) 2010-01-21
CN102099281B (zh) 2015-07-08
DE102008040521A1 (de) 2010-01-21

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