EP2232533A1 - Löcher oder gräben mit hohem aspektverhältnis - Google Patents
Löcher oder gräben mit hohem aspektverhältnisInfo
- Publication number
- EP2232533A1 EP2232533A1 EP08871114A EP08871114A EP2232533A1 EP 2232533 A1 EP2232533 A1 EP 2232533A1 EP 08871114 A EP08871114 A EP 08871114A EP 08871114 A EP08871114 A EP 08871114A EP 2232533 A1 EP2232533 A1 EP 2232533A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- aspect ratio
- holes
- layer
- hole
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 claims abstract description 73
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 40
- 238000005530 etching Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000000407 epitaxy Methods 0.000 claims description 9
- 239000000203 mixture Substances 0.000 claims description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 20
- 239000000463 material Substances 0.000 abstract description 15
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 4
- 238000001039 wet etching Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 43
- 238000000151 deposition Methods 0.000 description 14
- 238000011049 filling Methods 0.000 description 12
- 230000008021 deposition Effects 0.000 description 11
- 235000012431 wafers Nutrition 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000009623 Bosch process Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 235000012489 doughnuts Nutrition 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 substrate Chemical compound 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- the present invention relates to a method to increase throughput when manufacturing high Aspect Ratio (AR) holes or trenches, and high AR holes or trenches obtained by said method.
- AR Aspect Ratio
- holes or trenches are etched, using dry or wet etching techniques, typically dry etching is preferred.
- a third dimension e.g. of a silicon wafer
- a deep silicon etch is required and further high aspect structures are designed.
- Many products with high aspect holes are in production or development like deep trench capacities, Trench MOSFET, DRAM capacities, through wafer via interconnects, etc.
- Document US2004/0180510 Al discloses methods of producing trench structures having substantially void- free filler materials therein.
- the fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench.
- Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.
- Document US2005/0153507 Al discloses a fabrication method for a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact. After forming and sinking an electrically conductive filling, an insulation collar and, if appropriate, a buried contact that is connected on all sides, the following are effected: providing at least one liner layer in the trench; filling the trench with a filling made of an auxiliary material, which filling is encapsulated by the at least one liner layer in the trench; providing a mask on the filling for defining the structure of the buried contact, the mask having no projections into the trench; removing a part of the filling using the mask; removing an underlying part of the at least one liner layer for uncovering a corresponding part of the insulation collar.
- D2 and D3 seem to disclose the use of silicon liners, which is of the same material as the substrate, but not of the same crystal or poly-crystalline structure. Further, these liners only temporarily reduces the aspect ratio, as they are removed during further processing. As seems standard practice in such cases, the liner is removed during the process of forming holes, and therefore the silicon liner does not directly reduce the final aspect ratio. In fact, it remains largely the same, as the liner does not or at the most to a small extend appear in the final trench.
- Document US2006/0264054 Al (D4) discloses a method for etching a trench in a semiconductor substrate. More specifically, the present invention relates to a method for etching deep trenches such as those having aspect ratios of 30 and higher.
- a method for etching a trench in a semiconductor substrate includes a first etch cycle wherein the trench is etched to a first depth. Thereafter, a protective liner is deposited on at least the upper part of the trench's sidewalls. The protective liner includes inorganic material. During at least one second etch cycle, the trench is etched to its final depth.
- the substrate is made from another material, which serves as a protective layer, such as SiGe. It is not made of the same material as the substrate, such as Si.
- the liners are not of identical composition to the substrate although they might be Si based or be based on the same material as being used for the substrates. It is noted that the use of liner to reduce the aspect ratio, must, however, be of a different material than that of the substrate to get a selective etch of silicon and not the spacer.
- Etching of wafers as well as certain techniques of deposition of layers, such as techniques as CVD, epitaxy, etc. are very costly, because in certain cases only one wafer can be produced at the same time. So reduction of process time would benefit the costs of processing.
- the person skilled in the art would not consider adding process steps to an existing process, as the total process time and costs would increase, which is in general considered as a disadvantage.
- the objective of the present invention is to remove disadvantages of the prior art, especially those relating to costs and process time.
- existing advantages, such as high aspect ratios of holes, should be maintained.
- the overall idea of the present invention is to increase the aspect ratio in general, by applying a layer in a hole. This is especially economically interesting for a high aspect ratio.
- the aspect ratio of a two-dimensional shape is the ratio of its longer dimension to its shorter dimension. It also applies to two characteristic dimensions of a three- dimensional shape, especially for the longest and shortest 'axes' or for symmetrical objects (e.g. rods or holes) that are described by just two measures (e.g. length and diameter or width). In such cases, the aspect ratio may evaluate to a value less than one (e.g. consider very short and very long rods).
- etch rate is size dependent, instead of etching a very small hole or trench that would require a very long processing, a larger hole or trench is etched, which is then filled with material to get the same aspect ratio, but with a shorter process time. This is due to an etch process time that is smaller because of the higher size structure and deposition techniques that are less expensive in terms of time and cost because of batch processing. The extra process costs are much lower than the large costs induced by a very long dry etch process.
- the present invention relates to a method of forming one or more holes in a substrate, comprising the steps of: providing a substrate having a composition, forming a mask, etching one or more holes in the substrate, which one or more holes have an initial aspect ratio, a depth and a width, which depth and width may vary from hole to hole, and applying a layer, which layer has the same composition as the substrate, preferably having the same crystal structure as the substrate, thereby forming holes which have a final aspect ratio, which final aspect ratio is smaller than the initial aspect ratio, which layer is substantially not removed.
- the present invention is equally well applicable to the formation of trenches, or squares, or donut shaped forms, or oblong structures, or combinations thereof.
- the term "hole” also means a trench, or any other structure having an aspect ratio.
- the present method increases the aspect ratio of said structure.
- the substrate can be any substrate, such as silicon, silicon oxide, silicon- germanium, etc, but preferably is silicon.
- a standard lithographic step is used, wherein a resist is used to protect part of the substrate that is not intended to be etched, and to have another part of the substrate available wherein one or more holes are etched.
- an etch step is applied to actually form one or more holes.
- the etch step is a dry etch step, such as BOSH or RIE, preferably by RIE.
- the RIE process is used to obtain an anisotropic etch.
- a continuous Si etching process is composed only of an etching process. Therefore etching chemistry is often based on e.g. SF 6 ZHBr or SF 6 ZO 2 . In such an etch step it is more difficult to obtain a very high aspect ratio via, as sidewall passivation control is considered more difficult.
- BOSCH process Another process known to obtain a very high aspect ratio via is the so-called BOSCH process.
- This BOSCH process is in fact a RIE etch, with cycles of etching and passivation. As the energy of the ion used is mostly perpendicular to the substrate, the sidewall passivation is not removed, and as a consequence the BOSCH process is improving the anisotropy.
- the BOSCH Si etching process comprises the steps of:
- Si Etch Pulse Si is etched isotropically by F radicals generated in a plasma of a fluorinated gas such as SF 6 .
- Passivation Pulse A layer of passivation polymer is deposited by dissociating a fluorocarbon precursor gas such as C 4 Fs in a plasma.
- - Depassivation Pulse The passivation polymer at the bottom of the etched features is preferentially removed mainly by ion bombardment.
- Pressures are typically in the order of tens of mTorr;
- RF power for plasma density: Thoussands of Watts;
- RF bias for ion energy: hundreds of Watts
- Temperature from cryogenic to room temperature; and - Gas flow: several seem (standard cubic centimer per minute).
- dry etch may be used as well, such as wet etch using KOH, or TMAH.
- wet etch process is an isotropic etching process. Further there are contamination issues. Therefore, in general dry etch is preferred.
- one or more holes are formed, which have a certain depth and a certain width, and thus an initial aspect ratio. It is also envisaged that depth and width may vary from hole to hole, thus at this stage the substrate may comprise various holes, which holes may each have a specific aspect ratio, width, and depth, respectively, varying from hole to hole, in a controlled and objected manner. Thereafter a layer is applied. Said layer has the same composition as the substrate.
- the layer has the same crystal structure as the substrate, e.g. in case of silicon the layer is an epitaxial grown layer.
- the layer is applied, specifically the width of the holes is reduced. It is noted that also the depth is reduced, but this effect is relatively small.
- the layer is typically also applied on the substrate. As a consequence especially the width of the one or more holes is reduced, by approximately two times the thickness of the layer applied. Thus, the aspect ratio is increased. However, as can for instance be seen in Fig. 3, the hole is only partly filled, i.e. is still open.
- the initial aspect ratio was d/Wl
- the final aspect ratio is approximately d/(Wl-2h) or d/W2.
- W2 ⁇ Wl the final aspect ratio is larger than the initial aspect ratio.
- the layer applied does not function as a protective layer or barrier, for instance for an underlying layer or structure.
- the layer applied is substantially not removed, i.e. it remains largely as it was after being applied.
- further processing steps could have some influence on the layer thickness or integrity of the layer, due to process conditions and chemicals used in such steps, but this influence is very small and furthermore, it does not differ significantly from further process steps used in the prior art, as these further process steps largely have the same or similar objective, such as filling of contacts, vias or trenches.
- the holes have an initial aspect ratio, which is a high aspect ratio, preferably larger than 4:1, more preferably larger than 8:1, even more preferably larger than 12:1, most preferably larger than 16:1, such as 20:1.
- the total process time for the present method, comprising etch and epitaxy, with respect to the prior art, for a specific or given aspect ratio reduces most for high aspect ratios.
- the present invention is most favorable for holes with high aspect ratios.
- the initial aspect ratio is at least 1.3 times smaller than the final aspect ratio, preferably at least 1.5 times smaller, even more preferably at least 1.7 times smaller, even more preferably at least 2.0 times smaller, most preferably at least 3.0 times smaller, such as 4.0 times smaller.
- the effect of the present method is most favorable when the diameter of the holes is reduced most, i.e. wherein the final aspect ratio is much larger than the initial aspect ratio.
- the substrate is silicon or an oxide, such as silicon oxide.
- the holes formed may be holes for capacities, through wafer vias, trenches, such as STI, contacts and vias filled with a conductor for connecting metal layers, and holes or structures that require a high aspect ratio in general.
- the layer is applied by epitaxy, LPCVD, MOCVD, plasma enhanced CVD, MBE (Molecular Beam Epitaxy), preferably epitaxy or LPCVD, most preferably epitaxy.
- the layer has a thickness of more than 0.05 times the width of the initial hole, more preferably at a thickness of more than 0.1 times the width of the initial hole, even more preferably at a thickness of more than 0.2 times the width of the initial hole, such as more than 0.25 times the width of the initial hole.
- a thicker layer reduces the aspect ratio the most.
- the substrate material could be a silicon like substrate, but could be also be germanium, which has very similar characteristics as silicon. Also glass substrates could be used, such as dielectric materials, such as SiO 2 .
- the material applied for the layer would in that case be SiO 2 , which could be applied by deposition of SiO 2 PECVD, or TEOS LPCVD.
- the hole is for a deep trench capacity, a trench MOSFET, a DRAM capacity, a through wafer via interconnect, a via, a connect, or combinations thereof. It is noted that with a higher aspect ratio, the time for filling a hole is also shorter. This is for instance important for a subsequent metal filling, which filling typically is a single wafer process. In the latter case it is then easier to close the hole and avoid any problems for a remaining process to be performed, such as a spin coating deposition.
- a via of 25 ⁇ m diameter can be filled by copper electroplating, wherein copper is just an example for a metal, with a high throughput and a better uniformity than filling a via of 50 ⁇ m diameter by copper electroplating, so it that sense it is easier.
- the present invention relates to one or more holes in a substrate, which holes have an initial aspect ratio relating to the one or more holes before applying a further layer as described above, further comprising a layer, which layer has the same composition as the substrate, thereby forming holes which have a final aspect ratio, which final aspect ratio is smaller than the initial aspect ratio.
- the present invention relates to a semiconductor device, made by a method according to the invention.
- the present invention relates to an IC comprising holes according to the invention.
- the present invention is further elucidated by the following Figures and examples, which are not intended to limit the scope of the invention. The person skilled in the art will understand that various embodiments may be combined.
- Fig. 1 shows an etch rate of a standard process as function of hole diameter.
- Fig. 2 shows a prior art hole formation
- Fig. 3 shows a hole formation according to the present invention.
- Fig. 4 shows a SEM photograph of hole according to the invention with EPI growth.
- Fig. 5 shows a SEM photograph of hole according to the invention with EPI growth.
- Fig. 1 shows an etch rate of a standard process as function of hole diameter.
- the etch rate expressed as ⁇ m /min
- the hole diameter expressed in ⁇ m.
- the Figure shows that for a small hole diameter the etch rate is also relatively small. Going from left to right, as the hole diameter increases, also the etch rate increases. It is noted that specifically for small hole diameters the etch rate is relatively small, which etch rate does not increase relatively that much at higher hole diameters.
- a hole surface could be considered to be infinite, but for a small hole diameter, volatile species experience difficulties to get out of hole because of for instance collisions, and as a consequence the etchrate drops.
- This phenomenom is known as Aspect ratio Dependent Etch (ARDE).
- Fig. 2 shows a prior art hole formation. The hole is formed by applying a lithographic mask and etching a hole in a substrate.
- Fig. 3 shows a hole formation according to the present invention.
- First a hole is etched, in a similar way as in Fig. 2.
- the hole diameter is much larger than in the case of Fig. 2.
- the initial aspect ratio is much smaller.
- the hole is partly filled by applying a layer.
- the layer is applied, specifically the width of the holes is reduced. It is noted that also the depth is reduced, but this effect is relatively small.
- the layer is typically also applied on the substrate. As a consequence especially the width of the one or more holes is reduced, by approximately two times the thickness of the layer applied.
- the aspect ratio is increased.
- the initial aspect ratio was d/Wl
- the final aspect ratio is approximately d/(Wl-2h) or d/W2.
- W2 ⁇ Wl the final aspect ratio is larger than the initial aspect ratio.
- the invention specifically relates to deep silicon holes filled with silicon deposition, where batch processing for those deposition techniques exists.
- the present could be extented to any high aspect ratio etch process.
- contact holes for CMOS processing are done in oxide.
- a less constraint etch could than be done, whereafter the contact is then filled with a material.
- an issue is the temperature budget.
- back end processing because of the metal layers, it is not possible to process to high temperature.
- precautions are taken with respect to this concern, it is possible to extent the present invention to those materials.
- Fig. 4 shows a SEM photograph of hole according to the invention which has been partly filled by applying EPI growth.
- Fig. 5 shows a SEM photograph of another hole according to the invention with EPI growth, but the resulting layer is poly-crystalline or with a high defect density.
- the present invention reduces an initial diameter, being 50 ⁇ m in the example, to a final diameter of 25 ⁇ m (not given in the table). From the above table, it is shown that the 10:1 aspect ratio hole is obtained by combining dry etch and epitaxy in only 88% of the time of a comparable single dry etch process of the prior art. For the 14:1 aspect ratio hole only 83% of the time is needed. For larger aspect ratios the reduction is even more significant. Thus, for holes with relatively large aspect ratios, a reduction in process time of more than 10% is achieved, often more than 15%, and in many cases a reduction of more than 20% process time is achieved.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08871114A EP2232533A1 (de) | 2008-01-16 | 2008-12-30 | Löcher oder gräben mit hohem aspektverhältnis |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08100543 | 2008-01-16 | ||
EP08871114A EP2232533A1 (de) | 2008-01-16 | 2008-12-30 | Löcher oder gräben mit hohem aspektverhältnis |
PCT/IB2008/055579 WO2009090520A1 (en) | 2008-01-16 | 2008-12-30 | High aspect ratio holes or trenches |
Publications (1)
Publication Number | Publication Date |
---|---|
EP2232533A1 true EP2232533A1 (de) | 2010-09-29 |
Family
ID=40430166
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP08871114A Ceased EP2232533A1 (de) | 2008-01-16 | 2008-12-30 | Löcher oder gräben mit hohem aspektverhältnis |
Country Status (2)
Country | Link |
---|---|
EP (1) | EP2232533A1 (de) |
WO (1) | WO2009090520A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103824767B (zh) * | 2012-11-16 | 2017-05-17 | 中微半导体设备(上海)有限公司 | 一种深硅通孔的刻蚀方法 |
CN105374675B (zh) * | 2013-12-03 | 2018-02-09 | 中微半导体设备(上海)有限公司 | 半导体结构的形成方法 |
CN106564855B (zh) * | 2015-10-08 | 2019-05-31 | 北京北方华创微电子装备有限公司 | 一种深硅刻蚀方法 |
EP3637448A4 (de) | 2018-08-21 | 2020-10-07 | Shenzhen Weitongbo Technology Co., Ltd. | Kondensator und herstellungsverfahren dafür |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4420962A1 (de) * | 1994-06-16 | 1995-12-21 | Bosch Gmbh Robert | Verfahren zur Bearbeitung von Silizium |
US20070212888A1 (en) * | 2004-03-29 | 2007-09-13 | Sumitomo Precision Products Co., Ltd. | Silicon Substrate Etching Method |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01125971A (ja) * | 1987-11-11 | 1989-05-18 | Seiko Instr & Electron Ltd | C−mis型半導体装置とその製造方法 |
US6821864B2 (en) * | 2002-03-07 | 2004-11-23 | International Business Machines Corporation | Method to achieve increased trench depth, independent of CD as defined by lithography |
KR100473476B1 (ko) * | 2002-07-04 | 2005-03-10 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
KR100559518B1 (ko) * | 2003-12-31 | 2006-03-15 | 동부아남반도체 주식회사 | 반도체의 에스티아이 형성방법 |
US7390710B2 (en) * | 2004-09-02 | 2008-06-24 | Micron Technology, Inc. | Protection of tunnel dielectric using epitaxial silicon |
KR100791342B1 (ko) * | 2006-08-09 | 2008-01-03 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
-
2008
- 2008-12-30 EP EP08871114A patent/EP2232533A1/de not_active Ceased
- 2008-12-30 WO PCT/IB2008/055579 patent/WO2009090520A1/en active Application Filing
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CHOLLET F ET AL: "Si(100) epitaxy by low-temperature UHV-CVD: AFM study of the initial stages of growth", JOURNAL OF CRYSTAL GROWTH, ELSEVIER, AMSTERDAM, NL, vol. 157, no. 1, 1 December 1995 (1995-12-01), pages 161 - 167, XP004001551, ISSN: 0022-0248, DOI: 10.1016/0022-0248(95)00382-7 * |
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