EP2109890A2 - Circuit mosfet a mode d'appauvrissement et applications - Google Patents

Circuit mosfet a mode d'appauvrissement et applications

Info

Publication number
EP2109890A2
EP2109890A2 EP08728213A EP08728213A EP2109890A2 EP 2109890 A2 EP2109890 A2 EP 2109890A2 EP 08728213 A EP08728213 A EP 08728213A EP 08728213 A EP08728213 A EP 08728213A EP 2109890 A2 EP2109890 A2 EP 2109890A2
Authority
EP
European Patent Office
Prior art keywords
terminal
type
transistor
coupled
mosfet transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08728213A
Other languages
German (de)
English (en)
Other versions
EP2109890A4 (fr
Inventor
Went T. Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Keystone Semiconductor Inc
Original Assignee
Keystone Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Keystone Semiconductor Inc filed Critical Keystone Semiconductor Inc
Priority to EP10172462A priority Critical patent/EP2287909A2/fr
Priority to EP10172459A priority patent/EP2287908A2/fr
Publication of EP2109890A2 publication Critical patent/EP2109890A2/fr
Publication of EP2109890A4 publication Critical patent/EP2109890A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Definitions

  • the present invention relates to the field of metal oxide semiconductor field effect transistors (MOSFET), and more particularly, to the simulation and use of depletion mode MOSFETs for electronic circuits, including electrostatic discharge protection circuits, Boolean logic circuits, buffering circuits and memory circuits.
  • MOSFET metal oxide semiconductor field effect transistors
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • MOSFET' s can be fabricated to operate in two fundamentally different ways, commonly called enhancement-mode and depletion-mode, operation.
  • enhancement-mode operation the MOSFET is in an "off state unless a voltage is applied to the gate terminal to switch the transistor to an "on” state.
  • depletion-mode operation the MOSFET is in an "on” state and requires a voltage applied to the gate terminal to switch the transistor to an "off state.
  • MOSFETs operaterating in enhancement-mode are often termed enhancement type MOSFETs and may be either N-channel or P-channel.
  • MOSFETs operating in depletion-mode are often termed depletion type MOSFETs and may be either N-channel or P-channel.
  • the enhancement type MOSFET is simple to use, since the channel between drain and source becomes conductive only after the gate to source junction is energized, as shown in curves 142 and 144.
  • the N type enhancement MOSFET is initially off, with no current Ids flowing when Vgs is zero, and becomes more conductive as V GS is made more positive, allowing a greater current Ids to flow from drain to source, as seen in curve 142.
  • the P type enhancement MOSFET is initially off, with no current flowing when Vgs is zero, and becomes more conductive, allowing a greater current to flow from drain to source as V GS become more negative, as seen in curve 144.
  • a depletion type MOSFET can be thought of as having two modes of operation, as shown in curves 114 and 116.
  • the N-type depletion MOSFET 114 has a depletion-mode in which the bias voltage at the gate, Vgs, is either zero or negative. In this mode, the N-type depletion MOSFET is "on", allowing a current to flow from drain to source, when the voltage is zero. As the bias voltage at the gate, Vgs, is made more negative, the current decreases and eventually stops, so that the MOSFET is "off.
  • the other mode of operation of the N-type depletion MOSFET is the enhancement mode, when the bias voltage at the gate, Vgs, varies from zero to more positive. At zero voltage, a current flows that may be considered as a large leakage current. As the bias voltage at the gate, Vgs, is increased the drain to source current increases, or is enhanced, just as in an N-type enhancement MOSFET.
  • the depletion type MOSFET operation shown in curves 114 and 116, may also be thought of as a shifted version of enhancement type MOSFETs. For instance, N type depletion MOSFET curve 114 is similar to the N type enhancement
  • SPICE Simulation Program with IC Emphasis
  • MOSFET logic can only be used for "negative-logic” circuits such as, for instance, Boolean NAND or NOR gates, rather than "positive-logic” circuits such as, for instance, AND or OR gates.
  • the invention provides integrated circuit (IC) designs using depletion-mode MOSFET circuits made possible by a pin assignment method of dealing with software simulation of depletion-mode operation of MOSFETS.
  • the IC design includes a static, random access memory device that includes a memory, buffer cell comprising at least one depletion
  • a two-transistor static random access memory cell that includes an enhancement MOSFET transistor forming a two-transistor static random access memory cell.
  • the IC design is a one-transistor, one-resistor, non-inverting buffer that may, with the further addition of an N type enhancement MOSFET transistor may be used to form a two-transistor, 1 resistor, static random access memory.
  • the IC design is a two transistor, non-inverting buffer that includes two opposite type, depletion type MOSFETs. The addition of an N type enhancement MOSFET transistor the formation of a three-transistor static random access memory cell.
  • the IC design is a four-transistor boolean logic circuit comprising at least two depletion MOSFET transistors that may be an AND Boolean logic circuit, an OR Boolean logic circuit or a mixed AND Boolean logic circuit.
  • the IC design is an electrostatic discharge protection circuit, that includes an N type depletion MOSFET transistor and a P type depletion MOSFET transistor.
  • Figure 1 the transfer characteristics of MOSFETs.
  • Figure 2 the schematic diagram for an inverter (prior art).
  • Figure 3 the schematic diagram for a non-inverting buffer using depletion
  • Figure 4 the physical model for the non-inverting buffer as shown in Figure 3.
  • Figure 5 the schematic diagram for the basic ESD protection using diodes (prior art).
  • Figure 6 the schematic diagram for the ESD protection using depletion
  • MOSFET as the first preferred embodiment.
  • FIG. 7 the schematic diagram for a non-inverting buffer using depletion
  • Figure 8 the schematic diagram for a latch using depletion MOSFETs.
  • Figure 9 the schematic diagram for a 3T-SRAM cell as the second preferred embodiment.
  • FIG. 10 the schematic diagram of an AND logic gate using depletion type
  • Figure 11 the schematic diagram of an OR logic gate using depletion type MOSFETs.
  • Figure 12 the schematic diagram of a basic master-slave flip-flop.
  • Figure 13 the schematic diagram for T-gate (prior art).
  • Figure 14 the schematic diagram for a master-slave flip-flop with reset input.
  • Figure 15 the schematic diagram for a master-slave flip-flop with set input.
  • Figure 16 the schematic diagram of a non-inverting buffer using a P type depletion MOSFET and a resistor.
  • Figure 17 the schematic diagram of a non-inverting buffer using an N type depletion MOSFET and a resistor.
  • Figure 18 the schematic diagram of a latch using a P type depletion MOSFET and a resistor.
  • Figure 19 the schematic diagram of a latch using an N type depletion MOSFET and a resistor.
  • Figure 20 the schematic diagram of a 2T1R-SRAM cell using N type depletion
  • MOSFET as an alternate embodiment.
  • Figure 21 the schematic diagram of a 2T1R-SRAM cell using P type depletion MOSFET as an alternate embodiment.
  • Figure 22 the schematic diagram of a reverse-biased diode using P-type depletion MOSFET.
  • Figure 23 the schematic diagram of a reverse-biased diode using N-type depletion MOSFET.
  • Figure 24 the schematic diagram of a non-inverting buffer using a single P type depletion MOSFET.
  • Figure 25 the schematic diagram of a non-inverting buffer using a single N type depletion MOSFET.
  • Figure 26 the schematic diagram of a latch using a single P type depletion MOSFET.
  • Figure 27 the schematic diagram of a latch using a single N type depletion
  • Figure 28 the schematic diagram of a 2T-SRAM cell using a single N type depletion MOSFET as an alternate embodiment.
  • Figure 29 the schematic diagram of a 2T-SRAM cell using a single P type depletion MOSFET as an alternate embodiment.
  • Figure 30 the schematic diagram of a mixed AND logic gate (/A)B using both enhancement and depletion MOSFETs.
  • Figure 31 the schematic diagram of a mixed OR logic gate (/A)+B using both enhancement and depletion MOSFETs.
  • Figure 32 the schematic diagram for the test circuit #1 to verify the SPICE model.
  • Figure 33 the schematic diagram for the test circuit #2 to prove the unlatched state of 2T-SRAM.
  • MOSFET 142 and a P type enhancement MOSFET 144 as shown in figure 2. If the concept of voltage to used identify the source and drain, then the source of the P type
  • MOSFET 144 is connected to the drain of the N type MOSFET 142 and is the also output pin 108 of the inverter 111. This produces a problem when the input at the gate is at logic low since there is no way to guarantee that the output pin will be at logic high.
  • the method of pin assignment using DC voltage mentioned above can only be applied to N type device and the pins assignment must be reversed for P type device.
  • the pin that has a higher DC voltage must be the source and the pin with lower DC voltage must be the drain.
  • these voltage rules be used for enhancement type MOSFETs. This is how the SPICE program identifies the pins of the MOSFET before executing the simulation. Since, in SPICE, the depletion MOSFET is treated as aderivative of enhancement MOSFET, the same voltage rules are used for both the enhancement type MOSFET and depletion type MOSFET.
  • the source of the P type MOSFET in the inverter example of Figure 2 will then be connected to the Vdd power supply pin and source of the N type MOSFET is connected to ground.
  • the drains of both transistors are connected together as the output pin.
  • the method of using majority current carrier to identify the source and drain pins is more accurate and can successfully explain the operation of enhancement MOSFET. Unfortunately, using the majority current carrier method prevents simulating depletion- mode MOSFET operation.
  • the depletion type MOSFET operated in the depletion mode is simply a switch that is normally ON until the junction between the gate and source is energized.
  • the depletion type MOSFET really does not care what voltage the drain and source pins are connected to.
  • the only thing that matters to a depletion type MOSFET operated in the depletion mode is whether if there is a voltage across the junction between the gate and source to energize the transistor and to pinch off the channel between drain and source.
  • the gate of an N type depletion MOSFET 114 needs a negative voltage with respect to the source to induce positive charges in the channel between drain and source.
  • Vdd 110 When the N type depletion MOSFET 114 is connected to Vdd 110 which is the highest possible voltage of the system, the Vdd pin 110 will produce the highest negative potential difference to the voltage at the gate to pinch off the channel between the drain and source.
  • the pin that is connected to Vdd 110 should, for the purpose of simulation, be regarded as the source pin for the N type depletion MOSFET 114 since this is where pinch-off first occurs.
  • the source pin of a MOSFET should simply be the pin that produces either the most of the majority current carrier or the pinch-off. This definition of the source pin produces accurate and correct results for the all types of MOSFETs under all operating conditions and should be the only rule for the computer simulation to identify the source and drain pins.
  • VGS to be within 0 to Vdd for the P type depletion MOSFET 116 as shown in the figure 1.
  • the ground pin 112 is the drain pin to the SPICE program and the source pin is also the output pin 108.
  • the VGS is always negative so that a current larger than the IDSS 103 will flow in the drain to source channel.
  • the voltage at the gate input 106 is at Vdd 110; since the voltage at the source 108 will never be higher than the voltage at the gate input 106, the VGS will become positive and the current flowing through the drain and source channel becomes smaller than IDSS 103.
  • the SPICE program will never allow the P type depletion MOSFET 116 to become pinch-off when the voltage at the gate input 106 is ranged between ground 112 and Vdd 110 because the voltage at the gate input 106 must be much higher than the voltage at the source in order to produce pinch-off; but the higher the VGS becomes, the less current will flow through the drain to source channel so that the voltage at the source 108 become higher to reduce the VGS.
  • the SPICE program it is impossible for the SPICE program to completely pinch off the drain to source channel because once the channel is pinched off, the voltage at the source 108 will become Vdd 110 and a current of IDSS 103 will flow through the channel again. Consequently, the VGS will never become large enough to pinch off the channel between drain and source completely.
  • the only way to produce pinch-off using the SPICE program is to raise the voltage at the gate input 106 to be much higher than Vdd 110 because the voltage at the source output 108 will never be higher than Vdd.
  • the ground pin 112 should then be termed the source pin for the purposes of SPICE simulation for the P depletion type MOSFET 116.
  • the circuit as shown in Figure 3 becomes a non-inverter buffer.
  • the non-inverting buffer of Figure 3 includes a depletion MOSFET transistor that is a P type transistor.
  • This depletion MOSFET transistor preferably has a gate terminal coupled to an input terminal, a substrate terminal coupled to a positive voltage supply terminal and a source terminal coupled to a ground terminal.
  • the circuit includes a resistor having a first terminal coupled to the drain terminal of the P type depletion MOSFET transistor, and a second terminal coupled to said positive voltage supply terminal, thereby forming a one-transistor, one resistor non- inverting buffer.
  • ESD electrostatic discharge
  • the electrostatic discharge (ESD) is a very damaging phenomenon affecting the reliability of ICs, especially for the CMOS IC products that inherently have high input impedance.
  • the ESD event can occur during the testing, handling, shipping and packaging of the IC products when undesired static charged particles with a high potential difference to the IC produce a large voltage spike to generate enough heat to cause permanent damages to the IC. Since most of the ESD events occur inside the IC and are not noticeable until damage has already occurred, it is a very difficult problem to deal with.
  • An ESD event typically ruptures the insulator under the gate of the input transistor of CMOS IC because the large voltage spike of the ESD event usually occurs at the gate of the input transistor. Since the insulator under the gate of a CMOS transistor is small and thin with very little capacitance, a high voltage spike can be generated with a small amount of static charge. Since the insulator is usually a poor thermal conductor that does not dissipate heat quickly, the gate structure of the CMOS IC is fragile and easily damaged. This problem is getting more severe as the physical size of CMOS IC is scaling down to improve the speed as well as the functionality of the IC.
  • CMOS IC devices The protection of the CMOS IC devices from the damages due to ESD event is one of the most challenging tasks for the IC design engineers [0078] Potentially, the most useful solution for protecting CMOS ICs from ESD damage is one that does not allow the external static charged particles to produce a potential difference between the gate of the input transistor and the rest of the input transistor of CMOS IC, thereby avoiding damage the insulator under the gates of the input transistors. Instead, any ESD energy should be directed to the more robust ground and/or substrate and/or power supply lines.
  • the common solution is to install a voltage clamping circuit at every input lead of CMOS IC as shown in Figure 5 to limit amplitude of the ESD voltage spike. Since the static charged oil and grease particles on the fingers of the operators are negative in charge, the negatively charged particles will produce a negative potential on the gate of the CMOS IC when the IC is touched. Assuming that the potential of the charged particles on the first operator in the factory is - Vl and the potential is a more negative -V2 on the second operator of an assembly line at the 30th floor of a skyscraper ten thousand miles away.
  • the potential at the gate, power supply, ground and substrate of the CMOS IC will all be -Vl after it is touched by the first operator. Since the static charged particles on the second operator have a higher negative potential, a negative voltage spike at the gate of the input transistor will quickly be formed when it is touched by the second operator. Before the input pin is touched by the second operator, although the input pin has already an electric potential of -Vl, the voltage on every pin of the whole IC is zero since the IC is not powered up.
  • the voltage on the input pin 106 becomes more negative and the ground clamping diode 104 becomes conductive so that the voltage at the substrate and/or ground 112 will follow the ESD voltage at the input pin 106 after the ESD voltage is below -Vf where Vf is the forward voltage of the diode 104.
  • Both the voltages at the input 106 and the ground and/or substrate 112 will continue to become more negative while the voltage at the power supply node Vdd 110 remains at the zero.
  • the rising of the voltage at the input pin 106 and ground and/or substrate 112 into the negative direction will be stopped finally when the voltage at the input pin 106 causes the Vdd clamping diode 102 going into breakdown.
  • the amplitude of ESD voltage spike occurring to the input pin 106 is thus limited to be within the difference of forward voltage and reverse breakdown voltage of the clamping diodes and an ESD voltage spike occurs between the gate 108 of the input transistor and the power supply line Vdd 110 of the CMOS IC when the potential of the static charged particles on the second operator is more negative.
  • the voltage difference between the input pin 106 and the power supply line Vdd 110 of the CMOS IC is assumed to be equal to the breakdown voltage of the Vdd clamping diode 102 after the breakdown has occurred; but actually the voltage at the input pin 106 will rise much faster than the voltage at power supply line Vdd 110 because the power supply line Vdd 110 is connected to many transistors and probably also to a large bypass capacitor.
  • the rise time of the voltage at the power supply line Vdd 110 is thus much longer than the rise time of voltage at the input pin 106 and a voltage spike with an amplitude exceeding the diode's breakdown voltage can be generated to produce excess heat to cause rupture on the insulator under the gate 107 of the input transistor.
  • the other problem is that it is a constant uphill battle to clamp the voltage at the input pin 106 as the size of the gate is shrinking since a smaller gate will produce a larger, faster voltage spike and require an even faster clamping circuit.
  • Vdd clamping diode 102 The purpose of Vdd clamping diode 102 is simply to prevent the voltage of logic high level input from exceeding the power supply voltage Vdd 110 plus the forward voltage of the diode and the purpose of ground clamping diode 104 is simply to prevent the voltage of logic low input level from falling more negative than the negative of the forward voltage of the diode.
  • the current ESD protection technology using two diodes is actually an accidental byproduct of an over- voltage protection circuit.
  • An improved strategy for ESD protection may be to connect all the input pins 106 of the CMOS IC to the ground and/or substrate 112 and to the power supply line 110 with protective short-circuit connections to ensure that there is no potential difference between all the input pins and the circuits inside the CMOS IC when the
  • CMOS IC is not powered up. As long as the input pins 106 always stay at the same potential as the ground and/or substrate 112 and the power supply line Vdd 110 of the CMOS IC, there will be no resistance to produce an ESD voltage between the gate 107 of the input transistor and the rest of input transistor of the CMOS IC to generate a voltage spike on the gate of the input transistor regardless of how many high potential charged particles are on the input pins 106 of the CMOS IC.
  • the voltage spike will release most of the energy to the robust metallic ground and/or substrate 112 and power supply line Vdd 110 of the CMOS IC, instead of totally to the fragile, poor thermal conductive insulator under the gate 108 of the input transistor.
  • the protective short-circuit connection between the input pin 106 and ground and/or substrate 112 and the power supply line Vdd 110 can survive the heat generated from the energy of ESD voltage spike, the CMOS IC is protected.
  • the protective short-circuit connection between the input pin 106 and the substrate and/or ground 112 and power supply line Vdd 110 can be designed to pass as much current as we want, the CMOS IC can survive an ESD event easily.
  • the resistance between the gate 107 of the input pin of the CMOS IC and the rest of the CMOS IC is now too low to produce the damaging voltage spike on the gate structure while the resistance on the ground and/or substrate and power supply line is now very high since the whole CMOS IC is floated. An ESD voltage spike is thus produced on the ground and/or substrate and the power supply line instead of on the gate of the input pin 107.
  • a novel ESD protection circuit 101 is illustrated in Figure 6 as the first preferred embodiment of the present invention. This design uses depletion type MOSFETs to try to ensure that the input pins 106 of the CMOS IC always stay at the same potential as the ground and/or substrate 112 and power supply line Vdd 110 of the
  • a P type depletion MOSFET 116 provides a short-circuit connection between the input pin 106 of the CMOS IC to the ground and/or substrate 112.
  • the drain of the P type depletion MOSFET 116 is connected to the input pin 106 and the gate 107 of the input transistor of the CMOS IC to be protected while the source of the P type depletion MOSFET 116 is connected to the ground and/or substrate 112 of the CMOS IC.
  • the input pin 106 of the CMOS IC is always at the same potential as the ground and/or substrate 112 of the CMOS IC when the CMOS IC is not powered up.
  • the gate of the P type depletion MOSFET 116 is connected to the power supply line Vdd 110, the junction between the gate and source of the P type depletion MOSFET 116 will be energized as soon as the CMOS IC is powered up.
  • the channel between the drain and the source of the P type depletion MOSFET 116 will be pinched off immediately when the CMOS IC is powered up and only a very small pinch-off current is allowed to pass through the channel of the P type depletion MOSFET 116 after the CMOS IC powered up.
  • An N type depletion MOSFET 114 may also used to provide a short- circuit connection between the input pin 106 and the power supply line Vdd 110 of the CMOS IC when the CMOS IC is not powered up.
  • MOSFET 114 is connected to the power supply line Vdd 110 while the drain of the N type depletion MOSFET 114 is connected to the input pin 106 and the gate of the input transistor 107 of the CMOS IC to be protected. Since the gate of N type depletion MOSFET 114 is connected to the ground and/or substrate 112 and the source of the N type depletion MOSFET 114 is connected to the power supply Vdd line 110, the channel between the drain and the source of the N type depletion MOSFET 114 is a short-circuit connection when the source of the N type depletion MOSFET 114 is not powered up.
  • the potential of the input pin 106 of the CMOS IC is equal to the potential at both the ground and/or substrate 112 and the power supply line Vdd 110 of the CMOS IC when the CMOS IC is not powered up so that there is no potential difference between the gate 107 of the input transistor and the rest of the input transistor of the CMOS IC when the CMOS IC is not powered up and the static charged particles will never produce a voltage spike on the gate 107 of the input transistor of the CMOS IC during an ESD event.
  • the junction between the gate and source of the N type depletion MOSFET 114 is energized and the channel of N type depletion MOSFET 114 is pinched off almost immediately and only a small pinch-off current passes through the N type depletion MOSFET 114 when the CMOS IC is powered up. If the pinch off current of the N type depletion MOSFET 114 is approximately equal to the pinch off current of the P type depletion MOSFET 116, then the protective short-circuit connection 101 will become open and invisible to the CMOS IC when the CMOS IC is powered up.
  • Both the N type 114 and P type 116 depletion MOS may be fabricated with the rest of regular enhancement transistors in the CMOS IC.
  • the depletion MOSFETs may be fabricated without the first poly layer which is normally used to define the length of the channel for the enhancement type transistor. Instead, the whole channel between the drain and the source of the depletion MOSFET may be preserved and a different poly layer added later for the gate of the depletion type MOSFET.
  • the channel between the drain and the source of a depletion type MOSFET is built without the first poly layer, the channel between the drain and the source of a depletion type MOSFET is full of majority current carriers and is always a short-circuit connection electrically when the junction between the gate and source of the depletion type MOSFET is not energized. Since the whole purpose of the depletion type MOSFET is to produce a low impedance current path from the input pins 106 of the CMOS IC to the ground and/or substrate 112 and to the power supply line Vdd 110 of the CMOS IC, the only requirements for the depletion type OSFETs are to safely pass a lot of current and matched.
  • the same protective short-circuit connection 101 may also be used for every output pins of the CMOS IC as well. Since the output pins of the CMOS IC are always connected to either the drain or source of the MOSFETs and they are always much strongly built than the delicate gate structure of the MOSFET, the protective short- circuit connections circuit 101 for the output pins can be smaller physically. [0089] Since the substrate of a CMOS IC should connect to the lowest potential of the whole IC which is usually the ground network, the ground and substrate are usually connected together electrically. It is quite straight-forward to implement the protective short-circuit connection network 101 with a CMOS IC when the ground and substrate of the CMOS IC are connected together.
  • the substrate can be connected to a negative potential instead of ground in some applications, we will need to determine which pin for the protective short-circuit connection network 101 to connect to.
  • the short-circuit protection circuit 101 should connect the input pin 106 and power supply line 110 to the substrate instead of the ground network because the substrate is always larger than the ground network physically to dissipate more heat.
  • substrate is made of semiconductor material which does not dissipate heat as quickly as the ground network which is usually metallic, a smaller ground network might actually dissipate the heat more effectively than the larger substrate. In this case, the ground network becomes the better choice for the protective short-circuit connection network 101 to connect the input 106 and power supply line 110 to.
  • the protective short-circuit connection network 101 should connect the input pin 106 and the power supply line 110 to whichever of the ground pin or substrate pin that can dissipate the heat generated from the ESD voltage spike more effectively or to both pins.
  • the electrostatic discharge protection circuit includes an N type depletion MOSFET transistor; a P type depletion
  • MOSFET transistor a ground terminal coupled to a source terminal of said P type depletion MOSFET transistor and to both a gate terminal and a substrate terminal of said N type depletion MOSFET transistor; a positive power terminal coupled to a source terminal of said N type depletion MOSFET transistor and to both a gate terminal and a substrate terminal of said P type depletion MOSFET transistor; an input terminal coupled to a drain terminal of both said N type depletion MOSFET transistor and said P type depletion MOSFET transistor; and an output terminal coupled to said input terminal, thereby providing electrostatic discharge protection circuit.
  • a relatively simple logic circuit that uses the depletion type MOSFET is a non-inverting buffer 100 as shown in Figure 7.
  • the non-inverting buffer 100 is made of an N depletion type MOSFET 114 and a P depletion type MOSFET 116.
  • the gates of both MOSFETs are connected together as the input pin 106 and the drain of both MOSFETs are connected together as the output pin 108.
  • the drain of the P depletion type MOSFET 116 will be shorted to ground and/or substrate 112 when the gate-to- source junction of the P depletion type MOSFET 116 is not energized and the input pin 106 is at low logic level of 0 volt.
  • the N depletion type MOSFET 114 since a low logic level at the input pin 106 will energize the gate-to- source junction, the channel between drain and source of the N depletion type MOSFET 114 will be pinched off and remain in the high impedance state. As a result, the output of the buffer 108 will remain at logic low when the input pin 106 is at logic low.
  • the non-inverting buffer of Figure 7 includes an N type depletion MOSFET transistor and a P type depletion MOSFET transistor.
  • the N type depletion MOSFET transistor has a source terminal coupled to a positive voltage supply terminal, a substrate terminal coupled to a ground terminal, a gate terminal coupled to an input terminal, and a drain terminal coupled to an output terminal.
  • the P type depletion MOSFET transistor has a source terminal couple to the ground terminal, a substrate terminal coupled to the positive voltage supply terminal, a gate terminal coupled to the input terminal and a drain terminal coupled to an output terminal, thereby forming a two transistor, non-inverting buffer.
  • the current consumption of the non-inverting buffer 100 built with depletion type MOSFETs can be very low since the current consumed by the non- inverting buffer 100 is equal to the pinch-off current of the devices which is contributed by the majority current carrier in the drain-to-source channel and can be controlled to be within a minimum level.
  • the pinch-off current is very different to the leakage current flowing through the substrate.
  • the leakage current is contributed by minority current carrier in both the substrate and drain region of the transistor.
  • the amount of leakage current is usually small, it is very difficult to control the amount of leakage current precisely and the amount of leakage current can vary over a large range among devices.
  • Another problem of the leakage current is that it has a long thermal time constant since the leakage current is generated by the thermal nature of the devices. In contrast, the pinch-off current can be controlled precisely to be as low as the leakage current.
  • the non-inverting buffer 100 can be made into a non-inverting latch circuit 120 easily as shown in Figure 8 by shorting the input pin 106 and output pin 108 together.
  • the non-inverting latch 120 thus becomes a memory cell. Since the state of the output pin 108 and the state of the input pin 106 are always in the same phase, shorting the input pin 106 together with the output pin 108 will provide a positive feedback for the non-inverting latch 120 to lock the state of the output pin 108.
  • the state of the output pin 108 of the non-inverting latch 120 will remain at the current state forever; the high logic output state will be retained by the N type depletion MOSFET 114 and the low logic output state will be retained by the P type depletion MOSFET 116 as long as the power supply is active even if the input signal 106 is removed afterward.
  • the non-inverting latch 120 can thus be used as a memory cell for 3T-
  • SRAM 126 (3-transistor Static Random Access Memory) as shown in figure 9 as the second preferred embodiment.
  • a data switch transistor 128 controlled by the word-line 124 can read or write the data on the bit- line 122 from or into the memory cell 120.
  • the data switch transistor 128 can be built with a regular enhancement type MOSFET as shown in the figure 9 or any other switching device.
  • the word-line 124 signal is the enable signal to control the data switch transistor 128 and the signal on the bit-line 122 is the I/O data.
  • a 3T-SRAM cell 126 can thus be built with only two depletion type MOSFETs as the memory cell 120 and a data switching transistor 128 and the data in the 3T-SRAM cell 126 can be accessed with only a single data I/O bit-line 122 and a single enabling word-line 124.
  • the new 3T-SRAM cell 126 is far superior to the traditional 6T-SRAM since it uses only half of the hardware.
  • the new 3T-SRAM cell 126 is actually more similar to the DRAM cell which is made of a transistor and a capacitor.
  • the 3T-SRAM includes an N type depletion
  • the N type depletion MOSFET transistor has a source terminal coupled to a positive voltage supply terminal and a substrate terminal coupled to a ground terminal.
  • the P type depletion MOSFET transistor has a source terminal couple to the ground terminal and a substrate terminal coupled to the positive voltage supply terminal.
  • the gate terminal of the N type depletion MOSFET transistor is coupled to the drain terminal of the N type depletion MOSFET transistor, to the gate terminal of said P type depletion MOSFET transistor and to the drain terminal of the P type depletion MOSFET transistor.
  • N type enhancement MOSFET transistor having a drain terminal coupled to the gate terminal of the N type depletion MOSFET transistor, a substrate terminal coupled to the ground terminal, a source terminal coupled to a data line and a gate terminal coupled to an address line, thereby forming a three-transistor static random access memory.
  • SRAM and DRAM belongs to the volatile memory cells because they can not retain the memory if the power supply is removed.
  • a non- volatile memory cell can retain the data for a very long period of time without power supply. Since the non-volatile memory cells are built by completely different technologies to the volatile memory cells, they will not be discussed further in this patent disclosure.
  • Traditionally there are two kinds of volatile memory cell, the SRAM and
  • a traditional SRAM memory cell uses four enhancement type MOSFET transistors to latch the data and needs two more MOSFET transistors as the data I/O switch. It requires four enhancement type MOSFET to latch a data bit because it is impossible to build a non-inverting latch with only two enhancement type MOSFET transistors due to the nature of negative logic.
  • two inverters that each is made of two enhancement type MOSFET transistors are needed to produce a positive feedback and a total of four enhancement type MOSFET transistors is thus needed to latch a data bit. Since two of the four enhancement type MOSFETs in the latch are constantly on and the other two are constantly off, the current consumption of the 6T-SRAM cell is high.
  • 6T-SRAM cell Despite of the disadvantages of size and current consumption, since the data of 6T-SRAM cell can be accessed quickly and the data will be kept indefinitely without any maintenance as long as the power supply is active, 6T-SRAM cell is very easy to use and is still popular in the applications such as desktop computers or games that require moving lots of data quickly. However, as the CMOS IC is scaled down in size, it becomes harder to produce 6T-
  • 6T-SRAM The problem of 6T-SRAM is due to the fact that two inverters are needed to produce a positive feedback to latch the data. If the two inverters are not matched perfectly, one of the inverters will slew faster than the other when the data content is changed. The difference of the rate of slewing between the inverters will reduce the noise margin since a smaller noise can cause the 6T-SRAM to trap in the illegal state and become unstable. Since the leakage current becomes larger while the operating current of the inverter becomes smaller as the CMOS IC is scaled down, the noise margin of 6T- SRAM deteriorates quickly when the CMOS IC is scaled down.
  • the new 3T-SRAM cell 126 is an improvement on the traditional 6T-
  • the 3T-SRAM cell 126 consumes less current and occupies less room and may be shrunk easily because it is inherently stable.
  • the noise margin of the 3T-SRAM is the same as all other circuits so that as long as the operating current of the 3T-SRAM is much larger than the leakage current, the data content of the memory cell is stable.
  • 3T-SRAM is actually more similar to the memory cell of DRAM than to the traditional 6T-SRAM.
  • the DRAM memory cell is very small and consumes very little current.
  • the DRAM memory cell is normally made of a MOSFET transistor as the data switch and a capacitor to store the data. It is the simplest structure of memory cell of any kind until now and occupies the least room and consumes the least amount of current. However, since there is a constant leakage current through the substrate of the IC, the capacitor will lose the stored high logic level data over time. As a result, a DRAM memory cell needs to be refreshed to maintain the data constantly. The requirement of refreshing complicates the operation of DRAM and lengthens the access time for the
  • DRAM cell Since the DRAM cells can be packed densely, they are very popular for applications such as camera that needs to store a large number of pixels.
  • the other advantage of the DRAM cell is that it consumes very little current. The only current consumed by the DRAM cell is through the leakage current of the capacitor.
  • the power saving feature of DRAM cell makes it very popular among the portable applications such as cell phone. [00101] Since the DRAM offers much more advantages over SRAM, the DRAM has dominated the memory products, especially in the portable applications. In order to ease the use of DRAM, numerous technologies were invented during the past twenty years to ease the refreshing of DRAM cells and to make the DRAM to behave like the SRAM; for example, to hide the refreshing from the application either by using additional hardware or software.
  • the new 3T-SRAM cell 126 is a static RAM cell, it does not require maintenance so that it is very easy to use just like a regular 6T-SRAM cell. Since the 3T- SRAM cell 126 can use two depletion type MOSFETs to replace a capacitor and the size of the two depletion type MOSFETs can be very small because the drain-to-source channel must be very narrow to be easily pinched off completely.
  • the 3T-SRAM 126 Since the two depletion type MOSFETs of the 3T-SRAM cell 126 can be manufactured along with all other regular enhancement type MOSFET without requiring any special process, the 3T-SRAM 126 can be built much easier than DRAM which is notorious for its complicated process to produce capacitors. Since the level of the output signal from the 3T-SRAM 126 memory cell is always equal to the voltage of the power supply rails, the 3T-SRAM memory cell 126 produces an output signal with a large voltage swing.
  • the 3T-SRAM cell 126 consumes as little power as the DRAM, can be packed almost as densely as the DRAM, can access the stored data quickly without timing restrain, can produce a large output signal and can be manufactured at almost half of the labor of DRAM; it has all the benefits of both SRAM and DRAM but without their difficulties. It is simply the most desirable volatile memory cell. AND LOGIC GATE
  • a positive AND logic gate 132 can be built with two N depletion type
  • MOSFETs 114 and two P depletion type 116 MOSFETs as shown in Figure 10.
  • the two N depletion type MOSFETs 114 are connected in series and the two P depletion type MOSFETs 116 are connected in parallel so that the output 108 will be shorted to ground at low logic level when either one of the input A 129 or input B 130 is at a low logic level.
  • the output 108 can only become high logic level when both of the input A 129 and input B 130 are at a high logic level to short the output 108 to Vdd 110.
  • a positive AND logic 132 is thus achieved.
  • the positive AND logic gate includes a first and second N type depletion MOSFET transistor, and a first and second P type depletion MOSFET transistor.
  • a first input terminal is coupled to a gate terminal of the first P type depletion MOSFET transistor and to a gate terminal of the second N type depletion MOSFET transistor.
  • a second input terminal is coupled to a gate terminal of the first N type depletion MOSFET transistor and to a gate terminal of the second P type depletion MOSFET transistor.
  • a positive voltage supply terminal is coupled to a source terminal of said first N type depletion MOSFET transistor and to a substrate terminal of both the first and second P type depletion MOSFET transistors.
  • a ground terminal is coupled to a source terminal of both the first and second P type depletion MOSFET transistors, and to a substrate terminal of both the first and second N type depletion MOSFET transistors.
  • An output terminal is coupled to a drain terminal of both the first and second P type depletion MOSFET transistors and to a drain terminal of the second N type depletion MOSFET transistor, thereby creating an AND Boolean logic circuit.
  • a positive OR logic gate 134 can be built with two N depletion type
  • the positive OR logic gate includes a first and second N type depletion MOSFET transistor, and a first and second P type depletion
  • a first input terminal is coupled to a gate terminal of the first P type depletion MOSFET transistor and to a gate terminal of the second N type depletion MOSFET transistor.
  • a second input terminal is coupled to a gate terminal of the first N type depletion MOSFET transistor and to a gate terminal of the second P type depletion MOSFET transistor.
  • a positive voltage supply terminal is coupled to a source terminal of both the first and second N type depletion MOSFET transistors and to a substrate terminal of both the first and second P type depletion MOSFET transistors.
  • a ground terminal is coupled to a source terminal of the second P type depletion MOSFET transistor, and to a substrate terminal of both the first and second N type depletion MOSFET transistors.
  • An output terminal is coupled to a drain terminal of the first P type depletion MOSFET transistor and to a drain terminal of both the first and second N type depletion MOSFET transistor, thereby creating an OR Boolean logic circuit.
  • a basic master-slave flop-flop 158 is made of two sections, a master section 166 and a slave section 168 as shown in Figure 12. Both the master section 166 and the slave 168 section are made of a data switch and a buffer/latch circuit. Both the master section 166 and the slave section 168 toggle between the buffer mode to accept the data and latch mode to deliver the data alternatively out-of- phase so that when the master section 166 is in the buffer mode, the slave section 168 will be in the latch mode and vice versa.
  • Each of the master section 166 or the slave section 168 alone can also be used as a clocked latch by itself.
  • the master section 166 When the clock input is in the logic high level, the master section 166 will be in the buffer mode and the data input 138 is allowed to be passed to the non-inverting buffer/latch 150 through the input switch 160. During this period, the feedback path of the input buffer/latch 150 is opened so that the input buffer/latch 150 is in the buffer mode. As soon as the clock input changes the state to become logic low level, the input switch 160 will be opened and the feedback path of the input buffer/latch 150 will be closed and the input buffer/latch 150 will be switched to the latch mode and the data input 138 is latched.
  • the output switch 162 will be closed to allow the latched input data to be passed to the output 140 through the output buffer/latch 152 which is currently in the buffer mode since its feedback path is opened. But as soon as the clock input changes the state to become logic high level again, the output switch 162 becomes opened and the feedback path of the output buffer/latch 152 will be closed and the output buffer/latch 152 will stay in the latch mode to maintain the same data to the output 140. As a result, the data input 138 is sampled when the clock is at high logic level and is delivered to the output 140 when the clock is at low logic level and the negative falling edge of the clock signal effectively triggers the sampling of input data 138. [00110] Traditionally when the master-slave flip-flop is built with the enhancement type MOSFET, two inverters that each is made of two enhancement
  • MOSFETs are needed to form the buffer/latch circuit due to the lack of positive logic output as explained earlier in the 3T-SRAM section.
  • the use of two inverters to form a non-inverting buffer/latch in a master- slave flip-flop does not only take more room but also add more propagation delay to the output signal, require longer setup time before the trigger and longer hold time after the trigger to ensure the data integrity and consume more power.
  • the positive non-inverting buffer 100 is thus ideal to be used for the buffer/latch of the master-slave flip-flop 158.
  • a T-gate 136 is made of two enhancement type MOSFET transistors as shown in Figure 13.
  • a T-gate 136 has two complementary control inputs and two I/O pins, an input 146 and an output 148. Since the I/O pins of T-gate 136 are not polarized, the input 146 and output 148 are bidirectional. The purpose of the T-gate 136 is to allow the passage of data from the input 146 to the output 148 of the T-gate 136 when the T-gate 136 is enabled and to disrupt the passage of data when the T-gate 136 is disabled.
  • the T-gate 136 will be enabled only when the N input of the T-gate 136 is at high logic level while the P input is at a low logic level at the same time.
  • a high level logic input will be passed from the input 146 to the output 148 of the T-gate 136 through the P type enhancement MOSFET 144 and a low level logic input will be passed from the input 146 to the output 148 of the T-gate 136 through the N type enhancement MOSFET 142.
  • the N input of the T-gate 136 must be at a logic low level while the P input of the T-gate 136 must be at a logic high level at the same time.
  • the T-gate 136 When the T- gate 136 is disabled, there is no passage between the input 146 and output 148 of the T- gate 136. As a result, the T-gate 136 is simply a single-pole- single-throw switch. [00112] Mixing the use of depletion type and enhancement type MOSFET produces a basic master-slave flip-flop 158 built with the least possible amount of hardware.
  • the mixed master-slave flip-flop 158 is superior to the traditional master-slave flip-flop built with only the enhancement type MOSFET because the mixed master-slave flip-flop 158 requires half of the setup time and hold time so that it can toggle the output signal at twice the rate.
  • the basic master-slave flip-flop 158 is thus the best example to show why the depletion type MOSFET is important to achieve an optimal logic design.
  • Addition Set 156 or /Reset 154 input can be added to the basic master- slave flip-flop as shown in Figure 14 and 15.
  • the non-inverting buffer 100 will need to be replaced by either the non-inverting AND 132 or non-inverting OR 134 to allow for the additional set 156 or /reset 154 input pins.
  • the non-inverting buffer 100 can also be built by two other ways as shown in Figure 16 and 17 by using a resistor 190 to replace one of the MOSFETs.
  • the P type depletion MOSFET 116 when the input 106 is at logic high, the P type depletion MOSFET 116 will be pinched-off and remain in the high impedance state and the output voltage at output pin 108 will be pulled to the Vdd 110 by the loading resistor 190 and the only current consumed is the pinch-off current through the P type depletion MOSFET
  • the depletion MOSFET transistor is an N type transistor having a gate terminal coupled to an input terminal, a drain terminal coupled to an output terminal, a substrate terminal coupled to a ground terminal and a source terminal coupled to a positive voltage supply terminal.
  • resistor having a first terminal coupled to the drain terminal of the N type depletion MOSFET transistor, and a second terminal coupled to the ground terminal, thereby forming a one-transistor, one -resistor, non- inverting buffer.
  • the non-inverting latch 120 can also be built with a depletion type MOSFET and a resistor 190 as shown in Figure 18 and 19.
  • the disadvantage of using a resistor 190 is that it can take a large room to build a large resistor 190 since a small resistor will consume more current and should be avoided.
  • the only advantage of using a resistor 190 to replace the depletion type MOSFET is to save the N-well or P-well. An N-well or a P-well is inevitable when both N type and P type MOSFETs are used and an N-well or a P-well can occupy a large room. Using a resistor and only one kind of MOSFET without a well might increase the density of memory cell.
  • the resistor 190 can be made in many different ways, for example, by using a poly resistor or a well resistor or a transistor as an active load.
  • the SRAM memory cell can thus be called 2T1R-SRAM 127 when one of the MOSFETs of the memory cell 120 is replaced with a resistor as shown in Figure 20 and 21.
  • N type depletion MOSFET transistor having a substrate terminal coupled to a ground terminal and a source terminal coupled to a positive voltage supply terminal and a resistor having a first terminal coupled to the drain terminal of the N type depletion MOSFET transistor, and a second terminal coupled to the ground terminal.
  • the gate terminal of the N type depletion MOSFET transistor is coupled to its drain terminal.
  • N type enhancement MOSFET transistor having a drain terminal coupled to the gate terminal of the N type depletion MOSFET transistor, a substrate terminal coupled to the ground terminal, a source terminal coupled to a data line and a gate terminal coupled to an address line, thereby forming a two-transistor, 1 resistor, static random access memory.
  • a P-type depletion MOSFET transistor having a substrate terminal coupled to a positive voltage supply terminal and a source terminal coupled to a ground terminal.
  • resistor having a first terminal coupled to the drain terminal of the P type depletion MOSFET transistor, and a second terminal coupled to the positive voltage supply terminal.
  • the gate terminal of the P type depletion MOSFET transistor is coupled to its drain terminal.
  • an N type enhancement MOSFET transistor having one of a source/drain terminal coupled to the gate terminal of the P type depletion MOSFET transistor, a substrate terminal coupled to the ground terminal, the other of the source/drain terminal coupled to a data line and a gate terminal coupled to an address line, thereby forming a two-transistor, one resistor static random access memory.
  • the resistor 190 can also be replaced by a reverse-biased diode which is equivalent to a resistor with very high impedance.
  • the reverse-biased diode can be made in many ways inside the IC since it is simply a reverse-biased P-N junction.
  • Figure 22 illustrates some of the possible ways to produce a reverse-biased diode using the P-type depletion MOSFET 116 and Figure 23 illustrates some of the possible ways to produce a reverse-biased diode using N-type depletion MOSFET 114.
  • the leakage current flows in from the bulk to the drain-to-source channel of the reverse-biased diode or flows out from the drain-to- source channel of the reverse-biased diode to the bulk must be much larger than the pinch-off current of the memory cell transistor to prevent the pinch-off current of the memory cell transistor from altering the state of the stored data.
  • the pinch-off current through the memory cell transistor 116 and the leakage current to the low logic input state at the bit-line 122 through the data switch transistor 128 can discharge voltage stored on the stray capacitance, the logic high output at output pin 108 can be altered.
  • the voltage on the stray capacitance at the output pin 108 will not be discharged by the pinch-off current of the memory cell transistor 116 and the leakage current to the logic low input state at the bit- line 122 through the data switch transistor 128 and the logic high output state at output pin 108 will be retained indefinitely as long as the power supply line is active.
  • the reverse-biased diode Since the drain of the reverse-biased diode is the same as the drain of the memory cell transistor, the reverse-biased diode can be eliminated. As a result, the loading resistor 190 of the non-inverting buffer 100 as shown in Figure 16 and 17 can even be eliminated completely as shown in Figure 24 and 25 if the leakage current from the bulk to the drain of the memory cell transistor 116 or from drain of the memory cell
  • the non-inverting latch 120 using only a single depletion MOSFET can be shown in Figure 26 and 27 and 2T-SRAM memory cell 131 can be shown as in Figure 28 and 29.
  • the pinch-off current through the drain-to-source channel of the memory cell transistor 114 and the leakage current from the logic high input state at bit- line 122 through the data switch transistor 128 can charge up the voltage at the output pin 108; whereas, as long as the leakage current from the drain of the memory cell transistor 114 to the bulk is larger than the sum of the pinch-off current through the memory cell transistor 114 and the leakage current from the logic high input state at bit-line 122 through the data switch transistor 128, the logic low output state can still be retained by the stray capacitance at the output pin 108.
  • the pinch-off current through the drain-to-source channel of the memory cell transistor 114 and the leakage current from the logic high input state at bit- line 122 through the data switch transistor 128 can charge up the voltage at the output pin 108; whereas, as long as the leakage current from the drain of the memory cell transistor 114 to the bulk is larger than the sum of the pinch-off current through the memory cell transistor 114 and the leakage current from the logic high input
  • the memory cell transistor 116 will retain the logic low output state at output pin 108 indefinitely while the logic high output state is retained by the stray capacitance at the output pin 108.
  • the pinch-off current through the drain-to- source channel of the memory cell transistor 116 and the leakage current to the logic low input state at bit-line 122 through the data switch transistor 128 can discharge the voltage at the output pin 108; whereas, as long as the leakage current from the bulk to the drain of the memory cell transistor 116 is larger than the sum of the pinch-off current through the memory cell transistor 116 and the leakage current to the logic low input state at bit-line 122 through the data switch transistor 128, the logic high output state can still be retained by the stray capacitance at the output pin 108 indefinitely as long as the power supply is active.
  • the 2T-SRAM memory cells 131 as shown in Figure 28 and 29 are thus the simplest possible static memory cell. Since these two designs of 2T-SRAM memory cell 131 depend upon the leakage current which is very difficult to control precisely to retain one of the two output states, the yield of the 2T-SRAM memory cell 131 might be lower than the yield of 3T-SRAM 126. The leakage current, unfortunately, will also increase the power consumption of the 2T-SRAM memory cells 131. Since the 2T- SRAM memory cell 131 can be built without a well and with less hardware, the 2T- SRAM memory cell 131 can be built with a much higher density than 3T-SRAM memory cell 126. The advantage of higher density from 2T-SRAM memory cell 131 might weigh more than its lower yield and higher power consumption.
  • the leakage current to the substrate prevents the memory cell from retaining the logic high output state for a long period of time and it is very critical to reduce the amount of leakage current to the substrate.
  • the leakage current to the substrate is a culprit to the defect of DRAM memory cell.
  • the leakage current to or from the substrate will retain one of the two output states of memory cell and should be controlled to be within a certain level if possible.
  • the leakage current to or from the substrate becomes a friendly helper.
  • the leakage current to or from the substrate is irrelevant since the output state will be retained only by the memory cell transistors. The new design of SRAM cells thus completely solves the leakage current problem of the DRAM cell.
  • a depletion MOSFET transistor having a gate terminal coupled to a drain terminal, the substrate terminal coupled to a ground terminal or a positive voltage terminal and a source terminal coupled to a positive supply voltage terminal, or a ground terminal if the substrate terminal is coupled to the positive supply voltage terminal.
  • an N type enhancement MOSFET transistor having one of a source/drain terminal coupled to the gate terminal of the depletion MOSFET transistor, a substrate terminal coupled to the ground terminal, the other of the source/drain terminal coupled to a data line and a gate terminal coupled to an address line, thereby forming a two-transistor static, random access memory (2T-SRAM).
  • the depletion MOSFET transistor may be an N type transistor having the substrate terminal coupled to the ground terminal and the source terminal coupled to the positive supply voltage terminal, thereby forming a two-transistor static random access memory cell.
  • the depletion MOSFET transistor may be a P type transistor having the substrate terminal coupled to the positive supply voltage terminal and the source terminal coupled to the ground terminal thereby forming a two-transistor static random access memory cell.
  • the Philips MOSFET model 11020 uses potential to describe the transistor so that the only difference between enhancement and depletion device is the voltage at the gate (VBF in the SPICE model file).
  • the boundary of the depletion mode of a depletion device is for VGS to be within 0 to -Vdd for the N type depletion MOSFET as shown in the figure 1.
  • the Vdd 110 is set to 2.2V and the resistor R is set to lOKohm and the VBF value of the transistor is -2.5V and the voltage across the resistor indicates the amount of IDSS 103 since the voltage across the gate and source is zero volt to the SPICE program.
  • the output voltage is found to be 719mV so that IDSS is found to be equal to 71.9uA.
  • the resistance of the load resistor is changed to 10 11 ohm and the VBF is changed to - 0.5V.
  • the operating point of the transistor now is at pinch-off with very little current flowing through the resistor so that a high value resistance is needed to read the current.
  • the voltage at the output is found to be equal to 20OmV so that the current through the resistor is 2pA and indeed, the transistor is pinched-off.
  • the switch transistor 128 is then added and the test circuit #2 as shown in Figure 33 can test the unlatched operation of the 2T-SRAM.
  • a +3.3V is used as the bit-line input 122 to produce the maximum leakage current through the switch transistor 128.
  • a digital signal with peak logic high of 3.3V is used as the word-line signal 124 to enable the switch 128.
  • the switch 128 is enabled for only a short period at the beginning of the simulation to show the operation of the switch 128. After that, the switch 128 is disabled for the rest of the testing while the output voltage 108 is monitored. The output voltage 108 is found to be equal to
  • the output voltage 108 of the unlatched mode of the 2T-SRAM memory cell is basically equal to the sum of the voltage inputs from the bit-line input 122 and the power supply Vdd 110 of the memory cell.
  • both the memory cell 114 and the switch 128 are at high impedance state and become high impedance resistors.
  • Each of the two voltage sources are divided down by the transistors and added up to become the output voltage 108.
  • the voltage source is Vdd 110 and the resistor divider is made of the pinch-off current through D-S channel of the depletion MOSFET 114 and the leakage current from the Drain to the substrate; for the switch transistor 128, the voltage source is the voltage at bit-line input 122 and the resistor divider is also made of the leakage current through the D-S channel of the switch transistor 128 and the leakage current from the Drain to the substrate. Since the ratio of these two currents is determined by the transistor and is constant when the ambient temperature is fixed, the output voltage will remain constant and stable and will not run away. Even if the temperature rises, since the leakage current will become larger when the temperature rise, the larger leakage current will ensure that the output voltage remain stable.
  • the output voltage can vary over a large range due to the spread of leakage current.
  • a larger leakage current is actually very desirable to stabilize the output voltage 118 since it will produce less output voltage during the unlatched mode. This is a drastic departure from all the current DRAM technologies.
  • the same leakage current that caused problem for the DRAM is now needed to maintain a stable desired output state.
  • a mixed AND gate 202 to produce the logic of (/A)B can be shown as in
  • Figure 30 by replacing the depletion type MOSFET with enhancement type MOSFET for one of the input signals in the original AND logic circuit 132 as shown in Figure 10.
  • the A input 129 is connected to the gates of both the
  • N type and P type enhancement MOSFETs and the B input 130 is connected to the gates of both N type and P type depletion MOSFETs. Since the enhancement device and depletion device are opposite in the logic output, the N type depletion MOSFET 114 must be connected in series with the P type enhancement MOSFET 144 and the P type depletion MOSFET 116 must be connected in parallel with the N type enhancement MOSFET 142 to produce an AND logic. As a result, a mixed AND is produced from inverted A and normal B so that the output 108 becomes logic low when either the B input 130 is at logic low and the P depletion type MOSFET 116 is not energized or when the A input 129 is at logic high and the N enhancement type MOSFET 142 is energized. The output 108 can only become logic high when both the B input 130 is at logic high and the N type depletion MOSFET 114 is not energized and when A input 129 is at logic low and the P type enhancement MOSFET 144 is energized.
  • a first input terminal is coupled to a gate terminal of the P type enhancement MOSFET transistor and to a gate terminal of the N type enhancement MOSFET transistor.
  • a second input terminal is coupled to a gate terminal of the N type depletion MOSFET transistor and to a gate terminal of the P type depletion MOSFET transistor.
  • a positive voltage supply terminal is coupled to a source terminal of the N type depletion MOSFET transistor and to a substrate terminal of both the P type enhancement MOSFET transistor and the P type depletion MOSFET transistor.
  • a ground terminal is coupled to a source terminal of both the P type depletion MOSFET transistor and the N type enhancement MOSFET transistor, and to a substrate terminal of both the N type enhancement MOSFET transistor and the N type depletion MOSFET transistor.
  • An output terminal is coupled to a drain terminal of the P type depletion MOSFET transistor, the P type enhancement MOSFET transistor and the N type enhancement MOSFET transistor, thereby creating an mixed AND Boolean logic circuit [00137]
  • a mixed OR gate 204 to produce the logic of (/A)+B can be shown as in Figure 31 by replacing the depletion type MOSFET with enhancement type
  • the A input 129 is connected to the gates of both the N type and P type enhancement MOSFETs and the B input 130 is connected to the gates of both N type and P type depletion MOSFETs. Since the enhancement device and depletion device are opposite in the logic output, the N type depletion
  • MOSFET 114 must be connected in parallel with the P type enhancement MOSFET 144 and the P type depletion MOSFET 116 must be connected in series with the N type enhancement MOSFET 142 to produce an OR logic.
  • a mixed OR logic is produced from inverted A or normal B so that the output 108 becomes logic high when either the B input 130 is at logic high and the N depletion type MOSFET 114 is not energized or when the A input 129 is at logic low and the P enhancement type MOSFET
  • the output 108 can only become logic low when both the B input 130 is at logic low and the P type depletion MOSFET 116 is not energized and when A input 129 is at logic high and the N type enhancement MOSFET 142 is energized.
  • CMOS IC products can now be handled easily without any physical restriction to the personnel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne des circuits de logique positive, des systèmes et des procédés utilisant des MOSFET fonctionnant dans un mode d'appauvrissement, notamment des circuits de protection contre la décharge électrostatique (ESD), des verrous et des tampons non inverseurs, ainsi que des cellules de mémoire vive statique présentant de un à trois transistors. Lesdits nouveaux circuits s'ajoutent à la technologie MOSFET à mode d'enrichissement et sont également conçus pour améliorer la fiabilité des produits de circuits intégrés (CI) à semi-conducteur à oxyde de métal complémentaire (CMOS).
EP08728213A 2007-01-24 2008-01-24 Circuit mosfet a mode d'appauvrissement et applications Withdrawn EP2109890A4 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP10172462A EP2287909A2 (fr) 2007-01-24 2008-01-24 Circuit MOSFET à mode d'appauvrissement et application associée
EP10172459A EP2287908A2 (fr) 2007-01-24 2008-01-24 Circuit MOSFET d'appauvrissement et application associée

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88636307P 2007-01-24 2007-01-24
PCT/US2008/051913 WO2008092004A2 (fr) 2007-01-24 2008-01-24 Circuit mosfet à mode d'appauvrissement et applications

Publications (2)

Publication Number Publication Date
EP2109890A2 true EP2109890A2 (fr) 2009-10-21
EP2109890A4 EP2109890A4 (fr) 2010-02-10

Family

ID=39645162

Family Applications (3)

Application Number Title Priority Date Filing Date
EP08728213A Withdrawn EP2109890A4 (fr) 2007-01-24 2008-01-24 Circuit mosfet a mode d'appauvrissement et applications
EP10172462A Withdrawn EP2287909A2 (fr) 2007-01-24 2008-01-24 Circuit MOSFET à mode d'appauvrissement et application associée
EP10172459A Withdrawn EP2287908A2 (fr) 2007-01-24 2008-01-24 Circuit MOSFET d'appauvrissement et application associée

Family Applications After (2)

Application Number Title Priority Date Filing Date
EP10172462A Withdrawn EP2287909A2 (fr) 2007-01-24 2008-01-24 Circuit MOSFET à mode d'appauvrissement et application associée
EP10172459A Withdrawn EP2287908A2 (fr) 2007-01-24 2008-01-24 Circuit MOSFET d'appauvrissement et application associée

Country Status (4)

Country Link
EP (3) EP2109890A4 (fr)
JP (1) JP2010517204A (fr)
CN (1) CN101632176A (fr)
WO (1) WO2008092004A2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9328931B2 (en) 2011-02-11 2016-05-03 Esg Pool Ventilation Ltd Heating and/or cooling system for maintaining an environment at a desired temperature

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5577082B2 (ja) * 2009-12-08 2014-08-20 ルネサスエレクトロニクス株式会社 半導体装置
TWI386109B (zh) * 2009-12-17 2013-02-11 Askey Computer Corp 產線之靜電防護方法及裝置
CN101807905B (zh) * 2010-02-11 2012-05-23 西安捷威半导体有限公司 一种耗尽型半导体开关器件的驱动电路及其驱动方法
CN102651366B (zh) * 2012-01-12 2013-06-12 京东方科技集团股份有限公司 一种静电释放保护电路及包括该电路的显示装置
FI20150334A (fi) 2015-01-14 2016-07-15 Artto Mikael Aurola Paranneltu puolijohdekokoonpano
FI20150294A (fi) * 2015-10-23 2017-04-24 Ari Paasio Matalan tehonkulutuksen logiikkaperhe
CN108806742B (zh) * 2017-05-04 2022-01-04 汤朝景 随机存取存储器并且具有与其相关的电路、方法以及设备
TWI688192B (zh) * 2018-11-06 2020-03-11 新唐科技股份有限公司 控制電路及其包含之半導體結構
CN113078888B (zh) * 2020-01-06 2024-04-19 达尔科技股份有限公司 栅极驱动设备和控制方法
US11101796B2 (en) 2020-01-06 2021-08-24 Diodes Incorporated Gate drive apparatus and control method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4062000A (en) * 1974-10-03 1977-12-06 Mostek Corporation Current sense amp for static memory cell
US5966324A (en) * 1996-12-05 1999-10-12 Mitsubishi Denki Kabushiki Kaisha Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells
US6363005B1 (en) * 2001-03-07 2002-03-26 United Microelectronics Corp. Method of increasing operating speed of SRAM
US6639835B2 (en) * 2000-02-29 2003-10-28 Micron Technology, Inc. Static NVRAM with ultra thin tunnel oxides
US6992915B2 (en) * 2002-03-27 2006-01-31 Regents Of The University Of California Self reverse bias low-power high-performance storage circuitry and related methods

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997038444A1 (fr) * 1996-04-08 1997-10-16 Hitachi, Ltd. Dispositif a circuit integre semi-conducteur
JP2976903B2 (ja) * 1996-10-08 1999-11-10 日本電気株式会社 半導体記憶装置
US6879199B2 (en) * 2002-02-15 2005-04-12 Valere Power, Inc. PWM control signal generation method and apparatus
US7345511B2 (en) * 2002-08-29 2008-03-18 Technion Research & Development Foundation Ltd. Logic circuit and method of logic circuit design
US6906962B2 (en) * 2002-09-30 2005-06-14 Agere Systems Inc. Method for defining the initial state of static random access memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4062000A (en) * 1974-10-03 1977-12-06 Mostek Corporation Current sense amp for static memory cell
US5966324A (en) * 1996-12-05 1999-10-12 Mitsubishi Denki Kabushiki Kaisha Static semiconductor memory device driving bit line potential by bipolar transistor shared by adjacent memory cells
US6639835B2 (en) * 2000-02-29 2003-10-28 Micron Technology, Inc. Static NVRAM with ultra thin tunnel oxides
US6363005B1 (en) * 2001-03-07 2002-03-26 United Microelectronics Corp. Method of increasing operating speed of SRAM
US6992915B2 (en) * 2002-03-27 2006-01-31 Regents Of The University Of California Self reverse bias low-power high-performance storage circuitry and related methods

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
See also references of WO2008092004A2 *
Y. TAKAHASHI ET AL.: "A Multiple-Valued SRAM with Combined Single-Electron and MOS Transistors", IEEE TRANS.ELECTRON DEVICES, vol. 43, 1996, pages 1213-1214, *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9328931B2 (en) 2011-02-11 2016-05-03 Esg Pool Ventilation Ltd Heating and/or cooling system for maintaining an environment at a desired temperature

Also Published As

Publication number Publication date
EP2287909A2 (fr) 2011-02-23
JP2010517204A (ja) 2010-05-20
EP2109890A4 (fr) 2010-02-10
WO2008092004A2 (fr) 2008-07-31
CN101632176A (zh) 2010-01-20
EP2287908A2 (fr) 2011-02-23
WO2008092004A3 (fr) 2008-10-16

Similar Documents

Publication Publication Date Title
US7817459B2 (en) Depletion-mode MOSFET circuit and applications
EP2287909A2 (fr) Circuit MOSFET à mode d'appauvrissement et application associée
US9071242B2 (en) Level shifters, methods for making the level shifters and methods of using integrated circuits
US10636457B2 (en) Overvoltage protection for a fine grained negative wordline scheme
US11088541B2 (en) Integrated circuit and electrostatic discharge protection circuit thereof
JPS63229748A (ja) Ｃｍｏｓ記憶セル集積回路
US9520182B2 (en) Memory elements with relay devices
US20060056220A1 (en) SRAM memory cell protected against current or voltage spikes
US7321506B2 (en) Multivibrator protected against current or voltage spikes
US10522214B2 (en) Robust negative bit-line and reliability aware write assist
Usami et al. Energy efficient write verify and retry scheme for MTJ based flip-flop and application
US20130314824A1 (en) Preventing electrostatic discharge (esd) failures across voltage domains
KR20080076411A (ko) 정전기 보호 회로
US20080165459A1 (en) Pad ESD Spreading Technique
TW200931804A (en) Apparatus and method for preventing snap back in integrated circuits
US7292482B2 (en) Multivibrator protected against current or voltage spikes
US7196959B2 (en) Implementation of a multivibrator protected against current or voltage spikes
US20220238509A1 (en) Electrostatic discharge circuit and electrostatic discharge control system
US6791886B1 (en) SRAM cell with bootstrapped power line
Tang et al. A novel ESD power clamp circuit with TSPCL D flip-flop
Elakkumanan et al. Leakage aware SER reduction technique for UDSM logic circuits
van der Meer et al. Effectiveness of Weak-Inversion Current Reduction

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20090813

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 27/088 20060101AFI20090826BHEP

Ipc: G11C 11/412 20060101ALI20091230BHEP

A4 Supplementary search report drawn up and despatched

Effective date: 20100113

DAX Request for extension of the european patent (deleted)
17Q First examination report despatched

Effective date: 20100504

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20110310