Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2340/00—Aspects of display data processing
  • G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels

Definitions

• the present invention relates generally to improving the processing of video signals in communication systems.
• the present invention relates to a system and method for adding on-screen display (OSD) information into a digital video signal.
• OSD on-screen display
• OSD on-screen display
• examples of the use of OSD information include closed captioning and subtitles for video programming.
• Another example is the display of a command name such as "PLAY” or "PAUSE” when a command button on a video display system is pressed.
• ROM character read only memory
• a typical character ROM may comprise 128 or 256 individual characters (or even more), both alphanumeric and graphic.
• character ROMs are effective in analog video systems, they present problems in digital video systems.
• OSD generators in analog systems typically employ a pixel clock having a relatively low clock speed in the range of 3 MHz to 12 MHz.
• digital video systems require a much faster pixel clock.
• the pixel clock in a digital OSD generator system may typically operate 3-4 times faster than the pixel clock in an analog OSD generator system.
• Some digital systems operate at a pixel clock speed of about 13.5 MHz, which is 4.5 times the typical minimum analog pixel clock speed of 3 MHz.
• character ROM size requirements are directly proportional to the pixel clock rate, a 3- or 4-fold (or more) increase in clock speed necessitates a proportional increase in the size of the character ROM. For example, when the pixel clock of a system employing a 12x18 character display is increased by a factor of four the character ROM must also be increased by a factor of four.
• a single character requiring 216 bytes of character ROM at the typical minimum analog pixel clock speed of 3 MHz requires at least 864 bytes of character ROM when the pixel clock speed is increased to the typical minimum pixel clock speed of 13.5 MHz for a digital system.
• the total character ROM requirement at the higher digital pixel clock speed is 110,592 bytes.
• the additional memory requirements make use of a typical character ROM scheme an undesirably expensive solution in a digital video system.
• Known alternatives to the use of character ROM in digital systems are similarly expensive and/or produce undesirable results.
• One such alternative is a dual conversion scheme whereby digital video data and OSD characters themselves are converted into an analog format before insertion of the characters into the digital video stream.
• Analog filter techniques are then used to smooth the OSD characters before insertion. Unfortunately, this process requires an additional conversion back to digital format which introduces artifacts of its own. The costs associated with such a dual conversion scheme are significant. An efficient system and method of inserting OSD information into a digital video stream which reduces transition artifacts is desirable.
• the disclosed embodiments relate to a system that is adapted to process digital video data.
• An exemplary embodiment of the system comprises a processor that produces a digital video data stream, and a character generator that is adapted to select a pixel data value from one of a plurality of standard data lines to insert into the digital video data stream based on a representation of a character stored in a memory associated with the character generator.
• An exemplary method relates to processing digital video data. The exemplary method comprises the acts of producing a digital video data stream, selecting a pixel data value from one of a plurality of standard data lines based on a representation of a character stored in a memory, and inserting the pixel data value into the digital video data stream.
• FIG. 1 is a block diagram of a digital video system in accordance with an exemplary embodiment of the present invention
• FIG. 2 is a block diagram of an OSD character generator in accordance with an exemplary embodiment of the present invention
• FIG. 3 is a diagram illustrating the use of a character map to provide OSD information
• FIG. 4 is a diagram that illustrates smooth transition data and sharp transition data, as well as associated data signals
• FIG. 5 is a diagram that illustrates data signals used to create OSD information in an analog video system
• FIG. 6 is a diagram illustrating the use of standard data signals to create
• FIG. 7 is a diagram showing in-phase data elements, anti-phase data elements, and associated data signals in accordance with an exemplary embodiment of the present invention.
• FIG. 8 is a diagram illustrating the use of decision points to indicate one of a plurality of standard data signals in accordance with an exemplary embodiment of the present invention.
• FIG. 9 is a state diagram that is useful in explaining the operation of an exemplary embodiment of the present invention.
• the present invention relates to a system and method for efficiently inserting OSD information into a digital video stream for display.
• An exemplary embodiment of the present invention employs a character memory that stores a coarse binary image (or bitmap) of each character using about the same resolution as typical for an analog video system.
• the required character memory is, accordingly, not significantly larger than the character memory required for an analog system.
• standard data signal or “standard data line” are used to refer to one of a relatively small group of data signals or data lines that may be used to create a much larger set of characters.
• the standard data lines which do not themselves represent any specific character, are used in conjunction with the stored character data to create any character in the character set.
• the only increase in character memory is the additional memory needed to store the small number (for example, four) standard data lines in high resolution digital format.
• the standard data lines are defined with smooth transitions, reducing the creation of undesirable artifacts when OSD characters are inserted into a digital video data stream.
• An exemplary embodiment of the present invention eliminates the need to store actual minimum, intermediate and maximum pixel level data for each character. Instead, the information stored in memory for each character provides a collection of decision points by which an adaptive address generator, such as an OSD character generator, selects one of a small and finite number of standard data lines to construct the desired character.
• the adaptive address generator employs appropriate rising/falling edges and maximum/minimum level values.
• OSD characters are created by the insertion of generic rising/falling edges and predetermined maximum/minimum level values. In this manner, any alphanumeric character or icon may be created without significantly increasing memory requirements relative to conventional systems.
• FIG. 1 is a block diagram of a digital video system in accordance with an exemplary embodiment of the present invention.
• the video system is generally referred to by the reference number 100.
• the video system 100 comprises a processor 110, which obtains digital video data from a source such as a DVD player or the like (not shown).
• the processor 110 produces a digital video data stream 112 and delivers it to an OSD character generator 114 for further processing.
• the OSD character generator 114 is connected to a memory 118 by a memory interface 116.
• the memory 118 stores bitmap representations of various alphanumeric and icon data for transformation into OSD character information.
• Such OSD information is inserted into the digital video data stream 112 by the OSD character generator 114 to produce a digital video data stream with OSD information included. That data stream is referred to herein as an OSD digital video data stream 120.
• the OSD digital video data stream 120 is used to create an image on a display 122, for viewing by a user of the system.
• FIG. 2 is a block diagram of an OSD character generator circuit in accordance with an exemplary embodiment of the present invention.
• the OSD character generator circuit 200 includes a microcontroller 204 which generally controls the operation of the circuit.
• the microcontroller 204 operates to insert OSD characters into the digital video data stream 112 (FIG. 1) thereby producing digital video out w/ OSD signal 120.
• a first switch circuit 206 selectively receives OSD data (position a) or digital video data from the digital video data stream 112 (position b).
• first switch circuit 206 which is shown in FIG. 2 as a mechanical switch for purposes of functional illustration only, may comprise a multiplexer and/or other appropriate circuitry. Moreover, the specific components and construction details of first switch circuit 206 are not an essential feature of the present invention.
• a second switch circuit 208 selects between one of a plurality of standard data lines to create OSD characters for insertion into the digital video data stream 112.
• the second switch circuit 208 which is shown in FIG. 2 as a mechanical switch for purposes of functional illustration only, may comprise a multiplexer or other circuitry. Moreover, the specific components and construction details of second switch circuit 208 are not an essential feature of the present invention.
• the separate standard data lines selected by second switch circuit 208 are stored in the memory 118 as in-phase data 212, all-high data 214, anti-phase data 216 and all-low data 218. The specific composition of these data lines is discussed in greater detail below.
• the data lines 212-218 stored in the memory 118 are combined with relatively low resolution character data stored in the character memory 210 to create alphanumeric and/or graphic OSD characters for insertion into the digital video data stream 112 by second switch circuit 208 thereby forming digitial video output w/ OSD signal 120.
• the following example explains the insertion of OSD characters into the digital video data stream 112 by the OSD character generator 200.
• the microcontroller 204 receives an input, such as user input, intended to create an onscreen display.
• An example of such an input is the signal created by the pushing of a "play” button on a DVD player that is associated with the OSD character generator circuit 200.
• the external stimulus indicating the need for OSD data causes microcontroller 204 to place first switch circuit 206 in position a.
• the pressing of the "play” button is intended to cause the word “PLAY" to be displayed on a video screen associated with the system.
• the microcontroller 204 selects the alphanumeric characters "P", "L”, “A”, "Y” from the character memory 210.
• the microcontroller appropriately (as described below) chooses data from the in-phase data 212, all-high data 214, anti-phase data 216 and all-low data 218 to insert the appropriate characters into the digital video data stream 112.
• the resultant OSD digital video data stream 120 contains both the original video data and the added OSD character data.
• first switch circuit 206 is returned to position b.
• FIG. 3 is a diagram illustrating a character map that is used to define data to be inserted into a digital video data stream 112 (FIG. 1) as OSD information.
• the diagram is generally referred to by the reference number 300.
• a character map grid 302 provides a framework for the definition of alphanumeric characters and icons in a character map.
• the character map grid 302 comprises a 12x18 array of elements (shown as squares, but not referenced) that represent characters stored in a character memory such as the character memory 210 (FIG. 2). Each element contains a predetermined number of display pixels.
• FIG. 3 illustrates a numeric character 4 in the character map grid 302.
• each of the pixels within an individual element have separate respective pixel data values associated therewith.
• each element of the character map grid 300 represents 3 pixels of data, as shown by a set of pixel data 304.
• the number of pixels represented by each element of a character map varies, but three or four pixels per element are typical.
• the number of pixels represented by each element of the character map grid 302 is not an essential feature of the present invention.
• Each pixel data value may comprise a digital data word of, for example, 8 bits.
• an increased clock rate typical of digital video systems results in the need for 3 or 4 pixels of data for each element of the character map grid 302, as well as the corresponding increase in size of the character memory.
• An exemplary set of pixel transition data 306 illustrates the problem of artifact creation resulting from sharp data transitions.
• the pixel data value of the first three pixels in the transition data 306 is FEh. This value represents the maximum pixel data value in a typical 8-bit digital video system. In the example shown in FIG. 3, the value FEh corresponds with the color black. In the example shown in FIG. 3, the pixel data values for the right three data locations 306 (02h) represent the color white, which provides the most possible contrast with respect to the maximum pixel data value FEh.
• a maximum transition in values occurs between pixels three and four, i.e., a transition from the highest pixel data value possible (FEh) to the lowest pixel value possible (02h) occurs from one pixel (the third value) to the next pixel (the fourth value).
• FEh highest pixel data value possible
• 02h lowest pixel value possible
• the fourth value the fourth value
• Such a sharp transition in pixel data value is likely to create an undesirable artifact when displayed on a video display.
• exemplary embodiments of the present invention produce OSD data without sharp transitions and the resulting undesirable video artifacts, and do so without requiring increased system memory necessitated by the use of high resolution character maps.
• FIG. 4 is a diagram that illustrates smooth transition data and sharp transition data, as well as associated data signal waveforms.
• the graph is generally referred to by the reference number 400.
• FIG. 4 is useful in explaining the memory savings that may be achieved by an exemplary embodiment of the present invention. It should be noted that smooth transition data can be programmed into the character memory for each character, but that doing so incurs a three- to fourfold memory increase. Embodiments of the present invention, however, may achieve smooth transitions and yet may require only a relatively small increase in character memory requirements.
• FIG. 4 shows a plurality of sharp transition data values 402, each of which corresponds to one pixel value.
• the first four sharp transition data values 402 have a value of FEh, which is the maximum value in a typical 8-bit digital video system. Those bytes are immediately followed by four bytes having a value of 02h, which is the minimum allowable value in a typical system.
• the result is a sharp transition wave form 404 when corresponding data is applied to a digital video data stream, such as the digital video data stream 112 (FIG. 1).
• FIG. 4 also shows a plurality of smooth transition data values 406.
• the smooth transition data elements employ only two data elements of maximum value (FEh) followed by two successively smaller valued data elements.
• FEh data elements of maximum value
• the first of the two successively smaller data elements has a value of 56h and the second of the successively smaller data elements has a value of 28h.
• the remaining four smooth transition data values 406 have a minimum value of 02h.
• a digital video data stream such as the digital video data stream 112 (FIG. 1)
• the creation of undesirable video artifacts may be substantially reduced relative to abruptly transitioning data values.
• a challenge is to create smooth transitions without the significant increase in memory capacity that is typically needed for character mapping in a conventional digital video system. A further illustration of this challenge is explained below with reference to FIG. 5.
• FIG. 5 is a diagram that illustrates data signals used to create OSD information in a character ROM system.
• the diagram explaining the character map operation is generally referred to by the reference number 500.
• a character map grid 502 has eighteen lines of data. As with the character map grid 302 (FIG. 3), each of the elements (squares) of the character map grid 502 corresponds to multiple pixels on a display screen.
• the character map grid 502 contains representations of two characters, a numeral 8 and a numeral 9.
• a character data signal 504 shows data used to produce line 11 of the character map grid 502.
• a character data signal 506 illustrates the data used to create line 12 of the character map grid 502.
• the character data signal 504 is high for corresponding elements of the character map grid 502 in which a maximum pixel data value (FEh) is present in line 11, and low (02h) otherwise.
• FEh maximum pixel data value
• the elements having a value of FEh (which are shown as darkened or solid elements) are elements that actually form a portion of the character being displayed (the numerals 8 and 9 in FIG.
• the character data signal 506 is high in corresponding grid elements where the data value is a maximum pixel data value (FEh) in line 12, and a minimum pixel data value (02h) otherwise.
• FEh maximum pixel data value
• 02h minimum pixel data value
• lines 3 and 16 are also identical. Of the 18 lines of the character map grid 502, there are 10 different variations or unique line patterns. Thus, creation of the display shown in FIG. 5 can be accomplished using only 10 lines of data rather than 18 (the total number of lines in the character map grid 502).
• System memory is saved by storing the lines that are repeated only once in a character memory and accessing the stored lines again for successive occurrences of those patterns.
• the memory savings that is obtained is of limited practical utility since savings is derived with regard to only those characters that can be created with the 10 lines of data.
• Exemplary embodiments of the present invention achieve substantial memory savings relative to a conventional digital video system by using standard data signals, as is hereinafter more particularly described, to create OSD characters having smooth transitions.
• FIG. 6 is a diagram illustrating the use of standard data signals to create OSD character information in accordance with an exemplary embodiment of the present invention.
• the diagram is generally referred to by the reference number 600.
• a character map grid 602 is shown depicting the display of a numeral 8 and a numeral 9.
• each of the elements (squares) of the character map grid 602 corresponds to multiple pixels on a display screen.
• An exemplary embodiment of the present invention employs four distinct standard data lines from which any character desired for insertion into a digital video bit stream may be created.
• an entire character set e.g., 128 or 256 characters
• This coarse format is only about one-third or one-quarter of the resolution needed to create the characters at a full digital video pixel rate. In other words, the memory requirements for storage of the character set would be about the same as for a typical analog system.
• an additional four lines of data are stored in full resolution (i.e., sufficient for display at the mil digital video pixel rate). These four lines make up standard data lines that are selectively accessed to create all the characters of the character set, while producing smooth, relatively artifact free transitions.
• the four standard data lines stored in full resolution format include an in-phase data line 604, an all-high data line 606, an anti-phase data line 608 and an all-low data line 610.
• the anti-phase data line 608 is the opposite of the in-phase data line 604, i.e., the anti-phase data line 608 is one-hundred and eighty (180) degrees out of phase with the in-phase data line 604.
• the only additional memory needed relative to a conventional analog system is the amount of memory used to store the four standard data lines 604, 606, 608 and 610 in high resolution format.
• a considerable savings in memory size is achievable in an exemplary embodiment of the present invention relative to the memory size required to store an entire character set of 128 or 256 characters in high resolution format.
• Line n is the same as line 11 illustrated in FIG. 5.
• FIG. 6 includes sequential reference numbers (shown immediately below or underneath line n) corresponding to each element in line n.
• Line n itself includes either a 0 or 1, depending on the corresponding pixel data value of the pixels for that element of the character display.
• a 1 pixel data value FEh
• a 0 corresponds to all other elements of the character grid map 602.
• Elements 1 and 2 of line n which are 0s, are formed by selection of the all- low data line 610 by the microcontroller 204 (FIG. 2).
• the all-low data line 610 is selected by referencing the data for the corresponding elements of line n of the numeral 8 in the coarse image data stored in character memory.
• element 3 of line n is a 1 because that element is needed to form the numeral 8 in the character map 602. Because the prior state was a 0, a rising edge is needed for element 3.
• the microcontroller 204 (FIG. 2) selects the anti-phase data line 608 to apply in element 3. Because elements 4 and 5 are also high, the microcontroller 204 (FIG.
• an exemplary embodiment of the present invention thus forms any character stored in a coarse resolution character map without significantly increasing system memory requirements.
• FIG. 7 is a diagram showing in-phase data, anti-phase data, and associated data signals in accordance with an exemplary embodiment of the present invention.
• the graph is generally referred to by the reference number 700.
• FIG. 7 shows how an exemplary embodiment of the present invention may be employed to provide smooth, rather than sharp, transitions between pixels that have pixel data values of significantly different magnitude (e.g., FEh and 02h), and thereby avoid the resulting undesirable image artifacts.
• the in-phase data signal 604 (FIG. 6) and the antiphase data signal 608 (FIG. 6) are data signals representative of pixel data values that change state, they are stored in high resolution format (unlike the associated character memory).
• the in-phase and anti-phase data signals 604, 608 are programmed with or include pixel data values that result in a smooth transition when displayed, as shown in FIG. 7.
• a plurality of in-phase pixel data values 702a, b, c, . . . n corresponds to a segment 704 of smooth in-phase signal 604.
• Each of the in-phase pixel data values 702a, b, c, . . . n are stored in respective memory locations (not shown).
• the first two in-phase pixel data values 702a, b are a high or maximum pixel data value, such as FEh.
• a high-to- low transition begins.
• the third pixel data value 702c has a transitional value of 56h, and the following pixel data value 702d is programmed at a successively lower transitional value, such as 28h.
• the next two pixel data values (702e and 702f) have minimum values, such as 02h, followed by a low-to-high transition in the following two pixel data values 702g, h and i.
• the low- to-high-transition is accomplished by programming for pixel data values 702g, h and i successively greater values, such as 28h, 56h and FEh, as shown in FIG. 7.
• a segment 706 of the smooth anti-phase data signal 608 (FIG.
• the first two anti-phase pixel data values 708a, b are a low or minimum value, such as 02h.
• the following low-to-high-transition includes pixel data values 708c and d, which are assigned successively higher transitional values, namely 28h for pixel data value 708c and 56h for pixel data value 708d.
• Subsequent smooth transitions are similarly accomplished using transitional data values rather than extreme differences in pixel data values or abrupt opposites.
• the combination of coarsely stored character data with the standard data lines 604, 606, 608 and 610 allow creation and insertion of any desired character into a digital video bit stream with smooth transitions at a minimum increase in memory compared to typical analog video systems.
• FIG. 8 is a diagram illustrating the use of decision points to determine which one of a plurality of standard data lines is accessed in order to assign its corresponding pixel data value to an actual pixel element of a display in accordance with an exemplary embodiment of the present invention.
• the diagram is generally referred to by the reference number 800.
• OSD character data is provided in groups of four bytes, each of which corresponds to one pixel data value. This means that, for every four pixel data values, a decision must be made as to which of the standard data lines contains the next successive pixel data values needed to create the display of the character from the character map 602 that is currently being displayed.
• in-phase data 802 from the in-phase data line 604 (FIG. 6) is currently chosen for display
• a decision about whether to switch to pixel data values corresponding to another of the standard data lines occurs at each of a plurality of decision points 804, which correspond to every fourth pixel data value.
• a decision is made every four pixel data values to continue displaying pixel data values corresponding to the current one of the four standard data lines or to switch to pixel data value from a different one of the standard data lines.
• FIG. 9 is a state diagram that is useful in explaining the operation of an exemplary embodiment of the present invention.
• the state diagram is generally referred to by the reference number 900.
• the state diagram 900 describes the operation of an exemplary embodiment of the present invention that employs a 12-bit memory addressing scheme.
• the two most significant address bits (MSBs) A 10 and An may be used to select the specific one of the four stored high resolution standard data lines.
• the two MSB address bits may be considered as a row address, with each of the four standard data lines comprising the row.
• the 10 least significant bits (LSBs) A 0 through A 9 provide the address of individual data values for each of the standard data lines selected by the two MSBs.
• the 10 LSB address lines may be considered as a column address.
• the 10 LSB data lines may be generated by a 10-bit up-counter synchronized with a video line.
• the MSB address lines may be selected by an adaptive address generator such as the microcontroller 204 (FIG. 2) according to the state diagram 900. Address switching takes place, if needed, at periodic decision points, as discussed above with reference to FIG. 8.
• the operations represented by the state diagram 900 exploit the fact that certain pixel data values for the standard in-phase data line 604 (FIG. 6) have been purposely chosen to correspond to the value of one of the address lines used to access the memory location that retains that particular in-phase pixel data value.
• the data value of the standard in-phase data line (either "0" or "1") is chosen to be the same as the value of an address line A 2 .
• the maximum and minimum pixel data values corresponding to the in-phase data line 604 (FIG. 6) are purposely stored in memory locations chosen to allow the state of those pixel data values to be the same as the value of the A 2 address line for those memory locations. In this manner, the pixel data value for the in-phase data line may be determined by the state of the address line A 2 without checking the actual data value itself.
• the value of A 2 is selected to correspond to the pixel data value of a particular one of the standard data lines because the OSD character data is by definition organized into groups of four pixel values. A separate address location is needed for each of the four pixel values of data. Therefore, the two least significant address lines (Ao and Ai) can not be categorically defined to correspond to the data because they must change within each four pixel group of data to access the data. In other words, address line A 2 is chosen to correspond to the value of the data because address line A 2 is the least significant address line that is guaranteed to be constant for any group of four data values.
• the data value of all of the four standard data lines are known at any given point just by knowing the value of the address line A 2 for the standard in-phase data line 604 (FIG. 6).
• the value of the data for the in-phase data line 604 (FIG. 6) is the same as the value of A 2 (by definition).
• the corresponding value of the standard anti-phase data line 608 (FIG. 6) is the opposite of the value of the standard in-phase data line 604 (FIG. 6).
• the values of the standard all-high data line 604 (FIG. 6) and all-low data line 610 (FIG. 6) are constant. This means that the value of A 2 may be tested at each transition point to determine which of the standard data lines should be chosen to contribute the next four-pixel group of pixel data values.
• each member of the four pixel groups of OSD character data do not have to be the same.
• defining elements of the groups of four values (such as the second and third values of each set) to have successively increasing or decreasing intermediate values allows smooth transitions and reduces the creation of artifacts, as described above.
• Each of the groups of four pixel values comprises either a rising edge or a falling edge in this example.
• the state diagram 900 shows an in-phase data state 902, an anti-phase data state 904, an all-high data state 906 and an all-low data state 908. Each of these data states corresponds to one of the four standard data lines described herein. Moreover, those of ordinary skill in the art will appreciate that the state diagram 900 is useful for creating programming to govern the operation of the microcontroller 204 (FIG. 2) as it selects among the standard data lines to produce OSD character data. If the microcontroller 204 has selected pixel data values from the in-phase data line 212 (FIG.
• the microcontroller 204 is referred to herein as being "in the in-phase data state 902.”
• the microcontroller 204 has selected the all-high data line 214 (FIG. 2), the microcontroller 204 is referred to herein as being "in the all-high data state 906,” and so on.
• the microcontroller 204 If the microcontroller 204 is in the in-phase data state 902, it will remain there if, at a decision point, the current state of address line A 2 does not equal the next character bit (from the coarsely stored character representation stored in the character memory 210 (FIG. 2)) to be displayed. If, at a decision point, the microcontroller 204 is in the in-phase data state 902, the next character bit from the character memory 210 (FIG. 2) is a 1 and the current state of address line A 2 is a 1, the microcontroller 204 will transition to the all-high data state 906. If, at a decision point, the microcontroller 204 is in the in-phase data state, the next character bit from the character memory 210 (FIG. 2) is a 0 and the current state of address line A 2 is a 0, the microcontroller 204 will transition into the all-low data state 908.
• the microcontroller 204 If the microcontroller 204 is in the all-high data state 906, it will remain in that state so long as the next character bit from the character memory 210 (FIG. 2) is a 1. If, at a decision point, the microcontroller 204 is in the all-high data state 906, the microcontroller 204 will transition into the anti-phase data state 904 if the next character bit from the character memory 210 (FIG. 2) is a 0 and the current state of A 2 is also 0. If, at a decision point, the microcontroller 204 is in the all-high data state 906, the microcontroller 204 will transition to the in-phase data state 902 if the next character bit from the character memory 210 (FIG. 2) is a 0 and the current state of address line A 2 is a 1.
• the microcontroller 204 If the microcontroller 204 is in the all-low data state 908, it will remain there so long as the next character bit from the character memory 210 (FIG. 2) is a 0. If, at a decision point, the microcontroller 204 is in the all-low data state 908, the microcontroller 204 will transition to the anti-phase data state 904 if the next character bit from the character memory 210 (FIG. 2) is a 1 and the current state of address line A 2 is also a 1. If, at a decision point, the microcontroller 204 is in the all-low data state 908, the microcontroller 204 will transition to the in-phase data state 902 if the next character bit from the character memory 210 (FIG. 2) is a 1 and the current state of address line A 2 is a 0.
• the microcontroller 204 If the microcontroller 204 is in the anti-phase data state 904, it will remain there so long as the current state of the address line A 2 is equal to the next character bit from the character memory 210 (FIG. 2). If, at a decision point, the microcontroller 204 is in the anti-phase data state 904, the microcontroller will transition to the all-high data state 906 if the next character bit from the character memory 210 (FIG. 2) is a 1 and the current state of the address line A 2 is a 0. If, at a decision point, the microcontroller 204 is in the anti-phase data state 904, the microcontroller 204 will transition to the all-low data state 908 if the next character bit from the character memory 210 (FIG. 2) is a O and the current state of the address line A 2 is a 1.

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