EP1972702B1 - Verfahren zur herstellung von aluminiumnitridkristall, aluminiumnitridkristall, aluminiumnitridkristallsubstrat und halbleiterbauelement - Google Patents

Verfahren zur herstellung von aluminiumnitridkristall, aluminiumnitridkristall, aluminiumnitridkristallsubstrat und halbleiterbauelement Download PDF

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EP1972702B1
EP1972702B1 EP07706498.8A EP07706498A EP1972702B1 EP 1972702 B1 EP1972702 B1 EP 1972702B1 EP 07706498 A EP07706498 A EP 07706498A EP 1972702 B1 EP1972702 B1 EP 1972702B1
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Prior art keywords
aluminum nitride
dislocations
nitride crystal
aln crystal
crystal
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French (fr)
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EP1972702A1 (de
EP1972702A4 (de
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Naho Mizuhara
Michimasa Miyanaga
Tomohiro Kawase
Shinsuke Fujiwara
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/38—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension

Definitions

  • the present invention relates to methods of manufacturing aluminum nitride (AlN) crystals, and to AlN crystals and AlN-crystal substrates and semiconductor devices, and in particular relates to a method of manufacturing AlN crystal, and to AlN crystals, AlN crystal substrates, and semiconductor devices fabricated employing the AlN crystal substrates, that enable semiconductor devices having advantageous properties to be obtained.
  • AlN aluminum nitride
  • AlN crystal substrates have gained attention as substrates for optoelectronic and other semiconductor devices on account of the crystal's having an energy bandgap of 6.2 eV, a thermal conductivity of approximately 3.3 WK -1 cm -1 , and high electrical resistance.
  • AlN crystal substrates can be produced from AlN crystal grown by sublimation, hydride vapor-phase epitaxy (HVPE), or other deposition techniques onto the surface of seed-crystal substrates such as silicon (Si) or silicon-carbide (SiC) crystal substrates.
  • HVPE hydride vapor-phase epitaxy
  • Non-Patent Reference 1 B. Raghothamachar, M. Dudley, J.C. Rojo, K Morgan and L.J. Schowalter, "X-ray Characterization of Bulk AIN Single Crystals Grown by the Sublimation Technique", Journal of Crystal Growth, Vol. 250, March 2003, p.244 .
  • Non-Patent Reference 2 X.
  • vapor depositing nitride semiconductor monocrystalline layers onto an AlN crystal substrate having as large a surface as possible to obtain as many semiconductor devices as possible from a single AlN crystal substrate is effective.
  • US 2004/0187766 relates to a method of fabricating monocrystalline crystals and discloses all of the features in the preamble of claim 1.
  • an object of the present invention is to make available AlN crystal manufacturing methods, and AlN crystals, AlN crystal substrates, and semiconductor devices fabricated employing the AlN crystal substrates, that make it possible to obtain semiconductor devices having advantageous device properties.
  • the present invention affords methods of manufacturing AlN crystals, and AlN crystals, AlN crystal substrates, and semiconductor devices fabricated employing the AlN crystal substrates, that enable semiconductor devices having advantageous properties to be obtained.
  • the conventional thinking has been that the lower the dislocation density is in the AlN crystal constituting AlN crystal substrates, the better; the present inventors, however, discovered that if the dislocation density in the AlN crystal constituting AlN crystal substrates is too low, the semiconductor device properties deteriorate.
  • the present inventors then found that in AlN crystal substrates constituted from bulk AlN crystal having a front side whose surface area is 10 cm 2 or more, by having the dislocation density in the AlN crystal constituting the AlN crystal substrate be from 1 ⁇ 10 3 dislocations/cm 2 to 1 ⁇ 10 6 dislocations/cm 2 , the properties of the semiconductor devices prove to be ideal, wherein they came to complete the present invention.
  • the semiconductor device properties degenerate.
  • the semiconductor device properties degenerate.
  • the impurities and deposits remain in the regions of the AlN-crystal-substrate-constituting AlN crystal where there are few dislocations, degrading the crystalline quality of the regions where the dislocations are few, and in turn degrading the crystalline quality of semiconductor films grown over the regions where dislocations are few.
  • Semiconductor device properties are thought to be thereby adversely affected in implementations in which the dislocation density in the AlN-crystal-substrate-constituting AlN crystal is, at less than 1 ⁇ 10 3 dislocations/cm 2 , too low.
  • the AlN crystal constituting the AlN crystal substrate at least one dislocation type selected from the group consisting of screw dislocations, edge dislocations, and mixed dislocations in which the screw and edge dislocations are mixed can be included.
  • the ratio of the dislocation density of screw dislocations to the density of dislocations overall in the AlN crystal is preferably 0.2 or less.
  • the present inventors discovered that in implementations in which semiconductor devices have been fabricated, by processes including the successive deposition of semiconductor films, onto the front side of AlN crystal substrates constituted by AlN crystal in which the dislocation density of screw dislocations is 1 ⁇ 10 4 dislocations/cm 2 or less, the semiconductor device properties tend to be even more satisfactory, and that there is a similar tendency also in implementations in which screw dislocations are not present in the AlN crystal constituting the AlN crystal substrate.
  • a dislocation in the AlN crystal corresponds is decided from the size of the etch pits formed on the AlN crystal substrate surface by the above method.
  • the largest diametric span of the pit is from 10 ⁇ m to 15 ⁇ m
  • the largest diametric span of the pit is from 1 ⁇ m to 5 ⁇ m.
  • "largest diametric span" in the present invention means the length of the longest line segment among line segments connecting two points present on the margin of an etch pit.
  • AlN crystal of the present invention in the course of growing AlN crystal by, for example, sublimation onto a seed-crystal substrate such as an Si crystal substrate or an SiC crystal substrate, and the AlN crystal being lengthened by the AlN crystal growth, with the major portion of the dislocations in the AlN crystal presumably propagating in directions other than along the c axis, the dislocation density in the AlN crystal lessens at a greater remove from the seed-crystal substrate, and this fact is utilized in the AlN crystal's manufacture.
  • a seed-crystal substrate such as an Si crystal substrate or an SiC crystal substrate
  • a SiC seed-crystal substrate 3 having the surface whose area is 10 cm 2 of more is prepared as seed-crystal substrate, and an AlN crystal 8 is grown by sublimation onto the surface of the SiC seed-crystal substrate 3.
  • the AlN crystal 8 b manufactured in this manner was rendered the AlN crystal having the surface whose area is 10 cm 2 or more with a dislocation density in the AlN crystal being between 1 ⁇ 10 3 dislocations/cm 2 and 1 ⁇ 10 6 dislocations/cm 2 inclusive-preferably with a dislocation density in the AlN crystal being between 2 ⁇ 10 4 dislocations/cm 2 and 5 ⁇ 10 6 dislocations/cm 2 inclusive.
  • an AlN crystal substrate composed of the AlN crystal 8 b manufactured in the above manner
  • an AlN crystal is grown by sublimation onto the surface of the AlN crystal substrate serving as seed-crystal substrate, and then at least a piece of the grown AlN crystal is picked out, also in which manner the AlN crystal having the surface whose area is 10 cm 2 or more with a dislocation density in the AlN crystal being between 1 ⁇ 10 3 dislocations/cm 2 and 1 ⁇ 10 6 dislocations/cm 2 inclusive-preferably with a dislocation density in the AlN crystal being between 2 ⁇ 10 4 dislocations/cm 2 and 5 ⁇ 10 5 dislocations/cm 2 inclusive can be manufactured.
  • the SiC seed-crystal substrate 3 serving as seed-crystal substrate in the forgoing preferably has a thickness of 150 ⁇ m or more to 400 ⁇ m or less, and more preferably has a thickness of 150 ⁇ m or more to 350 ⁇ m or less, with a thickness of 150 ⁇ m or more to 300 ⁇ m or less being most preferable. Bringing thickness of the SiC seed-crystal substrate 3 to above thicknesses facilitates manufacturing the AlN crystal having the dislocation densities described above.
  • a temperature of the SiC seed-crystal substrate 3 during the growth of the aluminum nitride crystal 8 onto the surface of the SiC seed-crystal substrate 3 is preferably 1650°C or more. It is conceivable that screw dislocations are reduced utilizing the fact that employing the SiC seed-crystal substrate 3 differing approximately 1 % in lattice constant from the AlN crystal 8 causes lattice relaxation to occur at a few ⁇ m from the SiC seed-crystal substrate 3, resulting in that a large part of the screw dislocations loops and disappears.
  • An AlN crystal is grown by sublimation onto the surface of a SiC seed-crystal substrate 2 inches in diameter and 250 ⁇ m in thickness in the following manner.
  • FIG. 3 A cross-sectional schematic diagram of an AlN crystal growing device employed in this embodiment is illustrated in Fig. 3 .
  • an AlN source 2 such as AlN powder is accommodated in the under part of a graphite crucible 1, and the SiC seed-crystal substrate 3 whose surface has been processed to be flat is arranged in the top part of the crucible 1.
  • a seed-crystal substrate protector 4 made of graphite is arranged so as to closely attach to the back side.
  • a heating element 7 is heated with a high-frequency heating coil 6 to raise temperature in the crucible 1.
  • temperature in the part of the crucible 1 where the SiC seed-crystal substrate 3 is arranged being kept at 2000°C
  • temperature in the part of the crucible 1 where the AlN source 2 is accommodated being kept at 2200°C
  • AlN is sublimated from the AlN source 2 to grow an AlN crystal film about 30 ⁇ m in thickness onto the surface of the SiC seed-crystal substrate 3 arranged in the top part of the crucible 1, and then the temperature in where the AlN source 2 is accommodated is raised to 2400°C, and the AlN crystal 8 is grown for 100 hours.
  • the AlN crystal 8 is cooled to room temperature (of 25°C), and is removed from the device. Then the 10 mm-thick AlN crystal 8 is grown onto the SiC seed-crystal substrate 3 with diameter of 2 inches.
  • slicing is started at an interval 2 mm or more into the AlN crystal 8 obtained in above manner from the surface of the SiC seed-crystal substrate 3, and 10 AlN crystal substrates 9 having the (0002) plane as the surface, with diameter of 2 inches are fabricated. Successively, the Al faces of these 10 AlN crystal substrates 9 are specular-polished.
  • an AlN crystal 10 is grown onto the surfaces of the AlN crystal substrates 9 obtained in above manner by sublimation in which the growing device illustrated in Fig. 1 is employed.
  • the temperature in where the AlN crystal substrates 9 are arranged being kept at 2000°C
  • the temperature in where the AlN source 2 is accommodated is raised from room temperature to 2400°C at a constant gradient, and AlN is sublimated from the AlN source 2, to grow the AlN crystal 10 for 100 hours.
  • the grown AlN crystal 10 is cooled to room temperature (of 25°C), and is removed from the growing device. As a result, the AlN crystal 10 having a diameter of a little less than 2 inches is produced. Subsequently, as illustrated in the cross-sectional schematic diagram in Fig. 6 , the AlN crystal 10 is sliced to pick out an AlN crystal substrate 11.
  • dislocation density in the AlN crystal substrates 9 has a tendency to lower with greater distances from the SiC seed-crystal substrate 3.
  • dislocations in the AlN crystal substrate 11 picked out from the AlN crystal 10 have the almost same density and distribution as the AlN crystal substrates 9 utilized as seed-crystal substrate. For this reason, the AlN crystal substrate 11 with a desired dislocation density and distribution can be produced with adequate reproducibility.
  • Semiconductor films and metal films are successively deposited onto the Al face of each of 10 AlN crystal substrates 22 sliced off from the AlN crystal 8 or AlN crystal 10 and differing from each other in dislocation density to fabricate field-effect transistors having the structure illustrated in the cross-sectional schematic diagram in Fig. 7 .
  • a 0.5 ⁇ m-thick AlN film 12, 100 nm-thick GaN film 13, and 30 nm-thick AlGaN film 14 are epitaxially grown to deposit them successively on the Al face of the AlN crystal substrates 22 by metalorganic chemical vapor deposition (MOCVD).
  • MOCVD metalorganic chemical vapor deposition
  • the AlN film 12 and GaN film 13 are each undoped.
  • a Ti film 15, Al film 16, Ti film 17 and Au film 18 are deposited successively onto the surface of the AlGaN film 14 to form a source electrode 19 and drain electrode 20 separately.
  • a gate electrode 21 composed of an Au film is formed between the source electrode 19 and the drain electrode 20 on the surface of the AlGaN film 14.
  • the gate length is 2 ⁇ m, and intervals between the gate electrode 21 and the source electrode 19, and between the gate electrode 21 and the drain electrode 20 are respectively 10 ⁇ m.
  • the wafer after the formation of the gate electrode 21 is divided into chips, and the field-effect transistors having the structure illustrated in Fig. 7 are fabricated.
  • breakdown voltages of those of the field-effect transistors which are fabricated employing an AlN crystal substrate composed of an AlN crystal having a dislocation density of 1 ⁇ 10 3 dislocations/cm 2 or more to 1 ⁇ 10 6 dislocations/cm 2 or less are high, and particularly in those of the field-effect transistors which are fabricated employing an AlN crystal substrate composed of an AlN crystal having a dislocation density of 2 ⁇ 10 4 dislocations/cm 2 or more to 1 ⁇ 10 6 dislocations/cm 2 or less, their breakdown voltages stabilize at a higher 1200 to 1250 V
  • the AlN crystal substrate composed of the AlN crystal in which a dislocation density is between 2 ⁇ 10 4 dislocations/cm 2 and 1 ⁇ 10 5 dislocations/cm 2 inclusive is employed, with at least one type of dislocation selected from the group consisting of screw, edge, and mixed dislocations being included in the AlN crystal, and with a ratio of the dislocation density in terms of screw dislocations to the density of all dislocations in the AlN crystal being more than 0.2
  • field-effect transistor breakdown voltages between the gate electrode 21 and the drain electrode 20 are brought to 1050 to 1100 V, meaning that the break down voltages are made lower compared with the breakdown voltages (1200 to 1250 V) in the situation in which above ratio of the dislocation density in terms of screw dislocations is 0.2 or less,.
  • dislocation density in terms of screw dislocations in AlN crystal substrates is preferably 1 ⁇ 10 4 dislocations/cm 2 or less.
  • the semiconductor device evaluation is carried out based on the field-effect transistor breakdown voltages between the gate electrode and the drain electrode, it is believed that as to other semiconductor devices whose properties are influenced by crystallinity of semiconductor films, evaluation results similar to those in above examples can be obtained.
  • the following semiconductor devices can be fabricated: light-emitting devices (such as light-emitting, and laser diodes); electronic devices (such as rectifiers, bipolar transistors, field-effect transistors, and HEMTs); semiconductor sensors (such as temperature, pressure, and radiation sensors, and visible light-ultraviolet detector); surface acoustic wave (SAW) devices; acceleration sensors; micro electro mechanical system (MEMS) parts; piezoelectric vibrators; resonators; and piezoelectric actuators, for example.
  • light-emitting devices such as light-emitting, and laser diodes
  • electronic devices such as rectifiers, bipolar transistors, field-effect transistors, and HEMTs
  • semiconductor sensors such as temperature, pressure, and radiation sensors, and visible light-ultraviolet detector
  • SAW surface acoustic wave
  • MEMS micro electro mechanical system
  • piezoelectric vibrators piezoelectric vibrators
  • resonators piezoelectric actuators

Claims (7)

  1. Verfahren zur Herstellung eines Aluminiumnitridkristalls, das Folgendes einschließt:
    einen Schritt des Wachsens eines Aluminiumnitridkristalls auf eine Oberfläche eines SiC Saatkristallsubstrats; und
    ein Schritt des Herausnehmens mindestens eines Teils des Aluminiumnitridkristalls, der in einem Bereich von 2mm bis 60mm von der SiC Saatkristallsubstratoberfläche zum Aluminiumnitridkristall liegt,
    wobei die Dicke des SiC Saatkristallsubstrats (3) zwischen 150 µm und einschließlich 300 µm ist, und
    die Temperatur des SiC Saatkristallsubstrats, wenn der Aluminiumnitridkristall auf der SiC Saatkristallsubstratoberfläche aufgewachsen wird, 1650° C oder mehr ist; und
    das Aluminiumnitridkristallwachstum auf der SiC Saatkristallsubstratoberfläche durch Sublimation ausgeführt wird.
  2. Aluminiumnitridkristallherstellungsverfahren nach Anspruch 1, das weiterhin umfasst:
    einen Schritt des Wachsens des Aluminiumnitridkristalls auf die Oberfläche des herausgenommenen Aluminiumnitridkristalls.
  3. Aluminiumnitridkristall mit einer Vorderseite, dessen Oberflächenfläche 10 cm2 oder mehr ist bei einer Versetzungsdichte im Aluminiumnitridkristall zwischen 1 x 103 Versetzungen/cm2 und einschließlich 1 x 106 Versetzungen/cm2, und der mindestens einen Versetzungstyp einschließt, der aus der Gruppe ausgewählt wird, die aus Schraubenversetzungen, Randversetzungen und gemischte Versetzungen besteht, wobei das Verhältnis der Versetzungsdichte von Schraubenversetzungen zur Versetzungsdichte 0,2 oder weniger ist.
  4. Aluminiumnitridkristall nach Anspruch 3, dadurch gekennzeichnet, dass die Versetzungsdichte zwischen 2 x 104 Versetzungen/cm2 und einschließlich 5 x 105 Versetzungen/cm2 ist.
  5. Aluminiumnitridkristall, nach Anspruch 3, dadurch gekennzeichnet, dass die Versetzungsdichte von Schraubenversetzungen 1 x 104 Versetzungen/cm2 oder weniger ist.
  6. Aluminiumnitridkristallsubstrat, das aus dem Aluminiumnitridkristall gemäß einem der Ansprüche 3 bis 5 gebildet wird.
  7. Halbleitervorrichtung, das unter Verwendung des Aluminiumnitridkristallsubstrats gemäß Anspruch 6 verwendet wird.
EP07706498.8A 2006-01-12 2007-01-10 Verfahren zur herstellung von aluminiumnitridkristall, aluminiumnitridkristall, aluminiumnitridkristallsubstrat und halbleiterbauelement Expired - Fee Related EP1972702B1 (de)

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JP2006005062 2006-01-12
PCT/JP2007/050151 WO2007080881A1 (ja) 2006-01-12 2007-01-10 窒化アルミニウム結晶の製造方法、窒化アルミニウム結晶、窒化アルミニウム結晶基板および半導体デバイス

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EP1972702A1 EP1972702A1 (de) 2008-09-24
EP1972702A4 EP1972702A4 (de) 2010-08-11
EP1972702B1 true EP1972702B1 (de) 2013-09-25

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US (1) US20090087645A1 (de)
EP (1) EP1972702B1 (de)
KR (1) KR101404270B1 (de)
CN (1) CN101370972B (de)
WO (1) WO2007080881A1 (de)

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JP5303941B2 (ja) * 2008-01-31 2013-10-02 住友電気工業株式会社 ＡｌｘＧａ１−ｘＮ単結晶の成長方法
JP5461859B2 (ja) * 2008-03-28 2014-04-02 Ｊｆｅミネラル株式会社 ＡｌＮバルク単結晶及び半導体デバイス並びにＡｌＮ単結晶バルクの製造方法
JP2011246315A (ja) * 2010-05-28 2011-12-08 Sumitomo Electric Ind Ltd 炭化珪素基板およびその製造方法
CN102140680A (zh) * 2011-05-10 2011-08-03 青岛铝镓光电半导体有限公司 氮化镓单晶的制备方法
US9419181B2 (en) * 2013-05-13 2016-08-16 Infineon Technologies Dresden Gmbh Electrode, an electronic device, and a method for manufacturing an optoelectronic device
JP6434367B2 (ja) * 2015-05-14 2018-12-05 東京エレクトロン株式会社 基板液処理装置及び基板液処理方法並びに基板液処理プログラムを記憶したコンピュータ読み取り可能な記憶媒体
CN105483833A (zh) * 2015-11-24 2016-04-13 北京华进创威电子有限公司 一种氮化铝单晶的位错腐蚀方法
CN108642561B (zh) * 2018-07-06 2021-01-05 中国电子科技集团公司第四十六研究所 一种在氮化铝单晶的生长中保护籽晶表面的方法
KR102122668B1 (ko) 2018-12-12 2020-06-12 에스케이씨 주식회사 잉곳의 제조장치 및 이를 이용한 탄화규소 잉곳의 제조방법
CN110886018A (zh) * 2019-12-03 2020-03-17 中国电子科技集团公司第四十六研究所 一种大尺寸高质量氮化铝单晶的生长方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2852974A1 (fr) * 2003-03-31 2004-10-01 Soitec Silicon On Insulator Procede de fabrication de cristaux monocristallins

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5858086A (en) * 1996-10-17 1999-01-12 Hunter; Charles Eric Growth of bulk single crystals of aluminum nitride
US7501023B2 (en) * 2001-07-06 2009-03-10 Technologies And Devices, International, Inc. Method and apparatus for fabricating crack-free Group III nitride semiconductor materials
JP4089398B2 (ja) 2002-03-14 2008-05-28 住友金属工業株式会社 ＡｌＮ単結晶の製造方法
US7323256B2 (en) * 2003-11-13 2008-01-29 Cree, Inc. Large area, uniformly low dislocation density GaN substrate and process for making the same
JP2005343722A (ja) * 2004-06-01 2005-12-15 Sumitomo Electric Ind Ltd ＡｌＮ結晶の成長方法、ＡｌＮ結晶基板および半導体デバイス

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2852974A1 (fr) * 2003-03-31 2004-10-01 Soitec Silicon On Insulator Procede de fabrication de cristaux monocristallins

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EP1972702A4 (de) 2010-08-11
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CN101370972B (zh) 2012-09-26
US20090087645A1 (en) 2009-04-02

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