EP1958232A1 - Système à plasma à pression moyenne pour le retrait de couches de surface sans perte de substrat - Google Patents

Système à plasma à pression moyenne pour le retrait de couches de surface sans perte de substrat

Info

Publication number
EP1958232A1
EP1958232A1 EP05853311A EP05853311A EP1958232A1 EP 1958232 A1 EP1958232 A1 EP 1958232A1 EP 05853311 A EP05853311 A EP 05853311A EP 05853311 A EP05853311 A EP 05853311A EP 1958232 A1 EP1958232 A1 EP 1958232A1
Authority
EP
European Patent Office
Prior art keywords
wafer
plasma
chuck
discharge tube
recited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05853311A
Other languages
German (de)
English (en)
Inventor
John Wolfe
Aseem Srivastava
Ivan Berry
Palani Sakthivel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Houston
Axcelis Technologies Inc
Original Assignee
University of Houston
Axcelis Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Houston, Axcelis Technologies Inc filed Critical University of Houston
Publication of EP1958232A1 publication Critical patent/EP1958232A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32733—Means for moving the material to be treated
    • H01J37/32752—Means for moving the material to be treated for moving the material across the discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H01J2237/3343—Problems associated with etching
    • H01J2237/3346—Selectivity

Definitions

  • the present invention relates in general to semiconductor processing, and in particular, to the selective removal of surface layers from a workpiece, as for example, a semiconductor wafer in the manufacture of integrated circuits. It will be understood that while the following discussion is directed to semiconductor manufacturing proceses, the present invention may apply to various manufacturing processes and apparatus therefore such that the present invention shall not be limited to semiconductor manufacturing.
  • Photoresist masks define every layer of an integrated circuit (IC), from front-end- of-line (FEOL) ion implantation for isolation, P-or N- well doping, threshold voltage adjustment and source-drain contacts to back-end-of-line (BEOL) plasma etching or plating of metal and etching of interlevel dielectrics. These coatings must be removed efficiently and completely after each level in the semiconductor device is formed, hi this context, resist removal may be variously described as resist ashing, stripping or etching.
  • IC integrated circuit
  • FEOL front-end- of-line
  • BEOL back-end-of-line
  • etching is used universally to refer to ashing, stripping or etching, and, where appropriate, may refer to various other processes where removal of a surface layer is implied.
  • a normally non-reactive gas such as O 2
  • flows through a microwave or radio-frequency discharge where it is transformed into a plasma, defined as a mixture of excited molecules, radicals, ions, and electrons.
  • the charged species in the plasma may recombine as they flow through a downstream distribution system.
  • many radicals may have sufficient lifetimes to reach the wafer.
  • the present description provides a novel plasma source never before used in semiconductor manufacturing processes, based on surface waveguide discharge technology.
  • Previous implementation of plasma systems have employed a source of electromagnetic power to activate a plasma gas, such as the Surfaguide device developed by Moisson et al., (Moisson et al, IEEE Trans. Plasma Sci., PS-12, 203-214, 1984).
  • the limited cooling efficiency of this apparatus effectively limited the power densities of the resulting plasma.
  • oil-cooled plasma sources have commonly been implemented.
  • operating a plasma at high energy involves very high temperatures. Cooling oil decomposes under these conditions, depositing a carbonized layer on the outside wall of the plasma discharge tube within the waveguide.
  • the wafers are heated to enhance the reaction rate during downstream plasma ashing.
  • the application time in conventional processes for an unimplanted resist layer may be as low as 15 seconds at 27O 0 C for O 2 -based plasma chemistry.
  • the process throughput is further reduced because the wafer temperature must be kept below about 12O 0 C to prevent the ejection of particulates, which may occur when the crust explodes under the pressure of gas, mainly NH 3 , that is evolved in response to heating above the hardbake temperature. This phenomena is known as popping, (D. Fleming et al, Manufacturing Improvements Realized through an Optimized pre-Implant UV/Bake Process, Future Fab International, 4,1, 1977, p 177).
  • Ion implanted resist films unlike graphite or photoresist, are essentially inert; they do not adsorb atmospheric oxygen, nitrogen, or water vapor.
  • the present invention addresses the foregoing needs by providing a new approach for removing surface layers from semiconductor wafers.
  • the present invention provides a method wherein reactant gases are activated by a medium pressure surface wave discharge.
  • the method further involves the formation of volatile reactants in the plasma gas that can strip photoresist from the surface of a wafer.
  • the plasma gas forms a reactive plasma jet that impinges on a substrate from which surface layers may be selectively, thus safely, etched with high efficiency.
  • the method may be practiced in a commerically viable manner for stripping applied materials from large wafers by scanning them in front of the j et.
  • the present invention can be characterized generally as an apparatus for selectively removing surface layers from a workpiece in a manufacturing process, wherein the apparatus comprises: a process chamber; a plama applicator; and a cooling system.
  • the process chamber defines a subatmospheric environment for receiving the workpiece to be processed such that a surface layer can be removed.
  • the plasma applicator generates a plasma and includes a pressurized supply of reactant process gas, a plasma discharge tube in fluid communication with the pressurized supply of reactant process gas, an electromagnetic power source for directing electromagnetic power to the plasma discharge tube to generate a plasma therein, and a nozzle opening situated at an end of the plasma discharge tube for jetting the plasma gas into the process chamber in a direction toward the workpiece.
  • the cooling system includes a conduit substantially surrounding the plasma discharge tube for circulating a gaseous coolant therethrough, thereby forming a cooling channel around the plasma discharge tube.
  • the apparatus provides a system wherein reactant gases, such as O 2 , H 2 , H 2 O, N 2 , etc., may flow through a narrow discharge tube made of quartz , sapphire or other electromagnetic insensitive material, and wherein surface wave activation by an electromagnetic power source, such as a microwave or RF power source, may be applied.
  • reactant gases such as O 2 , H 2 , H 2 O, N 2 , etc.
  • an electromagnetic power source such as a microwave or RF power source
  • a cooling system for the discharge tube using a gaseous coolant is provided, further comprising an integral cooling flange on the discharge tube, which may be attached to a cooling channel.
  • the apparatus may further comprise a discharge nozzle from which the gas emerges from the tube and impinges on a substrate, such that resultant volatile reaction products, such as H 2 O, CO 2 , or low molecular weight hydrocarbons, may selectively strip material layers from the surface of a substrate wafer.
  • the apparatus may further comprise a positioning system for supporting a wafer chuck, that provides wafer heating and positioning, and provides for high speed scanning of a wafer with the plasma source.
  • the use of surface wave discharges has the unique advantage of being able to guide the discharge from the point where excitation power is applied, to the wafer where it is used. Also, the method of providing a surface wave discharge may be practiced over a wide range of pressure without significant changes to the electromagnetic power system.
  • the ideal operating pressure range of the present invention is in the medium pressure regime (greater than about 10 Torr, but less than about 500 Torr).
  • Medium pressure plasmas have the advantage that very high rates of electron-ion recombination and energetic particle thermalization may eliminate the high energy charged species present in low pressure plasmas. Eliminating these high energy species eliminates the possibility of potentially damaging substrate currents and sputter erosion.
  • plasma gas temperatures in the medium pressure regime are extremely high compared to low pressure plasmas. Higher plasma gas temperatures provide an additional source of heat in the reactive zone on the wafer, specifically there where it is most required. This focused thermal energy positively contributes to the reactive removal of organic material, wherein the reaction rate of material removal is increased, thereby increasing the speed (and so the commercial viability) of the process.
  • the use of low pressures (less than about 10 Torr) for this plasma jet system may not be desirable because, as pressure decreases, the geometry of the plasma jet may flare out, thereby making the "spot size" less controllable.
  • the use of high pressures (greater than about 500 Torr) may not be advantageous because the reactive species needed for surface removal may recombine before reaching the wafer, thus reducing the effectiveness of the plasma for highly selective removal. Operation of the present invention over a wide pressure window may, however, enable atmospheric wafer exchange while the plasma source is still operating. Since ignition of the plasma normally requires low pressure (close to IT), cycling the process pressure may be avoided if the power source can be maintained during wafer exchange at about 760 Torr (atmospheric pressure). This may avoid additionally having to vaccum pump down to low pressure for plasma ignition, and then repressurizing to medium pressure for processing each semicondutor wafer, thereby further saving valuable process time in an industrial setting.
  • FIGURE 1 illustrates a cross-sectional diagram of a plasma removal system in an embodiment of the present invention
  • FIGURE 2 is a photograph of an operating plasma removal system in an embodiment of the present invention
  • FIGURES 3-7 illustrate empirical data collected on embodiments of the present invention
  • FIGURE 8 schematically illustrates a scanning pattern in an embodiment of the present invention
  • FIGURE 9 schematically illustrates heat flow in an embodiment of the present invention
  • FIGURES 10-17 are photomicrographs of samples treated using embodiments of the present invention.
  • FIGURES 18-19 illustrate method steps in flowchart form of embodiments of the present invention.
  • FIGURE 1 illustrates a schematic representation of the plasma applicator 101, process chamber 102, and high speed wafer scanning stage 103.
  • the plasma applicator 101 may be mounted on the chamber wall 104 of a semiconductor process tool, comprising a process chamber 102, wherein the chamber defines a subatmospheric environment for processing the wafer or any other workpiece wherein surface layer removal is desired.
  • An electromagnetic power supply feeds power 105 to a plasma discharge tube 106 through a thin- walled coupling aperture 110 in a reduced height section of waveguide 111.
  • microwave power at 2.45 GHz is applied to a 6 mm diameter quartz plasma discharge tube.
  • a plasma jet refers to the stream of pressurized plasma gas that emerges from the plasma applicator 101.
  • the plasma jet causes the activated process gases to impinge on a semiconductor wafer 2 mm distant. In another example, the wafer is as much as about 20 mm from the plasma jet.
  • the high speed wafer scanning stage comprises a chuck 130 with a wafer holder which clamps the wafer.
  • the wafer holder may be operated with the force of vacuum, chamber pressure, or electrostatically.
  • the wafer holder may contact the wafer with a thermally conducting or insulating material, depending on the degree of contact conductance desired with the wafer, hi one example, an insulating material layer is introduced between the wafer and the wafer holder to reduce thermal contact conductance, thereby increasing the wafer temperature by hindering dissipation of heat.
  • a conducting material layer is introduced between the wafer and the wafer holder to increase thermal contact conductance, thereby decreasing the wafer temperature by promoting dissipation of heat.
  • the chuck 130 may be connected to a power supply via coupling 133 for heating the wafer, or to an active cooling supply via coupling 132, such as water, for cooling the wafer.
  • the chuck may also be equipped with a thermocouple sensor via coupling 135 or other temperature sensor for monitoring the chuck temperature.
  • the chuck and wafer holder may be mounted on a mechanical positioning system for scanning the wafer, hi this, regard, scanning the wafer refers to dynamicaly positioning the wafer while being impinged by the plasma jet, so as to expose a region of the wafer to the plasma treatment.
  • the exposure by scanning may be uniform over an entire region on the wafer, or may involve selectively treating sections of the wafer to a differing level of exposure to the plasma.
  • a dual axis orthogonal positioning system comprising an x-axis linear drive 136 and a y-axis linear drive 134, is illustrated in an example embodiment.
  • the mechanical positioning system comprises two orthogonal, motor driven, translation stages with accelerations exceeding 2.5 times the acceleration of gravity and scanning speeds greater than 100 cm/s.
  • the present invention may execute a scanning pattern under computer control so that each point of the wafer passes within the footprint of the jet, said footprint having a diameter equal to about the full-width-at-half- maximum of a lateral plasma jet profile of the etched track.
  • the present invention may execute a scanning pattern under computer control providing lower scanning rates on the edge of the wafer to increase wafer temperature and compensate for reduced etch rates due to edge effects.
  • the present invention employs a cooling system using a gaseous coolant.
  • a high velocity gas flowing in a direction 113 opposite the plasma gas 114 is used to cool the plasma discharge tube, whereby operation of the plasma applicator 101 at much higher power dissipation is made possible, hi one example, a dry air or nitrogen coolant gas, confined by a concentric outer tube 116, cools the plasma discharge tube 106.
  • the plasma discharge tube 106 incorporates an integral base flange 118 to facilitate mounting to the applicator body.
  • An important function of the base flange 118 is to displace the O-ring seals 140 from the immediate vicinity of the plasma discharge tube 106, which may be extremely hot.
  • the O-ring seals 140 have a relatively low melting point and may easily be destroyed by excessive thermal loading. O-rings in direct contact with the downstream side of the plasma discharge tube 106 would inevitably melt.
  • the construction and design of the cooling system of the present invention provides for a large enough temperature gradient across the a base flange 118, such that the hot plasma emerging from the center nozzle 119 of base flange 118 does not cause deterioration of the O-ring seals 140 on the edge of base flange 118.
  • an aluminum spacer 142 separates the discharge tube flange 118 from a corresponding cooling flange 117 on an outer cooling conduit 116.
  • the embodiment of the present invention depicted in FIGURE 1 relies upon a concentric circular, coaxial cross-sectional geometry of the cooling system.
  • Other cross-sectional geometries of a plasma discharge tube surrounded by a cooling conduit, such as rectangular, square, oval, or eccentric arrangements may be practiced within the scope of the present invention.
  • Various cooling systems employing liquid or gaseous coolants, providing the same cooling performance, so as to enable the power regimes practiced in the present invention, may also be implemented in embodiments of the present invention.
  • the present invention may further comprise a trap 120 incorporated below the flange of the inner tube so as to eliminate leakage of electromagnetic power into the processing chamber.
  • a 1 A ⁇ transformer based microwave trap is employed.
  • the gaseous coolant may flow radially inward through channels in the lower surface of the trap 120 toward the plasma discharge tube 106 and enter the narrowed space 105 between the plasma discharge tube and the outer cooling conduit 116.
  • the velocity of the coolant gas increases substantially as it enters this region, as the flow cross-section is reduced.
  • the result is a signficantly enhanced cooling of the plasma discharge tube 106, particularly in the extremely hot zone within the waveguide 110.
  • a 1 mm wide gap between the plasma discharge tube and the cooling conduit results in coolant gas velocities approaching Mach 1, whereby high microwave power levels near 2.5 kW may be sustained on a continuous basis.
  • the air cooling of the present invention does not leave deposits on the discharge tube and does not cause damage to the plasma discharge tube, even after extended, continuous operation of the plasma j et at high power levels.
  • FIGURE 2 is a photograph of an operating plasma removal system in an embodiment of the present invention.
  • the visible plasma jet is about 20 cm in length and is luminous.
  • the process gas used in the example embodiment shown in FIGURE 2 is a reactive O 2 :N 2 mixture at a ratio of about 9:1, wherein a pressure of about 80 Torr was supplied at a flow rate of about 2 slpm.
  • the electromagnetic discharge power is about 1 kW.
  • the thermal power of the plasma jet provides the ability to heat the wafer locally, thus increasing etch rates by increasing reaction rates, while simultaneously delivering reactive species to feed the etching reaction of organic surface layers.
  • the total thermal power P delivered to the substrate from the impinging plasma jet was determined by measuring the rate of temperature T rise vs. time t, dT/dt, of a thermally isolated aluminum block placed under the jet by the following equation:
  • FIGURE 3 shows temperature versus time for a thermally isolated aluminum block.
  • the graph in FIGURE 3 shows a linear relationship between temperature and time, whereby dT/dt is the slope of the line.
  • FIGURE 4 illustrates a data plot of measurements of plasma jet power versus applied microwave power under the otherwise same process conditions for the example as in FIGURE 3.
  • plasma jet power depends linearly on microwave power, hi this example, the conversion efficiency is about 19 % and 21%, as measured by the slope of the linear interpolation of the measured data points, when the target (the semiconductor wafer) is 0.9 cm and 2.9 cm away, respectively, from the plasma source, measured from nozzle opening 119.
  • FIGURE 5 illustrates a data plot of measurements of plasma jet power versus distance from the plasma source under the otherwise same process conditions for the example as in FIGURE 3.
  • the jet power decreases as the distance from the source is increased from about 1 cm to about 5 cm. This may be a result of cooling of the plasma jet by mixing with the ambient temperature gas in the process chamber 102.
  • FIGURE 6 illustrates a data plot of measurements of plasma jet power versus concentration of O 2 , at a target distance of 2.9 cm from the plasma source, under the otherwise same process conditions for the example as in FIGURE 3.
  • FIGURE 6 shows a relatively constant of plasma jet power over an O 2 concentration of about 20% to about 90%. This result shows that plasma jet power is essentially independent of O 2 /N 2 gas composition.
  • FIGURE 7 illustrates a data plot of measurements of contact conductance versus the space between the wafer and the chuck.
  • the ability to control wafer temperature under the dynamic conditions during scanning by a plasma jet may determine the success of an ashing process.
  • Controlling wafer temperature is constrained by the thermal contact conductance (K) between the wafer and the chuck.
  • K thermal contact conductance
  • the values for K were measured for various gaps between the wafer and the chuck, by determining the steady state temperature of an aluminum block mounted on a constant temperature chuck. The spacing between block and chuck was maintained with thin mica spacers.
  • K is given by the following formula:
  • K A (T- T 0 ) ZP
  • A the area of contact between the block and the chuck
  • T 0 the chuck temperature
  • P the power.
  • the time constant ⁇ for heat transfer between the chuck and the wafer is given by:
  • X CIK
  • C the heat capacity of the wafer per unit area.
  • This time constant is about 2 seconds for a 300 mm silicon wafer in intimate contact with the chuck, increasing to about 10 seconds for a 0.01" gap.
  • the strong variation of contact conductance, and hence time constant, requires very precise gap control, implying the need for electrostatic or vacuum clamping of the wafer on the chuck.
  • Another benefit of the present invention operable in the medium pressure regime, over conventional low pressure systems is the ability to allow the use of vacuum clamping of the wafer on the chuck instead of requiring electrostatic clamping.
  • the wafer may be scanned in a serpentine raster pattern 1014 as shown in FIGURE 8.
  • line scans 1014 along the x-axis 1010 are alternated in each direction between short translations, i.e. track spacings, along the y-axis 1012, relative to the semiconducting wafer 1016.
  • the track spacing may be less than the diameter of the jet to provide a uniform etch profile across the wafer.
  • the track spacing was set to 0.7 cm. With a track spacing of 0.7 cm, the variation in etch depth between the track centers and the midpoints between the tracks is less than 2% of the initial resist thickness.
  • the plasma jet 1521 is scanned over a semiconductor wafer substrate 1530 that is coated with a surface layer of organic resist 1531.
  • the plasma jet 1521 emerging from the plasma source 1520 with high energy under medium pressure in the direction 1523 of the wafer 1530, creates a heated track 1522 that cools laterally by heat conduction through the wafer and vertically through the contact conductance to the wafer holder, i.e., the chuck.
  • the relevant thermal fluxes, Fj ate rai 1524 and F vert j ca i 1526 correspond to lateral heat flow and vertical conduction, respectively.
  • the chuck may be heated to increase resist etch rates on the wafer.
  • the chuck may also dissipate the excess heat imparted by the plasma jet.
  • the heat of the jet diffuses rapidly through the wafer, the diffusion length corresponding to the dwell time of the jet being greater than the wafer thickness for even the highest scanning speeds.
  • the lateral diffusion length is only 0.5 cm during a track scan time of about 0.2-0.4 seconds, increasing the width of the heated zone by about 50%.
  • the high speed scanning may be understood as the thermodynamic equivalent of a line heater moving across the wafer in the y-direction 1510, perpendicular to the high-speed scanning direction, hi one example, vertical heat flow is a slow process with a 2-10 second time constant for a silicon substrate, and is negligible during the time required to scan a single track. There may be instances, however, where vertical heat flow becomes an important thermal factor after several tracks have been scanned.
  • jet power may determine the effectiveness of a particular ashing process.
  • embodiments of the present invention are operated using a high level of electromagnetic power to activate the plasma jet, which translates directly into a higher etch rate. Increased power also maximizes the generation of reactive gases in the plasma and provides the heat for activating the ashing reaction between the resist and etching gas.
  • the initial chuck temperature may be set just below the hardbake temperature of the resist, hi one example, the initial chuck temperature is set to about 10 0 C below the resist hardbake temperature, which may be about 125 0 C.
  • the resist would be stable at this temperature and no popping should occur.
  • Contact conductance between the wafer and chuck may be maximized, for example, with helium backside cooling to minimize wafer temperature for a given input power density.
  • the scanning speed may be increased, thereby reducing effective power density in the wafer, to the point where the wafer can be scanned indefinitely without popping.
  • the required speed may be significantly greater than 1 m/s.
  • the wafer temperature gradually rises and the scanning plasma jet creates minute holes in the implanted photoresist crust, making the crust permeable to the gases released from the base resist.
  • the temperature may be allowed to rise by reducing the scanning speed or by reducing the contact conductance between the wafer holder and the chuck, thereby reducing the amount of heat dissipated through the wafer holder.
  • the result of the pre-scanning process for permeating the photoresist crust may be a rapid removal of the resist from the wafer surface during a secondary scanning operation.
  • Etching unimplanted resist involves fewer thermal constraints; the initial chuck temperature may be higher, in one example around 200-350 0 C, and contact conductance and scan speed may be set to be much lower, all leading to higher wafer temperatures and, thus, higher etch rates, hi the case of unimplanted resist, contact conductance could be reduced significantly.
  • the wafer may be raised off the chuck by a few ten thousands of an inch.
  • the ashing of high-dose, ion-implanted photoresist may occur as a two-step process in which the crust is first rendered permeable by a low temperature pretreatment process followed by a high temperature resist removal process.
  • the pretreatment process may take place with chuck temperatures below the bake temperature of the resist, in one instance 120 0 C. This relatively low temperature is required for preventing the ejection of particulates when the crust explodes due to gases evolved by thermal decomposition of the resist in the event that the carbonized crust has not been removed/punctured, a process also known as popping.
  • the temperature of the wafer may be safely raised to enhance the rate of resist removal. Measurements have established and verified the conditions of pretreatment and resist removal in scanned plasma jet ashing of heavily implanted (P, 40 keV, 5 x 1015/cm2) I-line photoresist from silicon wafers .
  • FIGURES 10-17 are photomicrographs of sample semiconductor wafers, having a surface layer of photoresist, treated by embodiments of the present invention.
  • FIGURE 10 shows a network of fine gas-filled blisters formed by the heat of a 1 kW plasma jet at 15 cm/s.
  • a blister fractured when the substrate was cleaved, showing that the pressure of the evolved gas has delaminated the crust from the underlying unimplanted resist base.
  • the height of the blisters is 3-4 times the original resist thickness.
  • This blistering effect is related to, but distinct from, the popping phenomenon, whereby large plates of crust are blown off the surface. Blistering, however, may be acceptable in instances whereby no particulate debris is generated.
  • FIGURE 12 shows a later stage of etching where most of the crust 2011 has been removed and blisters 2010 have merged.
  • the plasma jet may be operated at the maximum possible elecromagnetic power that can be applied.
  • it may be then necessary to scan the jet fast enough prevent excessive temperature rise.
  • multiple pretreatment scans may be required to achieve sufficient permeability to prevent popping during the resist removal step.
  • resist can be removed completely in a single scan at a speed on the order of 50-100 cm/s without changing the substrate temperature.
  • Other settings for process parameters may be used to achieve similar results in differing, but related, embodiments of the present invention.
  • FIGURE 15 shows a reticulated resist surface that may develop during the early stages of the pretreatment process. This surface becomes permeable, as shown in FIGURE 16, in the late stages of the pretreatment step.
  • I-line photoresist 1.2 microns I-line base resist, hardbaked at 120 0 C, then implanted with phosphorus at an energy of 40keV, and at a heavy implantation density of 5 x 10 15 /cm 2
  • This pretreatment was followed by subsequent resist removal scans at 2.5kW, and 40cm/s (whereas the other conditions were kept the same as the pretreatment). All crust and base resist was removed off the wafer, and no residue was seen under the scanning electron microscope, as evident in FIGURE 17.
  • FIGURE 18 illustrates a method 2401 for practicing the present invention in flowchart form.
  • the method may begin with step 2402 of introducing the wafer into a process chamber equipped with a plasma applicator apparatus, as described in FIGURE 1. If the plasma has previously been ignited at low temperature, step 2402 may be performed while the plasma is activated at ambient pressure.
  • the clamping interface between the wafer and the wafer holder may be adjusted for the desired thermal conductivity, either for high or low conductance, hi step 2406 the semiconductor wafer may be clamped into the chuck, using an atmospheric or vacuum force, or electrostatically, hi step 2408 operation of the cooling system, as previously described, for cooling the plasma discharge tube may be initiated.
  • the activation of the reactant process gas may be initiated in step 2410.
  • the wafer surface may be treated by the impinging plasma jet in step 2412.
  • the wafer may be scanned by the plasma jet beam in step 2414.
  • the method 2401 is illustrative of one embodiment of the present invention and may be equally practiced with various combinations of the illustrated process steps, with omission of certain steps, or in a different order of the given, depending on process and equipment requirements.
  • a pretreatment of an ion implanted resist is performed for rendering the resist crust permeable to gases.
  • unimplanted or pretreated ion implanted resist is treated for selective ashing and removal of the photoresist layer only.
  • FIGURE 19 illustrates one exemplary method 2501 for practicing the method step 2410 shown in FIGURE 18.
  • First an electromagnetic power source as previously described, may be activated in step 2502.
  • the electromagnetic radiation is transmitted through a waveguide to a plasma discharge tube in step 2504.
  • hi step 2506, electromagnetic power is contained in a trap for protecting the wafer from uncontrolled radiation.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

La présente invention concerne un système et un procédé pour retirer des résines photosensibles ou d’autres composés organiques de plaquettes semi-conductrices. Des gaz réactifs non fluorés (O2, H2, H2O, N2 entre autres) sont activés dans un tube de quartz par une décharge d’onde de surface à pression moyenne. Lorsque le jet de plasma frappe un substrat, les produits de réaction volatils (H2O, CO2, ou hydrocarbures à faible poids moléculaire) retirent sélectivement la résine photosensible de la surface. La pression moyenne permet également des températures de gaz élevées qui servent de source de chaleur efficace dans la zone réactive de la plaquette ce qui améliore les vitesses de gravure et permet d’obtenir un moyen pratique pour retirer une résine photosensible implantée d’ions.
EP05853311A 2005-12-07 2005-12-07 Système à plasma à pression moyenne pour le retrait de couches de surface sans perte de substrat Withdrawn EP1958232A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2005/044367 WO2007067177A1 (fr) 2005-12-07 2005-12-07 Système à plasma à pression moyenne pour le retrait de couches de surface sans perte de substrat

Publications (1)

Publication Number Publication Date
EP1958232A1 true EP1958232A1 (fr) 2008-08-20

Family

ID=35966034

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05853311A Withdrawn EP1958232A1 (fr) 2005-12-07 2005-12-07 Système à plasma à pression moyenne pour le retrait de couches de surface sans perte de substrat

Country Status (4)

Country Link
EP (1) EP1958232A1 (fr)
JP (1) JP2009518854A (fr)
CN (1) CN101326613B (fr)
WO (1) WO2007067177A1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102637633B (zh) * 2011-06-17 2015-08-12 京东方科技集团股份有限公司 一种阵列基板制造方法及系统
CN104040710B (zh) 2012-01-06 2017-11-28 诺发系统公司 用于均匀传热的自适应传热方法和系统
US10347547B2 (en) 2016-08-09 2019-07-09 Lam Research Corporation Suppressing interfacial reactions by varying the wafer temperature throughout deposition
US11694911B2 (en) * 2016-12-20 2023-07-04 Lam Research Corporation Systems and methods for metastable activated radical selective strip and etch using dual plenum showerhead

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59108883D1 (de) * 1990-09-07 1997-12-11 Sulzer Metco Ag Apparatur zur plasmathermischen Bearbeitung von Werkstückoberflächen
JP3180092B2 (ja) * 1997-12-03 2001-06-25 松下電工株式会社 プラズマ処理システム及びプラズマ処理方法
KR100263902B1 (ko) * 1998-04-20 2000-09-01 윤종용 표면 파 플라즈마 식각장치
JP2000036488A (ja) * 1998-07-21 2000-02-02 Speedfam-Ipec Co Ltd ウエハ平坦化方法及びそのシステム
JP2000124189A (ja) * 1998-10-21 2000-04-28 Speedfam-Ipec Co Ltd 局所エッチング装置及び局所エッチング方法
US6429142B1 (en) * 1999-02-23 2002-08-06 Taiwan Semiconductor Manufacturing Company In-situ photoresist removal by an attachable chamber with light source
JP4294816B2 (ja) * 1999-11-11 2009-07-15 スピードファム株式会社 シリコンウエハの表面処理方法，無臭シリコンウエハ製造方法，シリコンウエハの酸化膜形成方法，酸化シリコンウエハ製造方法，酸素活性種雰囲気形成装置，及び平坦化処理システム
US6534921B1 (en) * 2000-11-09 2003-03-18 Samsung Electronics Co., Ltd. Method for removing residual metal-containing polymer material and ion implanted photoresist in atmospheric downstream plasma jet system
JP2003109941A (ja) * 2001-09-28 2003-04-11 Canon Inc プラズマ処理装置および表面処理方法
US7183514B2 (en) * 2003-01-30 2007-02-27 Axcelis Technologies, Inc. Helix coupled remote plasma source
US8580076B2 (en) * 2003-05-22 2013-11-12 Lam Research Corporation Plasma apparatus, gas distribution assembly for a plasma apparatus and processes therewith
US7892357B2 (en) * 2004-01-12 2011-02-22 Axcelis Technologies, Inc. Gas distribution plate assembly for plasma reactors
JP4278533B2 (ja) * 2004-02-19 2009-06-17 芝浦メカトロニクス株式会社 アッシング方法及びアッシング装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2007067177A1 *

Also Published As

Publication number Publication date
JP2009518854A (ja) 2009-05-07
CN101326613A (zh) 2008-12-17
WO2007067177A1 (fr) 2007-06-14
CN101326613B (zh) 2010-12-08

Similar Documents

Publication Publication Date Title
US20070228008A1 (en) Medium pressure plasma system for removal of surface layers without substrate loss
US9443701B2 (en) Etching method
US5330606A (en) Plasma source for etching
TWI415186B (zh) 自基材移除氟化聚合物的設備與方法
JP5690596B2 (ja) フォーカスリング及び該フォーカスリングを備える基板処理装置
EP0383570A2 (fr) Procédé et appareil pour corroder du plasma
KR970077302A (ko) 플라즈마 처리 장치
JPH02224236A (ja) 集積回路デバイスを製造するための装置
US10192750B2 (en) Plasma processing method
JP6465442B2 (ja) プラズマ処理装置
EP0497563A2 (fr) Méthode de traitement de surface utilisant des particules chargées ou non chargées et appareillage de mise en oeuvre de cette méthode
WO1998014036A9 (fr) Depouillage au fluor et elimination de residu dans un calcinateur avec tube de plasma en saphir pour traitement en aval
EP1958232A1 (fr) Système à plasma à pression moyenne pour le retrait de couches de surface sans perte de substrat
US4827137A (en) Soft vacuum electron beam patterning apparatus and process
JPH1074600A (ja) プラズマ処理装置
KR100218836B1 (ko) 플라스마 처리장치
JP6043968B2 (ja) プラズマ処理方法並びに電子デバイスの製造方法
JPH05102083A (ja) ドライエツチング方法及びそのための装置
Pu Plasma Etch Equipment
KR20090012305A (ko) 기판 손실 없이 표면 층을 제거하기 위한 중간 압력플라즈마 시스템
JPH06104098A (ja) マイクロ波プラズマ処理装置
JP2000114207A (ja) 微細加工方法及び装置
JP2007235138A (ja) 大きい深さ対幅アスペクト比をもつホールからポリマーを制御下にかつ急速に除去するための大気内プロセスおよびシステム
JPH05275376A (ja) ドライエッチング装置およびドライエッチング方法
JPH10106798A (ja) 高速原子線源

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20080703

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR IT

RIN1 Information on inventor provided before grant (corrected)

Inventor name: WOLFE, JOHN

Inventor name: SRIVASTAVA, ASEEM

Inventor name: SAKTHIVEL, PALANI

Inventor name: BERRY, IVAN

RBV Designated contracting states (corrected)

Designated state(s): DE FR IT

17Q First examination report despatched

Effective date: 20090824

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20100105