EP1920518A1 - Dispositif et procede d'equilibrage de charge entre les cellules individuelles d'un condensateur a double couche - Google Patents

Dispositif et procede d'equilibrage de charge entre les cellules individuelles d'un condensateur a double couche

Info

Publication number
EP1920518A1
EP1920518A1 EP06793147A EP06793147A EP1920518A1 EP 1920518 A1 EP1920518 A1 EP 1920518A1 EP 06793147 A EP06793147 A EP 06793147A EP 06793147 A EP06793147 A EP 06793147A EP 1920518 A1 EP1920518 A1 EP 1920518A1
Authority
EP
European Patent Office
Prior art keywords
cell
voltage
switching transistors
tia
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP06793147A
Other languages
German (de)
English (en)
Inventor
Stephan Bolz
Martin GÖTZENBERGER
Rainer Knorr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Continental Automotive GmbH
Original Assignee
Siemens AG
Continental Automotive GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Continental Automotive GmbH filed Critical Siemens AG
Publication of EP1920518A1 publication Critical patent/EP1920518A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0014—Circuits for equalisation of charge between batteries
    • H02J7/0016—Circuits for equalisation of charge between batteries using shunting, discharge or bypass circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/396—Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/60—Other road transportation technologies with climate change mitigation effect
    • Y02T10/70—Energy storage systems for electromobility, e.g. batteries

Definitions

  • the invention relates to a device for charge equalization between the individual cells of a double-layer capacitor, in particular in a multi-voltage vehicle electrical system.
  • the invention also relates to a method for operating this device.
  • Double-layer capacitors have proved to be the most sensible technical solution for providing or storing short-term high powers, such as acceleration support by means of an electric motor (boost mode) or the electrical conversion of kinetic energy during regenerative braking in so-called “mild” hybrid vehicles.
  • the maximum voltage of a double-layer capacitor single cell is limited to about 2.5V to 3.0V, so that to provide a voltage of, for example 60V (a typical value for 42V vehicle electrical system) about 20 to 25 individual cells to a capacitor stack in series with are switching.
  • a known possibility is to monitor the voltage of each individual cell by means of separate electronics and, upon reaching or exceeding a maximum value of the cell voltage, bring about a partial discharge by means of a connectable parallel resistor (shunt). The cell then discharges via the shunt and its voltage drops below the maximum value again.
  • shunt connectable parallel resistor
  • the shunt is switched off again and no further charge is taken from the capacitor.
  • Such a circuit consumes little energy in the passive state, but the charge compensation by charge reduction (energy loss in the module) is achieved.
  • This variant is usefully used where a capacitor stack is operated predominantly close to the maximum voltage; for example, in the supply of emergency power systems.
  • the concept is limited to the fact that the charging current of the capacitor module must be smaller than the discharge current, since otherwise still an overload of individual capacitors when charging the module is possible.
  • the compensation system can not be switched on externally, but can only by exceeding the max. Voltage activated. When operating in a motor vehicle, however, exactly this state is not reached over a longer time, which ultimately leads in the long term to an imbalance in the capacitor module. This could already be verified by measurements in a test vehicle.
  • the system has the following disadvantages: no feedback to a higher-level operational management, whether a capacitor the max. Voltage has exceeded (Uc> 2.5 V);
  • the compensation is only activated if the max. Voltage is exceeded;
  • this form of charge compensation can be carried out at any time independently of the maximum voltage of an individual cell, so that a dangerous charge imbalance in the double-layer capacitor can not even build up.
  • these cables are loaded with high-frequency voltage pulses from the switching operations of the flyback converter and require separate EMC suppression measures.
  • Another aspect is the method of operating the flyback converter.
  • Commercially available control circuits switching regulator ICs
  • switching regulator ICs operate almost exclusively at a fixed switching frequency.
  • the charging of the magnetic memory (Speicherinduktivi- tat or transformer) takes place in one phase, the discharge, or energy transfer takes place in the output circuit in the other phase of the bar. This is especially useful if in addition to the switched current and a DC component is transmitted (non-lopsided operation).
  • attempts are made to avoid a switching gap, that is to say a period in which the magnetic memory element remains completely discharged, since then oscillation tendencies increasingly occur and the memory properties of the magnetic core can not be optimally utilized.
  • the oscillations are due to the resonant circuit, which consists of storage inductance and winding capacitance, as well as the fact that the resonant circuit is excited at the beginning of the switching gap and is not attenuated by any ohmic load.
  • the object of the invention is to provide a device for charge equalization between the individual cells of a double-layer capacitor in a multi-voltage vehicle electrical system, which allows a simplification in the structure of the circuit and the wiring to the individual capacitors of the module;
  • a function monitoring of the charge balancing circuit and the individual cells should be possible;
  • the circuit should be constructed essentially with standard components and are particularly suitable for attachment to the cell stack or the individual cells; it should be easy to extend the entire system and thus be easily scalable.
  • the object of the invention is also to specify a method for operating this device.
  • Figure 1 a basic circuit according to the invention
  • Figure 2 a first embodiment of a circuit according to the invention in a simple embodiment
  • FIG. 3 shows a second exemplary embodiment of a differential circuit according to the invention
  • Figure 4 a drive circuit for the switching transistors
  • Figure 5 a Nachladescrien for the circuit in a simple design
  • FIG. 6 shows a recharging circuit for the circuit in different embodiments
  • FIG. 7 is a schematic diagram of a rectifier
  • FIG. 8 shows an embodiment of a rectifier restricted to a simple charge equalization circuit
  • FIG. 9 shows an exemplary embodiment of a rectifier extended to a differential charge equalization circuit.
  • FIG. 1 A basic block diagram of an embodiment according to the invention is shown in FIG.
  • Figure 1 shows a double-layer capacitor, which consists of a series circuit (stack) of single-capacitor cells Cl to Cn.
  • Each capacitor cell Cl to Cn (hereinafter referred to as "cell") is associated with a capacitor CIa to Cna, whose first connection
  • - Can be connected to the first terminal of the associated cell Cl to Cn via a first switch SIa to Sna, and - via a second switch SIb to Snb with the second
  • Connection of the associated cell Cl to Cn can be connected.
  • the second terminals of the capacitors CIa to Cna are connected together.
  • the two switches SIa and Sna are opened and closed synchronously with a predetermined frequency, and the switches SIb and Snb are switched on and off in antiphase.
  • FIG. 2 shows an exemplary embodiment of the circuit according to FIG. 1.
  • the switches SIa to Snb from FIG. 1 are embodied here as MOS-FET switching transistors TIa to Tnb, the first terminals of the capacitors CIa to Cna being connected to the source terminals of the first Switching transistors TIa to Tna and to the drain terminals of the second switching transistors TIb to Tnb are connected.
  • the drain terminals of the first switching transistors TIa to Tna are connected to the first terminals of their associated cells Cl to Cn, while the sources of the second switching transistors TIb to Tnb are connected to the second terminals of their associated cells Cl to Cn.
  • a series connection of two resistors Rla-Rlb to Rna-Rnb is arranged, whose connection points are connected to the first terminals of the capacitors CIa to Cna assigned to them.
  • the switching transistors TIa to Tnb are operated as switches.
  • the capacitors CIa to Cna are charged so that only a small voltage is applied to the switching transistors TIa to Tnb, which is achieved by the resistors Rla-Rlb to Rna-Rnb; Cell Cl has a high charging voltage and cell Cn has a low charging voltage;
  • V2 V C2 + ... + V Cn _i + V Cn on the series connection of the capacitors CIa and Cna is the starting point of the following method:
  • Vl Vd + V 02 + • • • + Vcn-i
  • V2 V 02 + • • • + Vcn-i + V 0n
  • the differential voltage dVl has a positive value and a current corresponding to the voltage difference dVl flows from the first terminal of the cell C1 via TIa, CIa, Cna, Tna and via the cell stack Cn-I to Cl back to the starting point.
  • the two capacitors CIa and Cna are now at the voltage Vl.
  • the differential voltage dV2 has a negative value:
  • charge from cell Cl flows into the capacitors CIa, Cna, and in the second phase, charge from the capacitors CIa, Cna flows into cell Cn. This is a charge transfer from the higher charged cell Cl to the lower charged cell Cn.
  • the compensation circuit is expanded by doubling the circuit according to FIG.
  • the two circuits are operated in push-pull, so that now the switching transistors TIa and Tna and TId and Tnd and in the next cycle then the switching transistors TIb and TnB and Tic and Tnc are turned on simultaneously in one cycle.
  • the alternating current flowing through the intervening cells (in the aforementioned embodiment, C2 to Cn-I) is completely eliminated. Since the voltage potentials of the switching transistors TIa to Tnd shown in FIGS. 2 and 3, due to their arrangement, are approximately at the level of the cells C1 to Cn assigned to them, a simple triggering with ground reference is only possible to a limited extent.
  • FIG. 4 shows such a drive circuit for the switching transistors.
  • the function of this circuit is explained using the example of the switching transistors TIa and TIb shown in FIGS. 2 and 3 and applies mutatis mutandis to all other switching transistors T2a to Tnd of the circuits in FIGS. 2 and 3.
  • FIGS. 2 and 3 show the switching transistors TIa and TIb themselves and the series connection of two resistors Rla-Rlb, which are arranged parallel to the cell C1 and whose connection point is connected to the first terminal of the capacitor CI assigned to the cell C1. However, the gate terminals of both switching transistors, via which the control takes place, are not connected there.
  • the control of the switching transistors TIa and TIb takes place in the embodiment of Figure 4, for example, by capacitive coupling of the control signals Tla-A, Tlb-A via a respective coupling capacitor ClIa, ClIb, wherein still a clamping to the source potential of the respective switching transistor is necessary, which one Zener diode DIa, DIb and one resistor RlIa, RlIb each, which are connected between source and gate of the associated switching transistor TIa, TIb, wherein the cathode terminal of the Zener diode is connected to the gate of the associated switching transistor.
  • IClB is used for current amplification of the control signals Tla-A, Tlb-A.
  • TIb of the coupling capacitor ClIa or ClIb is arranged.
  • the switching signals Tla-Ein and Tlb-Ein should be at low level and have the terminals of the logic buffers IClA and IClB connected to the terminals of the capacitors ClIa and ClIb OV potential.
  • the gate terminal of the switching transistor TIa, TIb terminal of the capacitor ClIa, ClIb is - due to the resistor RlIa, RlIb - the source potential of the switching transistor TIa, TIb.
  • the gate-source voltage of the switching transistor TIa, TIb OV and switching transistor TIa, TIb is not conductive.
  • the terminal of the capacitor CIa connected to the source terminal of switching transistor TIa and the drain terminal of switching transistor TIb is set to half the voltage applied to cell Cl.
  • the gate-source voltage of the switching transistor TIa will increase approximately by the value of the voltage jump at the output of the logic buffer IClA and the switching transistor TIa switch on.
  • the zener diode DIa limits the gate-source voltage to a value permissible for the switching transistor.
  • the capacitor ClIa becomes resistive RlIa discharge something, but without falling below the turn-on of the switching transistor TIa.
  • the gate-source voltage at the switching transistor TIa also decreases by the same amount as the control signal Tla-Ein (the output voltage of the logic buffer ClA).
  • the gate-source voltage will now become negative. However, this is limited to a value of about -0.7V, since the zener diode DIa is now poled in the flow direction and thus clamps the voltage.
  • the capacitor ClIa is reloaded to its original value so that the next switch-on process can take place in the same way.
  • control signals Tla-Ein and Tlb-Ein have alternately high and low levels in the charge balance mode.
  • circuit arrangement described so far can carry out a charge equalization between one or more cells in the double-layer capacitor stack, they do not cause a total recharging of the stack from an external energy source.
  • a recharge may be required if the total voltage of the double-layer capacitor falls below a predetermined minimum value. It is simply the sum of the stored values of the charging voltages V C i to V Cn formed and compared with the predetermined minimum value. If this minimum value is undershot, individual cells, cell groups or the entire double-layer capacitor can be recharged by an external energy source.
  • the recharging circuit according to FIG. 5 consists of a recharging capacitor Cv whose one terminal is at reference potential GND and which is charged via a switchable current source Q with a constant current from an external energy source, for example an on-board voltage source Vbat via a switch SB to a predetermined voltage.
  • a voltage divider of two equal resistances RvIa, Rv2a is arranged.
  • a switching transistor Tva is provided whose drain is connected to the connection point of current source Q and after-charging capacitor Cv and whose source leads to a node A and is simultaneously connected to the junction of the two resistors RvIa, Rv2a, and - a switching transistor Tvb whose drain is provided is connected to the node A and whose source terminal is connected to reference potential GND.
  • both switching transistors Tva and Tvb act on the connection node A (see FIG. 2) of the capacitors CIa to Cna, it is now possible to simultaneously charge the reload capacitor Cv to the cell Cl by simultaneously switching the switching transistors Tva and TIa, or in opposite phases thereto or another cell. It is thus possible to reload individual cells in the stack.
  • the resistors RvIa, Rv2a of the same size ensure that the connection node A is at half the DC potential of the recharging capacitor Cv.
  • switching transistors TIa to Tnb (FIG. 2) or TIa to Tnd (FIG. 3) are not conductively controlled.
  • the switching transistors TIa and TIb assigned to one cell, for example Cl are turned on (in the case of the circuit according to FIG. 3, the switching transistors TIa and TId as well as TIb and Tic at the same time are switched simultaneously).
  • this produces a rectangular AC voltage whose peak-to-peak value corresponds to the charge voltage of cell C1. Due to the opposite-phase actuation of the switching transistors TIa and TIb or TIC and TId, the signals at the nodes A and B are also in opposite phase.
  • the DC voltage value of the nodes A and B is - as described above - half the value of the charging voltage of the recharging capacitor Cv. This DC voltage value is superimposed on the rectangular AC voltage.
  • the nodes A and A and B are - except with the Nachladescaria - also connected to the terminals A and A and B of a rectifier, which rectifies the rectangular AC voltage in a referenced GND reference voltage.
  • the principle of such rectification is shown in FIG. If the charging voltage of, for example, the cell Cl is determined and stored by measuring the output voltage Vout of the rectifier, the switching transistors TIa and TIb or TIa to TId assigned to the cell C1 are again switched to non-conducting.
  • the charging voltage of the cell C2 or another cell can be detected by corresponding switching of the associated switching transistors at the output Vout of the rectifier.
  • the charging voltages of all cells of the stack can be determined and stored one after the other.
  • the DC potentials of these nodes can be set to a reference potential by inserting a resistor between node A or B and a reference voltage-about 2.5V.
  • This AC voltage can then be converted with a suitable rectifier into a DC voltage corresponding to the peak-to-peak value with reference to reference potential GND. It is therefore suitable for further processing - for example at the A / D input of a microcontroller.
  • FIG. 8 shows a known per se embodiment of a rectifier for the evaluation of the cell voltages which is limited to the simple charge equalization circuit according to FIG. 2 and designed as a synchronous demodulator (see DE 100 34 060, FIG. 5 and associated description).
  • the inputs of the rectifier are to be connected via a switch Schla to the node A (the connection of the capacitors CIa to Cna) of the compensation circuit of Figure 2.
  • the control signal of the changeover switch Schla corresponds to the signals Tla-Ein to Tna-Ein described in FIG. 4, wherein the signal assigned to the respective capacitor C 1 to Cn to be measured is selected.
  • the circuit is also suitable for rectifying differential signals in the exemplary embodiment of the charge balancing circuit according to FIG. 3.
  • a switch Schlb is added only to switch Schla, both switches by means of the control signal of the cell to be measured each cell Cl to Cn associated switching transistor (for cell Cl it is the control signal Tla-one, for cell Cn then the control signal Tna-A) be switched so that in one phase node A to input A of the rectifier (op amp AMPI) and node B with
  • Input B of the rectifier (operational amplifier AMP2) is connected and in the other phase node A is connected to input B and node B to input A.
  • the signal Tla-A is used to measure the charging voltage of a cell of cell Cl.
  • the control signals T2a-A to Tna-A are to be used accordingly.
  • the following method sequence is initiated at specific, predetermined intervals: - Measurement of the charging voltages of all cells; For this purpose, as described above, the switching transistors assigned to each cell to be measured are switched, the charging voltage Vc of the cell is measured and stored; - Determining if a charge equalization is required; the stored values of the charging voltages of all cells are compared for their differences with each other; If one or more differences are above a predetermined limit value, a charge equalization must take place between the cells with too large differences.
  • the charging voltages are compared with a predetermined maximum value. If one or more values are above this maximum value, then a partial discharge must take place by charge equalization with cells having the lowest charge:
  • a recharge circuit according to FIG. 6 If a recharge circuit according to FIG. 6 is used, then a single cell can be recharged. This is particularly useful if, for example, as a result of aging, a cell shows significantly increased self-discharge; any subset of cells are reloaded; This is especially useful if cells with different properties (capacity, self-discharge) are installed in the stack and the subset should be aligned with the rest of the stack; the entire stack of capacitors are recharged when the stack is indeed balanced, but overall has a too low charging voltage.
  • a resistor is to be provided in the case of simple operation, one of whose terminals is to be connected to node A of the charge equalization circuit and whose other terminal is to be connected to a reference voltage Vref (for example + 2.5 V) (shown in dashed lines in FIG. 8). .
  • Vref for example + 2.5V
  • the efficiency of the circuit is very high; - Through the use of switching transistors operated as a switch, only small losses occur; the connection and potential separation of the cells takes place via capacitors; only a few and inexpensive components are required for the circuit; the voltage of each individual cell in the stack can be measured easily and with high precision; a compensation process can be activated at any time; the charge balance energy does not have to be taken from the entire stack, but can be selectively taken from a particular (highest charged) cell;
  • the circuit allows highly efficient, targeted charge balancing between individual cells or cell groups of the stack and the entire stack; With suitable circuit selection (differential switching), charge equalization takes place between any two cells without an AC load on the cells in between;
  • a charge equalization is also possible with a cell error (for example, short circuit) - the circuit associated with the affected cell is then simply no longer actuated; reloading individual cells or cell groups and the entire stack is possible; the circuit is particularly effective because different parts of each circuit parts can be used repeatedly;
  • a cell error for example, short circuit
  • the overall system is easy to expand and therefore easily scalable.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

L'invention concerne un dispositif et un procédé d'équilibrage de charge entre les cellules individuelles d'un condensateur à double couche, en particulier dans un réseau de bord de véhicule automobile à tension multiple. Selon ladite invention, un condensateur est associé à chaque cellule individuelle du condensateur à double couche, condensateur dont le premier raccord peut être relié au premier raccord de la cellule associée, par l'intermédiaire d'un premier commutateur, et au second raccord de la cellule associée, par l'intermédiaire d'un second commutateur, et dont le second raccord est relié aux seconds raccords de tous les condensateurs.
EP06793147A 2005-09-02 2006-09-01 Dispositif et procede d'equilibrage de charge entre les cellules individuelles d'un condensateur a double couche Withdrawn EP1920518A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005041824A DE102005041824A1 (de) 2005-09-02 2005-09-02 Vorrichtung und Verfahren zum Ladungsausgleich zwischen den Einzelzellen eines Doppelschichtkondensators, insbesondere in einem Mehrspannungs-Kraftfahrzeugbordnetz
PCT/EP2006/065924 WO2007026019A1 (fr) 2005-09-02 2006-09-01 Dispositif et procede d'equilibrage de charge entre les cellules individuelles d'un condensateur a double couche

Publications (1)

Publication Number Publication Date
EP1920518A1 true EP1920518A1 (fr) 2008-05-14

Family

ID=37450769

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06793147A Withdrawn EP1920518A1 (fr) 2005-09-02 2006-09-01 Dispositif et procede d'equilibrage de charge entre les cellules individuelles d'un condensateur a double couche

Country Status (5)

Country Link
US (1) US7825638B2 (fr)
EP (1) EP1920518A1 (fr)
CN (1) CN101283495B (fr)
DE (1) DE102005041824A1 (fr)
WO (1) WO2007026019A1 (fr)

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DE102005041824A1 (de) 2007-03-08
US20080252266A1 (en) 2008-10-16
CN101283495B (zh) 2013-04-03
US7825638B2 (en) 2010-11-02
WO2007026019A1 (fr) 2007-03-08
CN101283495A (zh) 2008-10-08

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