EP1920518A1

EP1920518A1 - Device and method for balancing charge between the individual cells of a double-layer capacitor

Info

Publication number: EP1920518A1
Application number: EP06793147A
Authority: EP
Inventors: Stephan Bolz; Martin GÖTZENBERGER; Rainer Knorr
Original assignee: Siemens AG; Continental Automotive GmbH
Current assignee: Continental Automotive GmbH
Priority date: 2005-09-02
Filing date: 2006-09-01
Publication date: 2008-05-14
Also published as: WO2007026019A1; CN101283495B; DE102005041824A1; US7825638B2; CN101283495A; US20080252266A1

Abstract

The invention relates to a device and a method for balancing charge between the individual cells of a double-layer capacitor, in particular in a multi-voltage motor vehicle electrical system, each individual cell of the double-layer capacitor being associated with a capacitor, the first terminal of which can be connected via a first switch to the first terminal of the associated cell and via a second switch to the second terminal of the associated cell, and the second terminal of which is connected to the second terminals of all the capacitors.

Description

description

DEVICE AND METHOD FOR CHARGE COMPENSATION BETWEEN THE INDIVIDUAL CELLS OF A DOUBLE LAYER CONDENSER

The invention relates to a device for charge equalization between the individual cells of a double-layer capacitor, in particular in a multi-voltage vehicle electrical system.

The invention also relates to a method for operating this device.

Double-layer capacitors have proved to be the most sensible technical solution for providing or storing short-term high powers, such as acceleration support by means of an electric motor (boost mode) or the electrical conversion of kinetic energy during regenerative braking in so-called "mild" hybrid vehicles.

The maximum voltage of a double-layer capacitor single cell, however, is limited to about 2.5V to 3.0V, so that to provide a voltage of, for example 60V (a typical value for 42V vehicle electrical system) about 20 to 25 individual cells to a capacitor stack in series with are switching.

As a result of different self-discharge of the individual cells, a charge imbalance in the double-layer capacitor builds up over time, which would ultimately render it unusable.

The spread of self-discharge of the individual cells within a capacitor module can be very large. Extrapolating this for periods of weeks to months, as relevant to the use of a motor vehicle, the existing problem becomes obvious. A simple charge equalization, such as by slight overcharging as in a lead-acid battery (starter battery), is not possible with double-layer capacitors.

A known possibility is to monitor the voltage of each individual cell by means of separate electronics and, upon reaching or exceeding a maximum value of the cell voltage, bring about a partial discharge by means of a connectable parallel resistor (shunt). The cell then discharges via the shunt and its voltage drops below the maximum value again.

If the maximum value falls below a certain voltage value, the shunt is switched off again and no further charge is taken from the capacitor.

Such a circuit consumes little energy in the passive state, but the charge compensation by charge reduction (energy loss in the module) is achieved. This variant is usefully used where a capacitor stack is operated predominantly close to the maximum voltage; for example, in the supply of emergency power systems.

However, the concept is limited to the fact that the charging current of the capacitor module must be smaller than the discharge current, since otherwise still an overload of individual capacitors when charging the module is possible. In addition, the compensation system can not be switched on externally, but can only by exceeding the max. Voltage activated. When operating in a motor vehicle, however, exactly this state is not reached over a longer time, which ultimately leads in the long term to an imbalance in the capacitor module. This could already be verified by measurements in a test vehicle. In summary, the system has the following disadvantages: no feedback to a higher-level operational management, whether a capacitor the max. Voltage has exceeded (Uc> 2.5 V);

no feedback as to whether the capacitor voltages are the same and therefore the capacitor module is balanced;

- the compensation is only activated if the max. Voltage is exceeded;

- Energy is transformed from resistance to heat during the balancing process.

Another known possibility is the use of a - also known - flyback switching regulator, wherein now the entire capacitor module energy is removed and this is then fed back into the most discharged single capacitor. Such a solution is known from EP 0432636 A2.

Alternatively, another energy source, such as an accumulator, can also be used here, as a result of which the circuit can additionally serve for slow charging of the capacitor module. See patent application DE 102 56 704.

In addition, this form of charge compensation can be carried out at any time independently of the maximum voltage of an individual cell, so that a dangerous charge imbalance in the double-layer capacitor can not even build up.

In addition, only charges are shifted, so energy is not taken from the module in the long term. This makes the concept particularly attractive for motor vehicle applications, since even after a prolonged vehicle standstill sufficient energy must be present in the electrical system in order to ensure a successful engine start safely. Also occur in the above-described vehicle function "Regenerative braking" currents up to about IkA, so that a charge equalization is excluded after the first known possibility in this situation.

The disadvantage of this extended execution, however, that the secondary side of the flyback transformer needs a lot of connections. With a capacitor stack of, for example, 25 individual cells, as required for the 42V vehicle electrical system, this results in 50 connections. In the technical realization, this would require a special winding body, which is not commercially available. Also, any change in the number of single cells in the stack requires an adaptation of the transformer.

However, changes in the numbers of single cells are to be expected, since the permissible maximum voltage will increase from generation to generation with the further technical development of the double-layer capacitors and correspondingly fewer individual cells will be required for a given total voltage.

The Leitungsfuhrung from the transformer to the capacitors is very expensive, since each contact in the module must be connected separately. In the above example this results in 26 lines, provided that the rectifier diodes are arranged on the transformer; otherwise it will be 50 lines.

In addition, these cables are loaded with high-frequency voltage pulses from the switching operations of the flyback converter and require separate EMC suppression measures.

Another aspect is the method of operating the flyback converter. Commercially available control circuits (switching regulator ICs) operate almost exclusively at a fixed switching frequency. The charging of the magnetic memory (Speicherinduktivi- tat or transformer) takes place in one phase, the discharge, or energy transfer takes place in the output circuit in the other phase of the bar. This is especially useful if in addition to the switched current and a DC component is transmitted (non-lopsided operation). In general, attempts are made to avoid a switching gap, that is to say a period in which the magnetic memory element remains completely discharged, since then oscillation tendencies increasingly occur and the memory properties of the magnetic core can not be optimally utilized. The oscillations are due to the resonant circuit, which consists of storage inductance and winding capacitance, as well as the fact that the resonant circuit is excited at the beginning of the switching gap and is not attenuated by any ohmic load.

In the described application, however, a non-gap operation is not possible because, with continuous recharging of the magnetic memory (storage inductance or transformer), saturation of the core material can not be avoided before its complete discharge.

The object of the invention is to provide a device for charge equalization between the individual cells of a double-layer capacitor in a multi-voltage vehicle electrical system, which allows a simplification in the structure of the circuit and the wiring to the individual capacitors of the module; In addition, a function monitoring of the charge balancing circuit and the individual cells should be possible; the circuit should be constructed essentially with standard components and are particularly suitable for attachment to the cell stack or the individual cells; it should be easy to extend the entire system and thus be easily scalable. The object of the invention is also to specify a method for operating this device.

This object is achieved by a device according to the features of claim 1 and a method according to the features of claim 10. Advantageous developments of the invention can be found in the dependent claims.

In the drawing show:

Figure 1: a basic circuit according to the invention; Figure 2: a first embodiment of a circuit according to the invention in a simple embodiment;

FIG. 3 shows a second exemplary embodiment of a differential circuit according to the invention;

Figure 4: a drive circuit for the switching transistors; Figure 5: a Nachladeschaltung for the circuit in a simple design;

FIG. 6 shows a recharging circuit for the circuit in different embodiments;

Figure 7 is a schematic diagram of a rectifier; FIG. 8 shows an embodiment of a rectifier restricted to a simple charge equalization circuit; and FIG. 9 shows an exemplary embodiment of a rectifier extended to a differential charge equalization circuit.

In order to be able to achieve charge equalization of the individual cells of a double-layer capacitor stack, energy should be taken from the cells which have the highest voltage and be supplied via a suitable circuit to the capacitors with the lowest voltage. A basic block diagram of an embodiment according to the invention is shown in FIG.

Figure 1 shows a double-layer capacitor, which consists of a series circuit (stack) of single-capacitor cells Cl to Cn.

Each capacitor cell Cl to Cn (hereinafter referred to as "cell") is associated with a capacitor CIa to Cna, whose first connection

- Can be connected to the first terminal of the associated cell Cl to Cn via a first switch SIa to Sna, and - via a second switch SIb to Snb with the second

Connection of the associated cell Cl to Cn can be connected.

The second terminals of the capacitors CIa to Cna are connected together.

The method according to the invention for determining the cell voltages, whose knowledge is required for a recharge or recharge of specific cells, will be described later.

All of the method steps described below are in principle carried out programmatically by means of microprocessors (not shown).

The two switches SIa and Sna are opened and closed synchronously with a predetermined frequency, and the switches SIb and Snb are switched on and off in antiphase.

If the voltages V _C i and V _Cn at the cells Cl and Cn are the same, no current will flow during switching.

However, if the voltages Vci and V _Cn at the cells Cl and Cn are different, then a current corresponding to the voltage difference will flow from the cell having the higher charging voltage to the cell having the lower voltage, for example from cell Cl to cell Cn. This shifts charge from the higher charged cell to the lower charged cell, allowing charge balancing between these two cells without affecting the remaining cells. In the cells Cl and Cn, a pulsating direct current flows, while in the intermediate cells C2 to Cn-I, an alternating current flows.

FIG. 2 shows an exemplary embodiment of the circuit according to FIG. 1. The switches SIa to Snb from FIG. 1 are embodied here as MOS-FET switching transistors TIa to Tnb, the first terminals of the capacitors CIa to Cna being connected to the source terminals of the first Switching transistors TIa to Tna and to the drain terminals of the second switching transistors TIb to Tnb are connected. The drain terminals of the first switching transistors TIa to Tna are connected to the first terminals of their associated cells Cl to Cn, while the sources of the second switching transistors TIb to Tnb are connected to the second terminals of their associated cells Cl to Cn.

Parallel to each cell C1 to Cn, a series connection of two resistors Rla-Rlb to Rna-Rnb is arranged, whose connection points are connected to the first terminals of the capacitors CIa to Cna assigned to them. The switching transistors TIa to Tnb are operated as switches.

As an initial condition for the method according to the invention, all the switching transistors TIa to Tnb are not conducting;

- The capacitors CIa to Cna are charged so that only a small voltage is applied to the switching transistors TIa to Tnb, which is achieved by the resistors Rla-Rlb to Rna-Rnb; Cell Cl has a high charging voltage and cell Cn has a low charging voltage;

- It should be a charge balance by charge transfer from cell Cl to cell Cn.

According to the method according to the invention for charge equalization, the second switching transistors TIb and Tnb of the cells to be reloaded are initially conductively controlled. There is a flowing initial equalizing current from the first terminal of the cell C2 via the second switching transistor TIb, the capacitors CIa and Cna and the second switching transistor Tnb to the second terminal of the cell Cn until the series circuit of CIa and Cna has the voltage V2 = V _C2 + ... + V _Cn _i + V _{Cn of} the capacitor sub-stack C2 to Cn has reached.

The voltage V2 = V _C2 + ... + V _Cn _i + V _Cn on the series connection of the capacitors CIa and Cna is the starting point of the following method:

Now, the second switching transistors TIb and Tnb are not turned on and the first switching transistors TIa and Tna are turned on. However, the resulting bonded part of the newspaper stack len Cl to Cn-I is located at a different, higher voltage Vl = V _C i + V _C2 + ... + _Cn V i as the series connection of two capacitors CIa and Cna (V2) :

Vl = Vd + V ₀₂ + • • • + Vcn-i V2 = V ₀₂ + • • • + Vcn-i + V _0n

This results in a difference voltage of:

dVl = Vl - V2 = V ₀₁ - V _Cn

Since, as defined above, Vcl> Vcn, the differential voltage dVl has a positive value and a current corresponding to the voltage difference dVl flows from the first terminal of the cell C1 via TIa, CIa, Cna, Tna and via the cell stack Cn-I to Cl back to the starting point. The two capacitors CIa and Cna are now at the voltage Vl.

If again the first switching transistors TIa and Tna are not turned on and the second switching transistors TIb and TnB are turned on, then the capacitors CIa and Cna have the voltage Vl, while the voltage on the part stack C2 +... + Cn is now V2. The differential voltage dV2 has a negative value:

dV2 = V2 - Vl

why the current flow through the capacitors CIa, Cna reverses.

Thus, in the first phase charge from cell Cl flows into the capacitors CIa, Cna, and in the second phase, charge from the capacitors CIa, Cna flows into cell Cn. This is a charge transfer from the higher charged cell Cl to the lower charged cell Cn.

In the remaining cells C2 to Cn-I, the currents have a positive or negative sign depending on the switching phase. Thus, there is effectively no charge shift here.

In a further embodiment according to FIG. 3, the compensation circuit is expanded by doubling the circuit according to FIG.

The two circuits are operated in push-pull, so that now the switching transistors TIa and Tna and TId and Tnd and in the next cycle then the switching transistors TIb and TnB and Tic and Tnc are turned on simultaneously in one cycle.

This ensures that in each switching phase, current flows from the higher-charged cell to the lower-charged cell, which accelerates the charging process and, with respect to the cells, improves the pulsed current profile to a uniform (DC) characteristic.

Also, the alternating current flowing through the intervening cells (in the aforementioned embodiment, C2 to Cn-I) is completely eliminated. Since the voltage potentials of the switching transistors TIa to Tnd shown in FIGS. 2 and 3, due to their arrangement, are approximately at the level of the cells C1 to Cn assigned to them, a simple triggering with ground reference is only possible to a limited extent.

So it is a circuit required that allows driving of the switching transistors regardless of their DC potential. Also, in the absence of control of the switching transistor must be turned off automatically to prevent damage to the components in case of faulty ongoing activation.

FIG. 4 shows such a drive circuit for the switching transistors. The function of this circuit is explained using the example of the switching transistors TIa and TIb shown in FIGS. 2 and 3 and applies mutatis mutandis to all other switching transistors T2a to Tnd of the circuits in FIGS. 2 and 3.

FIGS. 2 and 3 show the switching transistors TIa and TIb themselves and the series connection of two resistors Rla-Rlb, which are arranged parallel to the cell C1 and whose connection point is connected to the first terminal of the capacitor CI assigned to the cell C1. However, the gate terminals of both switching transistors, via which the control takes place, are not connected there.

The control of the switching transistors TIa and TIb takes place in the embodiment of Figure 4, for example, by capacitive coupling of the control signals Tla-A, Tlb-A via a respective coupling capacitor ClIa, ClIb, wherein still a clamping to the source potential of the respective switching transistor is necessary, which one Zener diode DIa, DIb and one resistor RlIa, RlIb each, which are connected between source and gate of the associated switching transistor TIa, TIb, wherein the cathode terminal of the Zener diode is connected to the gate of the associated switching transistor.

Depending on a logic buffer IClA, IClB is used for current amplification of the control signals Tla-A, Tlb-A. Between its output and the gate of the associated switching transistor TIa, TIb of the coupling capacitor ClIa or ClIb is arranged.

At the beginning of a switching operation, the switching signals Tla-Ein and Tlb-Ein should be at low level and have the terminals of the logic buffers IClA and IClB connected to the terminals of the capacitors ClIa and ClIb OV potential.

Connected to the gate terminal of the switching transistor TIa, TIb terminal of the capacitor ClIa, ClIb is - due to the resistor RlIa, RlIb - the source potential of the switching transistor TIa, TIb. Thus, the gate-source voltage of the switching transistor TIa, TIb OV and switching transistor TIa, TIb is not conductive.

Through the voltage divider Rla-Rlb (both resistors have the same values), the terminal of the capacitor CIa connected to the source terminal of switching transistor TIa and the drain terminal of switching transistor TIb is set to half the voltage applied to cell Cl.

If the signal TIa Ein switches to high level, (with a suitable choice of the values of ClIa and RlIa), the gate-source voltage of the switching transistor TIa will increase approximately by the value of the voltage jump at the output of the logic buffer IClA and the switching transistor TIa switch on.

It must be ensured that the voltage jump is large enough in comparison with the switch-on voltage of the switching transistor TIa. The zener diode DIa limits the gate-source voltage to a value permissible for the switching transistor. In the further course, the capacitor ClIa becomes resistive RlIa discharge something, but without falling below the turn-on of the switching transistor TIa.

If the control signal Tla-Ein then jumps to low level, the gate-source voltage at the switching transistor TIa also decreases by the same amount as the control signal Tla-Ein (the output voltage of the logic buffer ClA). However, since capacitor ClIa is slightly discharged, the gate-source voltage will now become negative. However, this is limited to a value of about -0.7V, since the zener diode DIa is now poled in the flow direction and thus clamps the voltage. At the same time, the capacitor ClIa is reloaded to its original value so that the next switch-on process can take place in the same way.

The control signals Tla-Ein and Tlb-Ein have alternately high and low levels in the charge balance mode.

Although the circuit arrangement described so far can carry out a charge equalization between one or more cells in the double-layer capacitor stack, they do not cause a total recharging of the stack from an external energy source.

A recharge may be required if the total voltage of the double-layer capacitor falls below a predetermined minimum value. It is simply the sum of the stored values of the charging voltages V _C i to V _Cn formed and compared with the predetermined minimum value. If this minimum value is undershot, individual cells, cell groups or the entire double-layer capacitor can be recharged by an external energy source.

If a recharge is not to be made via the connection Vst of the double-layer capacitor (or can), then it is possible to do this for example via an on-board voltage source Vbat by means of an additionally switchable recharging capacitor Cv, as for the simple Compensation circuit is shown in Figure 5 or for the differential compensation circuit in Figure 6.

The recharging circuit according to FIG. 5 consists of a recharging capacitor Cv whose one terminal is at reference potential GND and which is charged via a switchable current source Q with a constant current from an external energy source, for example an on-board voltage source Vbat via a switch SB to a predetermined voltage. Parallel to the recharging capacitor Cv, a voltage divider of two equal resistances RvIa, Rv2a is arranged.

Furthermore is

a switching transistor Tva is provided whose drain is connected to the connection point of current source Q and after-charging capacitor Cv and whose source leads to a node A and is simultaneously connected to the junction of the two resistors RvIa, Rv2a, and - a switching transistor Tvb whose drain is provided is connected to the node A and whose source terminal is connected to reference potential GND.

Since both switching transistors Tva and Tvb act on the connection node A (see FIG. 2) of the capacitors CIa to Cna, it is now possible to simultaneously charge the reload capacitor Cv to the cell Cl by simultaneously switching the switching transistors Tva and TIa, or in opposite phases thereto or another cell. It is thus possible to reload individual cells in the stack.

The resistors RvIa, Rv2a of the same size ensure that the connection node A is at half the DC potential of the recharging capacitor Cv.

Are the charging voltages in the cell stack or a subset of the same, so you can by simultaneously switching the Transmit transistors associated with these cells transfer charge to the entire cell stack or subset.

The above also applies mutatis mutandis to the switching transistors Tvc and Tvd and for the connection node B in the differential embodiment of Figure 6, which consists in a doubling of the circuit of Figure 5. The reloading process is accelerated in this embodiment.

By suitable control of the circuits according to Figures 2 and 3, it is very easy to determine the charging voltage of each cell Cl to Cn in the stack with high accuracy.

For this purpose, first of all switching transistors TIa to Tnb (FIG. 2) or TIa to Tnd (FIG. 3) are not conductively controlled. Now, alternately, the switching transistors TIa and TIb assigned to one cell, for example Cl, are turned on (in the case of the circuit according to FIG. 3, the switching transistors TIa and TId as well as TIb and Tic at the same time are switched simultaneously).

At node A or A and B, this produces a rectangular AC voltage whose peak-to-peak value corresponds to the charge voltage of cell C1. Due to the opposite-phase actuation of the switching transistors TIa and TIb or TIC and TId, the signals at the nodes A and B are also in opposite phase. The DC voltage value of the nodes A and B is - as described above - half the value of the charging voltage of the recharging capacitor Cv. This DC voltage value is superimposed on the rectangular AC voltage.

The nodes A and A and B are - except with the Nachladeschaltung - also connected to the terminals A and A and B of a rectifier, which rectifies the rectangular AC voltage in a referenced GND reference voltage. The principle of such rectification is shown in FIG. If the charging voltage of, for example, the cell Cl is determined and stored by measuring the output voltage Vout of the rectifier, the switching transistors TIa and TIb or TIa to TId assigned to the cell C1 are again switched to non-conducting.

Subsequently, the charging voltage of the cell C2 or another cell can be detected by corresponding switching of the associated switching transistors at the output Vout of the rectifier.

In this way, the charging voltages of all cells of the stack can be determined and stored one after the other.

If no recharging circuit is used (according to FIGS. 5, 6), the DC potentials of these nodes can be set to a reference potential by inserting a resistor between node A or B and a reference voltage-about 2.5V.

By this process, it is now possible to translate the charging voltage of a selected capacitor (for example Cl) from an optionally high DC potential into an AC voltage with reference to the reference potential.

This AC voltage can then be converted with a suitable rectifier into a DC voltage corresponding to the peak-to-peak value with reference to reference potential GND. It is therefore suitable for further processing - for example at the A / D input of a microcontroller.

FIG. 8 shows a known per se embodiment of a rectifier for the evaluation of the cell voltages which is limited to the simple charge equalization circuit according to FIG. 2 and designed as a synchronous demodulator (see DE 100 34 060, FIG. 5 and associated description). The inputs of the rectifier are to be connected via a switch Schla to the node A (the connection of the capacitors CIa to Cna) of the compensation circuit of Figure 2. The control signal of the changeover switch Schla corresponds to the signals Tla-Ein to Tna-Ein described in FIG. 4, wherein the signal assigned to the respective capacitor C 1 to Cn to be measured is selected.

By a simple addition of the rectifier circuit according to FIG. 8, the circuit is also suitable for rectifying differential signals in the exemplary embodiment of the charge balancing circuit according to FIG. 3.

For this purpose, a switch Schlb is added only to switch Schla, both switches by means of the control signal of the cell to be measured each cell Cl to Cn associated switching transistor (for cell Cl it is the control signal Tla-one, for cell Cn then the control signal Tna-A) be switched so that in one phase node A to input A of the rectifier (op amp AMPI) and node B with

Input B of the rectifier (operational amplifier AMP2) is connected and in the other phase node A is connected to input B and node B to input A.

Such an embodiment is shown in FIG. As a control signal, the signal Tla-A is used to measure the charging voltage of a cell of cell Cl. For the measurement of the cells C2 to Cn, the control signals T2a-A to Tna-A are to be used accordingly.

When operated on a capacitor stack, a meaningful functional sequence results, which can be processed by a microcontroller program.

According to the invention, the following method sequence is initiated at specific, predetermined intervals: - Measurement of the charging voltages of all cells; For this purpose, as described above, the switching transistors assigned to each cell to be measured are switched, the charging voltage Vc of the cell is measured and stored; - Determining if a charge equalization is required; the stored values of the charging voltages of all cells are compared for their differences with each other; If one or more differences are above a predetermined limit value, a charge equalization must take place between the cells with too large differences.

The charging voltages are compared with a predetermined maximum value. If one or more values are above this maximum value, then a partial discharge must take place by charge equalization with cells having the lowest charge:

- charge balance between the cells thus determined; Periodically measuring the charging voltages of the charge-sharing cells;

- Termination of the compensation process, when the charging voltages of the cells are sufficiently matched.

If it is desired to charge compensation as quickly as possible, it is alternatively possible to switch all the switching transistors assigned to the cells, ie simultaneously TIa to Tna and TId to Tnd in the first phase, and simultaneously TIb to Tnb and Tic to Tnc in the second phase. The current in the single switching transistor will not increase compared to the balance between two cells, but the total charge moved per unit time. This is much more efficient than other methods where charge is transferred from the entire stack to the cell with the lowest charging voltage.

If a recharge circuit according to FIG. 6 is used, then a single cell can be recharged. This is particularly useful if, for example, as a result of aging, a cell shows significantly increased self-discharge; any subset of cells are reloaded; This is especially useful if cells with different properties (capacity, self-discharge) are installed in the stack and the subset should be aligned with the rest of the stack; the entire stack of capacitors are recharged when the stack is indeed balanced, but overall has a too low charging voltage.

If no recharging circuit is used, a resistor is to be provided in the case of simple operation, one of whose terminals is to be connected to node A of the charge equalization circuit and whose other terminal is to be connected to a reference voltage Vref (for example + 2.5 V) (shown in dashed lines in FIG. 8). .

to provide, in differential operation, for each node A, B of the charge balancing circuit a resistor whose one terminal is to be connected to nodes A and B, respectively, and whose other terminal is to be connected to a reference voltage Vref (for example + 2.5V) (in Figure 9 shown in phantom).

Advantages of the Invention The efficiency of the circuit is very high; - Through the use of switching transistors operated as a switch, only small losses occur; the connection and potential separation of the cells takes place via capacitors; only a few and inexpensive components are required for the circuit; the voltage of each individual cell in the stack can be measured easily and with high precision; a compensation process can be activated at any time; the charge balance energy does not have to be taken from the entire stack, but can be selectively taken from a particular (highest charged) cell; The circuit allows highly efficient, targeted charge balancing between individual cells or cell groups of the stack and the entire stack; With suitable circuit selection (differential switching), charge equalization takes place between any two cells without an AC load on the cells in between;

- A charge equalization is also possible with a cell error (for example, short circuit) - the circuit associated with the affected cell is then simply no longer actuated; reloading individual cells or cell groups and the entire stack is possible; the circuit is particularly effective because different parts of each circuit parts can be used repeatedly;

- The overall system is easy to expand and therefore easily scalable.

Claims

claims

1. Device for charge compensation between the individual cells (Cl to Cn) of a double-layer capacitor, in particular in a multi-voltage vehicle electrical system,

characterized ,

in that each individual cell (C1 to Cn) of the double-layer capacitor is assigned a capacitor (CIa to Cna) whose first terminal can be connected to the first terminal of the associated cell (C1 to Cn) via a first switch (SIa to Sna) and via a second switch (SIb to Snb) can be connected to the second terminal of the associated cell (Cl to Cn) and the second terminal of which is connected to the second terminals of all capacitors (Cl to Cn).

2. Apparatus according to claim 1, characterized in that in a charge balance circuit for single operation, the first and second switches (SIa to Snb) as MOS-FETs

(TIa to Tnb) are executed, the first terminals of the capacitors (CIa to Cna) with the

Source terminals of the first switching transistors (TIa to Tna) and to the drain terminals of the second switching transistors (TIb to Tnb) are connected, the second terminals of the capacitors (CIa to Cna) are connected to each other in a node (A), the drain Terminals of the first switching transistors (TIa to Tna) are connected to the first terminals of their associated cells (Cl to Cn), the source terminals of the second switching transistors (Tlb to Tnb) are connected to the second terminals of their associated cells (Cl to Cn), and in parallel to each cell (Cl to Cn) a series connection of two resistors (Rla-Rlb to Rna-Rnb ) is arranged, whose connection points are connected to the first terminals of their associated capacitors (CIa to Cna).

3. A device according to claim 2, characterized in that for differential operation, a second, parallel to the first arranged charge equalization circuit is provided, wherein the first and second switches are designed as MOS FETs (Tic to Tnd), the first terminals of the capacitors (CIb to Cnb) are connected to the sources of the first switching transistors (Tic to Tnc) and to the drains of the second switching transistors (Tld to Tnd), the second terminals of the capacitors (CIb to Cnb) are connected to each other in a node (B) are connected, the drain terminals of the first switching transistors (Tic to Tnc) are connected to the first terminals of their associated cells (Cl to Cn), the source terminals of the second switching transistors (TId to Tnd) with the second terminals of their associated Cells (Cl to Cn) are connected, and parallel to each cell (Cl to Cn) a series connection of two resistors (Rlc-Rld to Rnc-Rnd) angeord is net whose connection points are connected to the first terminals of their associated capacitors (CIb to Cnb).

4. Device according to one of claims 2 or 3, characterized in that as a drive circuit for each switching transistor (TIa to Tnd) is provided, wherein a series connection of a logic buffer (ICIa to Icnd) and a coupling capacitor (ClIa to Clnd) is provided, via which the drive signal (Tla-A to Tnd-on) to the gate terminal of the switching transistor (TIa to Tnd) can be fed, and between the source and gate terminal a Zener diode (DIa to Dnd) is provided, the cathode of which is connected to the gate terminal, and a resistor (RlIa to Rind) is connected in parallel to the Zener diode (DIa to Dnd).

5. The device according to claim 2, characterized in that a Nachladeschaltung is provided, which has a Nachladekondensator (Cv) whose one terminal is at reference potential (GND) and which via a switchable current source (Q) with a constant current from an external energy source ( Vbat) can be charged via a switch (SB) such that a voltage divider comprising two resistors of the same size (Rvla-Rv2a to Rvna-Rvnb) is arranged for simple operation in parallel with the recharging capacitor (Cv), a switching transistor (Tva) is provided whose drain Terminal is connected to the connection point of the current source (Q) and the post-discharge capacitor (Cv) and whose source terminal is connected to the node (A) and simultaneously to the connection point of the two resistors (Rvla-Rv2a to Rvna-Rvnb), and a switching transistor (Tvb) whose drain terminal is connected to the node (A) and whose source terminal is connected to reference potential (GND).

6. Apparatus according to claim 2 or 3, characterized in that for differential operation a second, parallel to the first arranged Nachladeschaltung is arranged, which one parallel to the Nachladekondensator (Cv) arranged

Voltage divider comprising two equal resistors (RvIc-Rv2d to Rvnc-Rvnd), a switching transistor (Tva) having its drain terminal connected to the junction of the current source (Q) and the post-discharge capacitor (Cv) and whose source terminal connected to the Node (B) and simultaneously connected to the connection point of the two resistors (Rvla-Rv2a to Rvna-Rvnb), and a switching transistor (Tvb) whose drain terminal is connected to the node (B) and its source Terminal connected to reference potential (GND).

7. The device according to claim 2, characterized in that a known per se, designed as a synchronous demodulator rectifier is provided, whose input is connected in single operation with the node (A) of the charge balancing circuit.

8. Apparatus according to claim 3 or 7, characterized marked, that in differential operation two switches (Schla, Schlb) are provided which in one position the one input of the rectifier with node (A) of the charge equalization circuit and the other input ( B) of the rectifier connects to node (B) of the charge balancing circuit and in the other position connects one input (A) of the rectifier to node (B) of the charge balancing circuit and the other input (B) of the rectifier to node (A) of the charge balancing circuit; wherein the two switches (Schla, Schlb) are switched synchronously by the drive signal (Tla-Ein to Tna-Ein) of the switching transistor (TIa to Tna), which is associated with the cell (Cl to Cn) whose charging voltage is to be measured.

9. Device according to one of the preceding claims, characterized in that when nonexistent Nachladeschaltung a resistor is provided in the single mode, whose one ner connection with node (A) of the charge equalization circuit is connected, and its other terminal to a reference voltage (Vref) is, in differential operation for each node (A, B) of the charge equalization circuit, a resistor is provided, whose one terminal is connected to the node (A, B), and whose other terminal is connected to a reference voltage (Vref).

10. A method of operating the device according to one of claims 1 to 9, characterized in that in simple operation for measuring the charging voltage of a cell (here Cl), the switching transistors associated with this cell (TIa and TIb) are alternately turned on at a predetermined frequency and in that the rectangular AC voltage in the rectifier which thereby arises at the node (A) at the rectifier is translated to a DC voltage corresponding to the charging voltage (V _c i for cell Cl) with reference to reference potential (GND), which is subsequently stored.

11. The method according to claim 10, characterized in that at differential operation for measuring the charging voltage of a cell (here Cl) of this cell associated switching transistors (TIa and TId) simultaneously and in opposite phase to the switching transistors (TIb and Tic) are conductively controlled arise at the nodes (A) and (B) to each other opposite-phase rectangular alternating voltages whose

Peak-to-peak value in the rectifier with respect to a DC voltage corresponding to the charging voltage (V _c i for cell Cl) with reference is translated to reference potential (GND), which is then stored.

12. The method according to claim 10 or 11, characterized in that the charging voltages (V _C i to V _Cn ) of all cells (Cl to Cn) are measured and stored at periodic intervals.

Method according to claim 10 or 11, characterized in that the stored values of the charging voltages (V _C χ to V _Cn ) of all cells are periodically compared to their differences with each other and to a predetermined maximum value, and that if one or more Differences above a predetermined limit value or if one or more values are above the predetermined maximum value, successive charge equalization between the highest and the lowest loaded cell (Cl to Cn) is performed.

14. The method according to claim 12 or 13, characterized marked, that the sum of the stored values of the charging voltages (V _c i to V _Cn ) is formed and compared with a predetermined minimum value, and that falls below this minimum value individual cells, cell groups or the entire double-layer capacitor can be recharged from an external power source.

15. The method according to claim 13, characterized in that in single operation for charge equalization of a higher charged cell (Cl) to a lower charged cell (Cn) with a predetermined frequency in a first step, the first switching transistor (TIa) of the higher charged cell (Cl) and the first switching transistor (Tna) of the lower charged cell (Cn) are conductively controlled, whereby the series connected cells (Cl) and (Cn) associated capacitors (CIa and Cna) on a

Voltage Vl = V _C i + V _C2 + ... + V _Cn _i to be charged, and in a second step, the first switching transistors (TIA) and Tna) non-conductive and then the second switching transistor (TIB) of the highly charged cell (Cl ) and the second switching transistor (Tnb) of the lower charged cell (Cn) are conductively controlled, the cells (C2) to (Cn) having a lower voltage V2 = V _C2 + ... + V _Cn _i + V _Cn than the voltage Vl to the capacitors (CIa and Cna), whereby a balancing current of the two cells to be transposed cells (Cl and Cn) associated capacitors (CIa and

CIn) flows into the lower charged cell (Cn), and that this process is repeated until both cells (Cl and Cn) have approximately the same charging voltage.

16. The method according to claim 13 or 15, characterized in that in differential operation in the first step, the first switching transistors (TIa and Tna) and simultaneously the second switching transistors (TID and Tnd) are conductively controlled, and in the second step, the second switching transistors (TIb and Tnb) and simultaneously the first switching transistors (Tic and Tnc) are conductively controlled.

17. The method according to claim 13, characterized in that for a rapid charge equalization in the double-layer capacitor in the first step, all the first switching transistors (TIa to Tna) of one side and at the same time all second

Switching transistors (TId to Tnd) of the other side are conductively controlled, and in the second step, all the second switching transistors (TIb to Tnb) of the one side and simultaneously all the first switching transistors (Tic to Tnc) of the other side are conductively controlled.

18. The method according to claim 14, characterized in that for recharging a cell (here Cl) of the recharging capacitor (Cv) via the switchable current source (Q) and a switch (SB) from an external power source (Vbat) with a constant current to a predetermined Voltage is charged, and then in the single mode by simultaneous Leitendsteuern of

Switching transistor (Tva) and of the cell to be charged (here Cl) associated with the first switching transistor (TIa), the differential operation by simultaneous Leitendsteuern the switching transistor (Tva), the cell to be charged (here Cl) associated with the first switching transistor (TIa), the switching transistor ( Tvd) and the second switching transistor associated with the cell (Cl) to be charged

(TID)

Charge from the recharging capacitor (Cv) is transferred to the cell to be charged (Cl).

19. The method according to any one of claims 10 to 18, characterized in that all method steps are performed programmatically by means of microprocessors.