Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L29/42312—Gate electrodes for field effect devices
  • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
  • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
  • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
  • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
  • H01L31/035236—Superlattices; Multiple quantum well structures
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
  • H01L31/1812—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table including only AIVBIV alloys, e.g. SiGe

Definitions

• the invention relates to a method of manufacturing a semiconductor device with a substrate and a semiconductor body of silicon which is provided with at least one semiconductor element, wherein in the semiconductor body a semiconductor region of a material comprising a mixed crystal of silicon and another group IV element is formed, which semiconductor region is buried by deposition of a silicon layer.
• the invention also relates to a semiconductor device obtained with such a method.
• MOSFET Metal Oxide Semiconductor Field Effect Transistor
• IC Integrated Circuit
• a method as mentioned in the opening paragraph is known from the publication entitled "A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors” by Kyoung Hwan Yeo et al. that has been published in IEEE Electron Device Letters, vol. 25 no. 6, June 2004.
• a SiGe layer is deposited epitaxially on a semiconductor substrate and on said layer a silicon layer is deposited.
• a mask is provided on the silicon layer, which is provided with an opening. In the opening both the silicon layer and the SiGe layer are removed by etching. Subsequently, after removal of the mask, a further silicon layer is provided in the etched opening in the silicon and SiGe layer.
• a drawback of such a method is that the device obtained often contains defects. It is therefore an object of the present invention to avoid the above drawback and to provide a method, which results in devices with low numbers of defects and which is moreover simply to apply.
• a method of the type described in the opening paragraph is characterized by the following steps: on a surface of the semiconductor body a mask comprising an opening is provided; a semiconductor region of a material comprising a mixed crystal of silicon and another group IV element is selectively deposited in the opening; the mask is at least partly removed; and subsequently a silicon layer is deposited uniformly on the surface of the semiconductor body.
• the present invention is based on the recognition that the defects mentioned, are caused by epitaxy of the silicon layer into an etched structure.
• Etching the structure results in surface irregularities and surface roughness, which results in the creation of defects during subsequent epitaxial growth on such a surface.
• a mask e.g. of silicon dioxide
• the mask can very easily be removed, e.g. by etching, which can be done easily and selectively towards the semiconductor body.
• the creation of surface irregularities and surface roughness is largely avoided.
• the semiconductor region is covered by a silicon layer by uniformly depositing such a layer, e.g. by epitaxy. Since such a deposition is on a very smooth and defect free surface, the deposition does not result in the creation of defects. Removal of the semiconductor region as a sacrificial layer and replacement thereof by e.g. silicon dioxide may further easily be accomplished.
• the resulting structure comprising the semiconductor region buried by a silicon layer is planarized.
• the planarizing step is larger if the thickness of the semiconductor region is relatively large.
• a silicon region is selectively deposited in the opening of the mask.
• the semiconductor region is protected by a silicon region during subsequent processing.
• a silicon layer favors the subsequent selective deposition in the opening of the mask of a further semiconductor region comprising for example SiGe.
• a further semiconductor region of a material comprising a mixed crystal of silicon and another group IV element buried by silicon is formed, at a higher level than the semiconductor region and in a similar way as the semiconductor region has been formed.
• the method according to the invention allows for the realization of 3-d structures in which overlying semiconductor regions can be used as sacrificial region in the making of 3-d device structures.
• the further semiconductor region(s) - preferably separated from each other by silicon layers - are all deposited, preferably within one single deposition process, within the opening of the mask.
• the further semiconductor region(s) are formed in separate deposition processes/steps. This has the important advantage that the semiconductor regions do not need to coincide but may be positioned quite differently viewed in projection.
• the semiconductor regions are positioned such that they at most partly overlap each other. In this way many different 3-d device structures are easily obtainable.
• each semiconductor region is preferably followed by the uniform growth of a silicon layer, which buries the semiconductor region in question.
• the planarization step may be accomplished after each set of depositions comprising deposition of a semiconductor region and deposition of a burying silicon layer, however, the planarization step is preferably performed only once at the end of the total growth/deposition process.
• the further semiconductor region advantageously also is a SiGe region.
• a hole is formed that reaches the semiconductor region and the material comprising the mixed crystal of silicon and the other group IV element is removed by selective etching resulting in a cavity at the location of the semiconductor region.
• This sacrificial use of the buried semiconductor region of e.g. SiGe offers interesting possibilities for device structuring.
• the hole and the cavity are filled with an electrically insulating material. This allows for several device structures.
• the semiconductor element is formed in a silicon part of the semiconductor body, which is surrounded by the filled hole and is situated above the filled cavity. In this way the semiconductor element is completely electrically isolated from the remainder of the semiconductor body.
• a preferred semiconductor element in such a structure is a high- voltage field effect transistor for which such an isolation structure is very beneficial.
• a cavity filled with insulating material can be useful, e.g. to isolate semiconductor elements or parts thereof in the stack from each other.
• the cavity is filled with an electrically conducting material.
• an electrically conducting material like the use of such a cavity as the gate electrode in a field effect transistor or in a stack of field effect transistors positioned on top of each other.
• a single field effect transistor may be provided advantageously in this manner with two gate electrodes.
• the use of a cavity filled with an insulating material and the use of a cavity filled with a conducting material is possible.
• These possibilities stem from the fact that all semiconductor regions of e.g. SiGe can be reached by separately made holes in the surface of the semiconductor body, the e.g. SiGe material thereof can be removed in separate etching steps and the resulting cavities can be filled in separate deposition steps.
• the e.g. SiGe regions are not used as sacrificial layers but as part of the device structure more in particular as parts of the semiconductor element.
• the SiGe regions are preferably made in the form of coupled quantum wells. In this way, an infrared detector can be obtained comprising the coupled quantum wells that are contacted separately by semiconducting regions sunken in the surface of the semiconductor body.
• the silicon layer(s) and the semiconductor region(s) of the material comprising the mixed crystal of silicon and another group IV element are formed by epitaxy.
• the preferred other group IV element is Germanium, other elements are feasible.
• SiC could be used as the material of one ore more of the (further) semiconductor regions.
• the thickness of the semiconductor region(s) is preferably chosen between 5 and 50 nm and the Germanium content thereof is preferably chosen between 20 and 40 at. %. In this way, selective etching is most easily obtained on the one hand and on the other hand avoiding the creation of defects by the strain induced by the lattice mismatch, is still possible.
• a preferred material for the mask is silicon dioxide. In this way, a selective deposition process is more easily realized. Parts of the mask may be left after formation of the SiGe region and a protecting silicon layer on top thereof, e.g. to offer the possibility of holes in the surface of the semiconductor body and towards the semiconductor region by selective etching of such a remaining mask part. However, preferably the mask is removed completely.
• the device is subjected to a thermal treatment in a hydrogen atmosphere, preferably at a temperature above 850°C. In this way, the presence of oxygen atoms at the growth interface is avoided as good as possible.
• the invention also comprises a semiconductor device obtained by a method according to the invention.
• FIGS. IA through 1OC are views of a first semiconductor device at various stages in its manufacture by means of a first embodiment of a method in accordance with the invention, wherein the A Figure is a top view, the B Figure is a sectional view along the line B-B in the A Figure and the C Figure is a sectional view along the line C-C in the A Figure, Figs.
• IA through 16B are sectional views of a second semiconductor device at various stages in its manufacture by means of a second embodiment of a method in accordance with the invention, wherein the A Figure is a top view and the B Figure is a sectional view along the line B-B in the A Figure,
• Figs. 17 through 25 are sectional views of a third semiconductor device at various stages in its manufacture by means of a third embodiment of a method in accordance with the invention.
• Figs. 26 through 30 are sectional views of a fourth semiconductor device at various stages in its manufacture by means of a fourth embodiment of a method in accordance with the invention
• Figs. 31 A through 33B are views of a fifth semiconductor device at various stages in its manufacture by means of a fifth embodiment of a method in accordance with the invention
• Figs. 3 IA-H and 33 A-B being sectional views
• Fig. 32 being a 3-d top view.
• Figs. IA through 1OC are views of a first semiconductor device at various stages in its manufacture by means of a first embodiment of a method in accordance with the invention, wherein the A Figure is a top view, the B Figure is a sectional view along the line B-B in the A Figure and the C Figure is a sectional view along the line C-C in the A Figure.
• the semiconductor device manufactured in this example is a field effect transistor with a dual gate structure.
• a substrate 11, here of silicon is provided with a mask 3 provided with an opening 4.
• CVD Chemical Vapor Deposition
• a semiconductor region 1 is formed by means of selective epitaxy, which region 1 in this example is made of SiGe with a thickness of 20 nm and a Germanium content of 20 at.%.
• a silicon region 5 is formed and provided with, for example, a thickness of 10 nm and on top of this region 5 a further semiconductor region 6 of SiGe is formed with preferably the same properties as the semiconductor region 1.
• the mask 3 is removed by selective etching, e.g. in a diluted HF solution.
• the device 10 is then subjected to a thermal treatment, e.g. at 900 0 C and in a hydrogen ambient.
• CMP Chemical Mechanical Polishing
• a pad oxide layer 13 of a thermal oxide and a silicon nitride layer 14 are deposited on the device 10, the latter using CVD and with a thickness of, for example, 10 nm and 115 nm respectively.
• a pattern is formed by means of photolithography and etching in order to form a trench region 15 which is etched selective towards SiGe but will laterally surround both the lower and upper SiGe regions 1, 6 as well as the intermediate silicon region 5.
• a contact opening 16 is formed in the device by means of photolithography and etching.
• the contact opening 16 reaches as far as the lower SiGe region 1 of the SiGe/Si/SiGe stack 1, 5, 6.
• the SiGe of the SiGe regions 1, 6 is removed by means of selective isotropic etching using an etchant comprising CF 4 and O 2 .
• an etchant comprising CF 4 and O 2 .
• the walls of the cavities 8, 9 are provided with gate oxide layers 8 A, 9 A that are formed by means of a thermal oxidation in an oxygen ambient.
• another insulating material such as high-k
• ACVD Atomic Layer CVD
• the cavities 8, 9 are filled with a conducting material, in this example polycrystalline silicon formed by CVD.
• a conducting material in this example polycrystalline silicon formed by CVD.
• a polycrystalline silicon contact region 17 is formed by means of photolithography and etching.
• the hard mask comprising layers 13, 14 are removed and source and drain regions 20, 21 are formed by means of implantation.
• a FET Field Effect Transistor
• the semiconductor element in the device 10 having a dual gate structure 8B, 9B with a common electrical connection, which gates 8B, 9B are separated through gate oxides 8A, 9A from a channel region 22.
• the channel region 22 is contaminated by the required implantation in that a surface part of the semiconductor body 12 at the locations of the source and drain regions 20, 21 is removed by etching. This however is not shown in the drawing.
• Figs. 1 IA through 16B are sectional views of a second semiconductor device at various stages in its manufacture by means of a second embodiment of a method in accordance with the invention, wherein the A Figure is a top view and the B Figure is a sectional view along the line B-B in the A Figure.
• the semiconductor device manufactured in this example is stack of three field effect transistors.
• a semiconductor body 12 is provided with 6 SiGe regions 31, 31, 32, 33, 34, 35, 36 each of these regions being comparable with respect to thickness and composition with the SiGe regions 1, 6 of the previous example.
• Each of these regions 31-36 is formed in a separate growth process using a silicon dioxide mask as in the previous example provided with an opening in which opening the SiGe region in question is deposited.
• a silicon cover region is formed in the same process on top of the SiGe region in question which is comparable with silicon region 5 of the previous example.
• the silicon region deposited on top of SiGe region 34 should be thicker (approximately two times) in comparison with the silicon region deposited on top of the SiGe region 31.
• the reason for this is to make sure that the thin silicon region between e.g. SiGe regions 31 and 35 is completely replaced with oxide during oxidation of a later formed cavity in region 35, while the silicon region between e.g. SiGe regions 34 and 31 is sufficiently thick, so that there is sufficient layer of silicon left to form the transistor channel even after oxidizing the cavity of region 34.
• the masks used for forming the SiGe regions 31-36 are chosen such that these form gate regions 31, 32, 33 and isolation plane regions 34, 35, 36, each viewed in projection overlapping each other.
• the mask used is removed and a new mask is formed and patterned for the next growth process.
• the burying silicon layer 2 is formed after each growth process, however it is possible and more simple to grow one single burying silicon layer 2 after formation of the last gate region 33, followed by one single planarization step.
• holes 40 are etched reaching through the isolation plane regions 34-36 followed by removal of the corresponding SiGe regions by means of selective isotropic etching as in the previous example.
• the isolation plane regions 34-36 are filled with an insulating material 41 in this example by using a thermal oxidation in oxygen containing atmosphere.
• contact holes 3 IB, 32B, 33B are formed in the contact regions 31A-33A of the gate regions 31-33 followed by (see Figs. 15A and 15B) selective isotropic SiGe etching by which cavities are formed at the locations of the gate regions 31-33.
• the walls of these cavities are provided with a gate dielectric in this example, as in the previous one, formed by a thin thermal oxide and are then filled with a conducting material as in the previous example comprising poly-Si.
• source and drain regions 20, 21 are shown of the individual transistor that may be formed e.g. by implantation. It is to be noted that these regions 20, 21 already have been formed at an earlier stage of the manufacturing, i.e. by implantations after growth of each layer 31, 32, 33. In an alternative favorable method these heavily doped regions, are made by a growth process, e.g. after growing region 31, the following overgrowing (thin) silicon region could be heavily doped with P++ or N++, the part above region 31 being removed afterwards by means of a planarization step.
• Figs. 17 through 25 are sectional views of a third semiconductor device at various stages in its manufacture by means of a third embodiment of a method in accordance with the invention.
• the semiconductor device manufactured in this example is a high voltage field effect transistor with complete dielectric isolation.
• a substrate 11, here of silicon is provided with a mask 3 provided with an opening 4.
• the mask 3 in this example is made of silicon dioxide and is formed by depositing a uniform layer by means of CVD, which is subsequently patterned using photolithography and etching.
• a semiconductor region 1 is formed by means of selective epitaxy, which region 1 is made of SiGe in this example with a thickness of 20 nm and a Germanium content of 20 at.%.
• the mask 3 is removed by selective etching, e.g. in a diluted HF solution.
• the device 10 is then subjected to a thermal treatment, e.g. at 900 0 C in a hydrogen ambient.
• a uniform silicon layer 2 is deposited over the selectively grown structure followed by a planarization step, e.g. using CMP.
• a pad oxide layer 13 of a thermal oxide and a silicon nitride layer 14 are deposited on the device 10, the latter using CVD and for example with a thickness of 10 nm and 115 nm respectively.
• a pattern is formed by means of photolithography and etching in order to form trench regions 15 which are formed by means of etching of silicon selectively with respect to SiGe, for example using an etchant comprising HBr.
• the trench regions 15 run all perpendicular to the plane of the drawing.
• the SiGe region 1 is removed by selective etching, using the same selective and isotropic etchant as in the previous examples and resulting in a cavity IA at the location of the SiGe region 1.
• the cavity IA is filled with an insulating material like silicon dioxide e.g. by means of thermal oxidation as in the previous examples.
• an insulating material like silicon dioxide e.g. by means of thermal oxidation as in the previous examples.
• other trenches may be etched similar to the trenches 15 but now running parallel to the plane of the drawing.
• Fig. 25 the hard mask comprising layers 13, 14 are removed and the semiconductor element - not shown in the drawing - and in this example comprising a high- voltage FET is formed in one or more of the islands 2 of silicon.
• the manufacture of the semiconductor element in this merely comprises conventional steps and therefore is not further elucidated.
• Source and drain regions 20, 21 are formed by means of implantation.
• a device 10 with high- voltage FETs is obtained which are fully electrically isolated from adjacent and subjacent parts of the semiconductor body 12.
• Figs. 26 through 30 are sectional views of a fourth semiconductor device at various stages in its manufacture by means of a fourth embodiment of a method in accordance with the invention.
• the device 10 of this example comprises a fully depleted MOSFET as the semiconductor element.
• the device 10 already comprises the SiGe region 1 as in the previous examples and which is formed e.g. as discussed in the previous example with the aid of Figs. 17-21.
• the same reference numerals are used here as in that example.
• a cavity IA is formed by forming a hole in the semiconductor body 12 followed by selective etching of the SiGe region 1. Subsequently (see Fig. 28) the cavity IA is filled by an oxide layer by a thermal oxidation followed by (see Fig. 29) filling of the trenches 15 with silicon dioxide forming STI regions 15A followed by planarization and removal of the nitride layer 14. Finally (see Fig. 30) the field effect transistor F is formed with in itself usual steps. The deep source and drain regions 20, 21 are formed in the silicon region between the STI regions 15A and the buried isolation region IA.
• Figs. 31 A through 33B are views of a fifth semiconductor device at various stages in its manufacture by means of a fifth embodiment of a method in accordance with the invention, Fig. 32 being a 3-d top view and Figs. 3 IA-H, 33 A and 33B being sectional views.
• the device here comprises an infrared detector diode comprising a number of coupled SiGe quantum-wells.
• a first buried semiconductor region 1 of SiGe is formed in a semiconductor body of silicon.
• the silicon is N type doped with about 5el5 cm “3 and the SiGe is P+ typed doped with Iel8 cm “3 , the Ge content here is about 20% and thickness about 10 nm.
• the thickness of the silicon layers is between 5-10 nm, as discussed in previous examples using a mask 3 with opening 4.
• Figs. 31D- G further SiGe regions 111 are formed in a similar way using masks 33 with opening 44.
• sunken p-type doped regions 50, 51 are formed in a conventional manner contacting the two overlapping SiGe regions 1, 111.
• a high-k layer can be used that is deposited through atomic layer CVD.
• the conductive polysilicon can be replaced with metals also deposited by atomic layer CVD etc.
• the buried dielectric in the fourth embodiment maybe other dielectric than oxide, e.g. nitride and it could be also a combination of a thin oxide and semi- insulating material like SIPOS to create extra stress in the silicon channel above etc.
• a conducting material e.g. nitride
• a conducting compound and in particular a metal form attractive choices.
• a high-k material may advantageously be selected.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Ceramic Engineering (AREA)
• Electromagnetism (AREA)
• Chemical & Material Sciences (AREA)
• Nanotechnology (AREA)
• Biophysics (AREA)
• Optics & Photonics (AREA)
• Crystallography & Structural Chemistry (AREA)
• Manufacturing & Machinery (AREA)
• Life Sciences & Earth Sciences (AREA)
• Thin Film Transistor (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Element Separation (AREA)
• Recrystallisation Techniques (AREA)

Priority Applications (1)

Applications Claiming Priority (3)

Publications (1)

Family

ID=37265894

Family Applications (1)

Country Status (5)

Families Citing this family (3)

Family Cites Families (6)

• 2006
  • 2006-06-21 JP JP2008519028A patent/JP2008544563A/ja not_active Withdrawn
  • 2006-06-21 EP EP06765814A patent/EP1900037A1/en not_active Withdrawn
  • 2006-06-21 WO PCT/IB2006/052013 patent/WO2007000690A1/en not_active Application Discontinuation
  • 2006-06-21 CN CNA2006800231851A patent/CN101208804A/zh active Pending
  • 2006-06-28 TW TW095123245A patent/TW200705517A/zh unknown

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events