EP1880417A2 - Mit geneigten kontaktstellen ausgestattete siliziumchips und den siliziumchip umfassendes elektronisches modul - Google Patents
Mit geneigten kontaktstellen ausgestattete siliziumchips und den siliziumchip umfassendes elektronisches modulInfo
- Publication number
- EP1880417A2 EP1880417A2 EP06743608A EP06743608A EP1880417A2 EP 1880417 A2 EP1880417 A2 EP 1880417A2 EP 06743608 A EP06743608 A EP 06743608A EP 06743608 A EP06743608 A EP 06743608A EP 1880417 A2 EP1880417 A2 EP 1880417A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- chip
- integrated circuit
- cavity
- active face
- lateral contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 13
- 229910052710 silicon Inorganic materials 0.000 title description 13
- 239000010703 silicon Substances 0.000 title description 13
- 239000004020 conductor Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 31
- 238000005520 cutting process Methods 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 238000007493 shaping process Methods 0.000 claims description 2
- 241000270295 Serpentes Species 0.000 abstract 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 11
- 230000008021 deposition Effects 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 6
- 239000003292 glue Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000002604 ultrasonography Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 229910017214 AsGa Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000010329 laser etching Methods 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004753 textile Substances 0.000 description 1
- 238000003856 thermoforming Methods 0.000 description 1
Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Definitions
- the present invention relates to a method of manufacturing a semiconductor chip and a method of manufacturing an electronic module comprising a substrate, at least one conductive element integral with the substrate and a semiconductor chip.
- the invention relates in particular to the manufacture of an electronic module of small thickness and more particularly a module of the "contactless" type making it possible to produce various types of portable contactless objects, such as contactless smart cards, electronic badges without contact, contactless electronic tags, etc.
- a module can also be inserted into identification objects such as passports or identity cards.
- An integrated circuit is in the form of a silicon chip (chip) which has an active face on which is implanted an integrated circuit region, forming the integrated circuit itself, and contact pads electrically connected to the region of integrated circuit.
- chip silicon chip
- An electronic module is made by electrically connecting the contact pads of the chip to one or more conductors integral with an interconnection support, which are themselves connected to other electronic components.
- the conductor (s) of the interconnection support are generally not connected to other electronic components (except passive capacitor-type electrical components or self-inductance) but form an antenna circuit providing the interface between the integrated circuit and the external medium for receiving and / or transmitting data.
- the chip is generally mounted bare on the interconnection support, without being previously arranged in a protective housing, and the electrical connection of the contact pads with the interconnection support is generally obtained by means of the "chip and wire” technique. (“chip and wire”) or the "flip chip” technique.
- the chip is fixed on the interconnection support with its active face facing upwards, and its contact pads are connected to the conductors of the interconnection support by means of son son welded with ultrasound ("ultrasonic wire”). bonding ").
- the chip is mounted upside down on the interconnection support and its contact pads are directly soldered on corresponding conductive pads of the interconnection support, for example by pressing, application of ultrasonic vibrations, fusion of a material such as tin lead or bonding (by means of an electrically conductive glue).
- the mounting of a chip by ultrasonic wiring has the disadvantage that the loops formed by the wiring son generally have a height greater than one thickness of the chip and increase the total thickness of the micromodule.
- the wires must be embedded in a protective resin which increases the overall thickness of the assembly.
- the mounting of a chip "flip-chip” is often preferred to ultrasonic wiring.
- the flip-chip technique does not make it possible to produce electronic modules of which the thickness is sufficiently small to suit all applications, including non-contact type modules to be integrated in supports of very small thickness (paper sheet, cardboard, plastic sheets ...), despite the recent progress made in the thinning of the chips and the use of new materials (papers, polymers) to form very thin substrates.
- Another parameter involved in the final thickness of a "flip chip” module is the thickness of the conductive material beads ("Bumps", "Bail”, etc.) that interpose between the contact pads of the chip. and the surface of the interconnect support.
- an object of the present invention is to provide a semiconductor chip structure for making thin electrical connections between the chip and an interconnect medium.
- Another object of the present invention is to provide a thin electronic module comprising such a chip.
- an idea of the present invention is to provide a chip having inclined lateral contact pads which extend below a plane passing through the active side of the chip. Such contact pads may be connected laterally to a conductive element of an interconnection support, by means of a conductive material having no excess thickness relative to the plane of the active face of the chip. Thus, the electrical connection between the chip and an interconnection support does not increase the thickness of an electronic module produced by means of such a chip.
- Another idea of the present invention is to arrange the chip in a cavity in the interconnect carrier such that a portion of the thickness of the chip is within the thickness of the carrier. The conductors of the interconnection support are then substantially at the same level as the contact pads of the chip and can be connected thereto by a simple conductive bridge of small thickness. More particularly, the present invention provides a method of manufacturing at least one semiconductor chip, comprising a step of implanting an integrated circuit region on an active side of the chip. According to the invention, the method comprises:
- an inclined lateral contact pad electrically connected to the integrated circuit region and extending below the plane of the active face of the chip.
- the lateral contact area is formed by depositing a layer of an electrically conductive material extending from the inclined edge to the active face of the chip and covering a range of contact located in the integrated circuit region.
- the lateral contact area is made by depositing a layer of an electrically conductive material extending from the inclined edge to the active face of the chip where it enters the integrated circuit region to be connected thereto.
- the inclined edge is formed by forming an inclined-walled flared cutting path in a semiconductor wafer, and then cutting at least one edge of the wafer into the wafer along the cutting path .
- the method comprises the following steps:
- the method comprises a step of thinning the semiconductor wafer before cutting it.
- the invention also relates to a semiconductor chip comprising an active face on which an integrated circuit region is implanted.
- the chip comprises at least one inclined lateral contact pad extending below the plane of the active face of the chip and electrically connected to the integrated circuit region.
- the range 'inclined side contact is formed by an electrically conductive material which extends up to the active face of the chip and covers a contact pad of the integrated circuit region.
- the inclined lateral contact area is formed by an electrically conductive material which extends to the active face of the chip where it is electrically connected to the integrated circuit region.
- the invention also relates to a method of manufacturing an electronic module comprising a substrate, at least one conductive element integral with the substrate and a chip as defined above comprising at least one inclined lateral contact pad.
- the method comprises the following steps: - producing a cavity in the substrate,
- the method comprises a step of depositing, in the cavity, a material for fixing the chip.
- the method comprises a step of making a conductive bridge between the inclined lateral contact pad and the conductive element, by depositing a conductive material.
- the material forming the conductive bridge is deposited so as not to have an excess thickness extending above the plane of the active face of the chip.
- the method comprises a step of simultaneous realization of the conductive element and the conductive bridge.
- the cavity is made by a shaping treatment of the substrate.
- the cavity is made by forming the substrate by assembling at least two layers of a material, a layer forming the bottom of the cavity and the other layer having an orifice delimiting the walls of the cavity.
- the invention also relates to an electronic module comprising a substrate, at least one conductive element integral with the substrate and a semiconductor chip comprising an active face on which an integrated circuit region is implanted.
- the substrate comprises a cavity in which the chip is arranged
- the chip comprises at least one inclined lateral contact pad extending below the plane of the active face of the chip, and the inclined lateral contact pad is electrically connected to the conductive element.
- the chip is held in the cavity by a fixing material.
- the inclined lateral contact pad is substantially in the same plane of an edge of the cavity.
- the module comprises, between the inclined lateral contact pad and the conductive element, a conductive bridge formed by a conductive material that does not include an excess thickness extending above the plane of the active side of the chip.
- the conductive element forms an antenna.
- FIG. 1A is a view from above of a silicon wafer on which integrated circuits are collectively produced
- FIG. 1B is a view in section and perspective of a portion of the silicon wafer of FIG. 1,
- FIG. 2 is a cross-sectional view of a portion of the silicon wafer of FIG. 1, and illustrates a step of the chip manufacturing method according to the invention
- FIG. 3 is a perspective view of a FIG. chip according to the invention after cutting the silicon wafer of Figure 1
- - Figures 4A and 4B are cross-sectional views illustrating a method of manufacturing an electronic module according to the invention.
- FIG. 1A represents a silicon plate 1 seen from above and FIG. 1B shows a portion of the plate 1 seen in section and in perspective.
- Plate 1 receives a plurality of integrated circuit regions 3 collectively implanted in silicon in conventional manner.
- the integrated circuit regions 3 are delimited by vertical and horizontal cutting paths 2, along which the plate 1 will subsequently be cut to separate the integrated circuit regions and obtain individual integrated circuits in the form of chips.
- contact pads HA, HB are generally formed which are connected to the regions 3 via orifices passing through a protective layer deposited on the entire surface of the plate. silicon.
- each integrated circuit region receives two contact pads HA, HB intended for example to be connected to the terminals of an antenna coil.
- These contact pads HA, HB are conventionally produced, for example by metal deposition via a metallization mask in the presence of a metal vapor or by chemical deposition and etching of a metal layer.
- the cutting paths 2 have the shape of grooves with flared profile having inclined walls, and extend over a portion of the thickness of the plate 1.
- the plate 1 has a thickness of a few hundred micrometers and the paths cutting 2 have a depth of the order of a few micrometers - typically 5 microns - and a width of the order of 60 to 100 micrometers.
- the slope of the groove at its edges is for example of the order of 135 ° with respect to the upper face of the plate 1.
- electrically conductive tracks 13A 7 13B are formed on the inclined edges of the cutting paths 2, opposite each contact pad HA, HB. These pads 13A, 13B are intended to form lateral contacts on the future chips. To connect each range 13A, 13B to the corresponding contact pad HA, HB, and in order to avoid a subsequent interconnection step, the pads 13A 7 13B advantageously extend to the ranges HA, HB and cover them, thus ensuring optimum electrical contact with them.
- the bands 13A, 13B in the form of strips are produced by deposition of a conductive material 13.
- This step comprises firstly the formation of a mask of conventional metallization, covering the upper face of the plate 1 with a layer of photosensitive polymer which is insolated and developed to open windows corresponding to the areas to receive the conductive material 13.
- the conductive material 13 is then deposited by any appropriate method, in particular ionic or chemical deposition, or deposition of a conductive ink.
- Deposition of the conductive material 13 is of course carried out after having previously deposited an insulating layer on the cutting paths (not shown) in order to electrically isolate the conductive material 13 from the silicon.
- the metallization mask comprises metallization windows extended so as to form conductive strips which pass through the cutting paths and connect contact pads belonging to regions of different integrated circuits but lying opposite one another.
- the range HA of an integrated circuit region 3 is connected to the range HB of another integrated circuit region 3 by a conductive strip 13 which passes through the cutting path.
- the conductive material 13 does not fill completely the groove, but the shape of 'thereof, so that the upper face of the conductive strips has substantially the same taper as the inclined edges of the groove .
- the plate 1 is then cut along the central part of the cutting paths 2, marked by lines 15 in dashed lines in FIG. 2, in order not to destroy the inclined walls of the cutting paths or, at the very least, not to not destroy the part of the inclined walls closest to the regions of integrated circuits.
- the operation is conducted conventionally, by sawing, etching, laser, etc.
- the chip 3 shows a chip 1 'according to the invention obtained after cutting the plate 1.
- the chip has four side faces 6, here vertical, four inclined edges 7, and an upper face or active face 5 where is the integrated circuit region 3 and the contact pads HA, HB.
- the inclined edges 7 correspond to the walls of the cutting paths and extend between the lateral faces 6 and the active face 5, and they form a kind of beveled edges or chamfers.
- the conductive strips 13 which originally connected the contact pads of the adjacent integrated circuit regions were cut during the cutting of the plate 1 and now form two contact pads 13A, 13B according to the invention which respectively cover the contact pads HA , HB and extend respectively on two inclined edges 7A, 7B of the chip.
- the portions of the contact pads 13A, 13B covering the inclined edges 7A, 7B are widened laterally to obtain a larger connection area.
- the plate 1 Prior to cutting the plate 1, it may be subjected to a thinning step, for example by chemical and / or mechanical abrasion of its rear face.
- the thickness of the plate can thus be reduced to a value of less than 100 ⁇ m, and advantageously of the order of 50 ⁇ m.
- the contact pads HA, HB of the integrated circuit regions and the inclined pads 13A 7 13B are manufactured simultaneously during a step unique deposition of metal through a metallization mask or by deposition of a metal layer and etching of the metal layer by means of an etching mask.
- the contact pads HA, HB of the integrated circuit regions and the inclined ranges 13A, 13B according to the invention are then combined and formed by one and the same material.
- the same manufacturing session of a batch of silicon wafers may concern several thousand chips for different applications, some of which may be intended to be connected in a conventional manner to an interconnection support.
- the silicon wafers are made conventionally and those intended to receive the pads 13A 7 13B are isolated from the batch after the final manufacturing step, the pads 13A, 13B being then made in "post-fabrication" by covering the initial contact pads 11A, HB as described above. Thanks to the inclined lateral contacts 13A, 13B, the chip 1 'can be electrically connected to the conductors of an interconnection support by a simple horizontal electrical connection of the "bridge" type, as will be described below, with no relative allowance to the plane passing through the active side of the chip.
- Such a chip is thus capable of various destinations and allows in particular to achieve a thin electronic module, on any type of interconnection support, including paper, plastic, polymer, textile, ceramic, epoxy, etc. ..
- the module is made from an interconnection support or substrate 20 of a flexible material in which a cavity 21 of dimensions slightly greater than those of the chip has been made.
- the cavity 21 was here made by embossing a layer of flexible material, or by thermoforming. As represented by dashed lines, it can also be made by assembling a bottom layer 20A forming the bottom of the cavity 21 and an upper layer 20B comprising a hole formed by punching, delimiting the side walls of the cavity 21.
- a fixing material is deposited in the cavity 21, for example a polymer adhesive 22.
- the chip 1 ' is then introduced into the cavity and is pressed using a suitable tool 30, the substrate and the chip being optionally heated to accelerate the polymerization of the glue.
- the active face 5 of the integrated circuit is substantially in the plane of the upper face of the substrate 21.
- the adhesive that leaves the cavity 21 is for example absorbed by means of a blotting paper.
- Another solution is to arrange shims 31 at the bottom of the cavity, prior to insertion of the chip 1 ', for example wedge-shaped blocks, to control the thickness of the adhesive layer at the bottom of the cavity. cavity and avoid excessive crushing of the chip that would drive glue out of the cavity.
- the contact pads 13A, 13B of the chip 11 are electrically connected to a conductive element 23 which has been previously formed on the surface of the substrate 20. This operation is carried out by producing a conductive bridge 25 between the contact pads 13A, 13B and the conductive element 23.
- the conductive bridge 25 is for example made by depositing a conductive material which passes over the gap filled with glue extending between the walls of the cavity 21 and the inclined edges of the chip.
- the conductive material may be any conventional material used in microelectronics, for example an ink, a paste or an electrically conductive adhesive.
- the chip 1 ' is for example a PICC-type non-contact integrated circuit as described by the ISO 14443 standard.
- the conducting element 23 is in this case an antenna coil formed on the upper face of the substrate 21 or formed at the same time. interior thereof and having ends extending on the surface of the substrate to the chip. Such an antenna coil may conventionally have a plurality of coplanar turns surrounding the chip.
- the chip may also be an UHF-free integrated circuit and the conductive element 23 may be a UHF antenna without winding.
- the conductive element 23 is produced at the same time as the bridge 25, in a single conductive material deposition step 25.
- the conductive ink jet techniques by a system for example, two heads can be used for this purpose. It is also possible to apply a winding technique of an insulated copper wire using an inclined thermode and a deposit of a thickness of about 25 microns. ⁇
- the method according to the invention makes it possible to reduce by 5 to 10% the total thickness of the module formed by the integrated circuit and its interconnection support. It thus makes it possible to produce an electronic module with a thickness of less than one hundred micrometers in which an integrated circuit is embedded.
- the realized module also offers much better strength than the modules comprising son son welded to ultrasound, which must also be protected by an insulating material.
- the chip according to the invention as well as the electronic module made from such a chip are capable of various embodiments.
- the inclined edges of the chip may be obtained by an abrasive treatment applied to the chips after their separation from the plate and independent of the formation of the cutting lines 2 on the plate.
- connection method according to the invention can also be applied to the interconnection of at least two chips arranged next to each other so that their inclined contact pads are facing each other. Once the two integrated circuits are fixed on a support, the interstice between the chips is filled with an electrically conductive material ensuring the interconnection of the inclined contact pads. Pre-filling of this gap with an insulating material, before depositing the conductive material, is also possible.
- the invention applies to all types of chips, in particular to the chips in another semiconductor material, for example gallium arsenide AsGa chips.
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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FR0504710 | 2005-05-11 | ||
PCT/FR2006/000669 WO2006120309A2 (fr) | 2005-05-11 | 2006-03-29 | Microplaquette de silicium ayant des plages de contact inclinees et module electronique comprenant une telle microplaquette |
Publications (1)
Publication Number | Publication Date |
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EP1880417A2 true EP1880417A2 (de) | 2008-01-23 |
Family
ID=35539794
Family Applications (1)
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EP06743608A Withdrawn EP1880417A2 (de) | 2005-05-11 | 2006-03-29 | Mit geneigten kontaktstellen ausgestattete siliziumchips und den siliziumchip umfassendes elektronisches modul |
Country Status (4)
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US (1) | US7823322B2 (de) |
EP (1) | EP1880417A2 (de) |
JP (1) | JP2008541441A (de) |
WO (1) | WO2006120309A2 (de) |
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JP5403201B2 (ja) * | 2007-01-25 | 2014-01-29 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2010258300A (ja) * | 2009-04-27 | 2010-11-11 | Murata Mfg Co Ltd | 電子部品の配線構造および電子部品の製造方法 |
CN102474989A (zh) * | 2009-10-06 | 2012-05-23 | 株式会社藤仓 | 电路基板 |
US8469280B2 (en) | 2009-10-22 | 2013-06-25 | Intellipaper, Llc | Programming devices and programming methods |
US8469271B2 (en) | 2009-10-22 | 2013-06-25 | Intellipaper, Llc | Electronic storage devices, programming methods, and device manufacturing methods |
WO2011127183A2 (en) | 2010-04-07 | 2011-10-13 | Intellipaper , Llc | Memomy programming methods and memory programming devices |
WO2011127328A2 (en) * | 2010-04-07 | 2011-10-13 | Intellipaper, Llc | Electronic assemblies and methods of forming electronic assemblies |
DE102011112659B4 (de) * | 2011-09-06 | 2022-01-27 | Vishay Semiconductor Gmbh | Oberflächenmontierbares elektronisches Bauelement |
DE102011115163B4 (de) * | 2011-09-27 | 2021-03-04 | Infineon Technologies Ag | Trägerschicht für eine Chipkarte |
WO2014006699A1 (ja) * | 2012-07-04 | 2014-01-09 | 富士機械製造株式会社 | 半導体パッケージ及びその製造方法 |
CN103904048B (zh) * | 2012-12-27 | 2017-03-01 | 欣兴电子股份有限公司 | 内置式芯片封装结构 |
US9324664B2 (en) * | 2013-02-22 | 2016-04-26 | Unimicron Technology Corp. | Embedded chip package structure |
US11527482B2 (en) * | 2017-12-22 | 2022-12-13 | Hrl Laboratories, Llc | Hybrid integrated circuit architecture |
US11536800B2 (en) * | 2017-12-22 | 2022-12-27 | Hrl Laboratories, Llc | Method and apparatus to increase radar range |
WO2019125587A1 (en) * | 2017-12-22 | 2019-06-27 | Hrl Laboratories, Llc | Hybrid integrated circuit architecture |
US10957537B2 (en) | 2018-11-12 | 2021-03-23 | Hrl Laboratories, Llc | Methods to design and uniformly co-fabricate small vias and large cavities through a substrate |
US11088098B2 (en) * | 2019-08-12 | 2021-08-10 | Viasat, Inc. | Integrated structures with antenna elements and IC chips employing edge contact connections |
US10978347B2 (en) * | 2019-09-16 | 2021-04-13 | Disco Corporation | Device chip and method of manufacturing device chip |
WO2022005542A1 (en) * | 2020-06-29 | 2022-01-06 | Hrl Laboratories, Llc | Method and apparatus to increase radar range |
US11972970B1 (en) | 2020-09-01 | 2024-04-30 | Hrl Laboratories, Llc | Singulation process for chiplets |
WO2022203690A1 (en) * | 2021-03-26 | 2022-09-29 | Hrl Laboratories, Llc | Hybrid integrated circuit architecture |
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JPS61123990A (ja) * | 1984-11-05 | 1986-06-11 | Casio Comput Co Ltd | Icカ−ド |
US4999684A (en) * | 1988-05-06 | 1991-03-12 | General Electric Company | Symmetrical blocking high voltage breakdown semiconducotr device |
US4992847A (en) * | 1988-06-06 | 1991-02-12 | Regents Of The University Of California | Thin-film chip-to-substrate interconnect and methods for making same |
FR2797076B1 (fr) * | 1999-07-30 | 2003-11-28 | Gemplus Card Int | Procede de fabrication d4une carte a puce a contact |
US6693358B2 (en) * | 2000-10-23 | 2004-02-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
US6555906B2 (en) * | 2000-12-15 | 2003-04-29 | Intel Corporation | Microelectronic package having a bumpless laminated interconnection layer |
US20030006493A1 (en) * | 2001-07-04 | 2003-01-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and manufacturing method thereof |
US7214569B2 (en) * | 2002-01-23 | 2007-05-08 | Alien Technology Corporation | Apparatus incorporating small-feature-size and large-feature-size components and method for making same |
TWI232560B (en) * | 2002-04-23 | 2005-05-11 | Sanyo Electric Co | Semiconductor device and its manufacture |
JP4093018B2 (ja) * | 2002-11-08 | 2008-05-28 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
JP2004165191A (ja) * | 2002-11-08 | 2004-06-10 | Oki Electric Ind Co Ltd | 半導体装置、半導体装置の製造方法及びカメラシステム |
US7043830B2 (en) * | 2003-02-20 | 2006-05-16 | Micron Technology, Inc. | Method of forming conductive bumps |
US7253735B2 (en) * | 2003-03-24 | 2007-08-07 | Alien Technology Corporation | RFID tags and processes for producing RFID tags |
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2006
- 2006-03-29 JP JP2008510606A patent/JP2008541441A/ja active Pending
- 2006-03-29 WO PCT/FR2006/000669 patent/WO2006120309A2/fr not_active Application Discontinuation
- 2006-03-29 EP EP06743608A patent/EP1880417A2/de not_active Withdrawn
-
2007
- 2007-11-09 US US11/937,972 patent/US7823322B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
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See references of WO2006120309A2 * |
Also Published As
Publication number | Publication date |
---|---|
WO2006120309A3 (fr) | 2007-03-08 |
JP2008541441A (ja) | 2008-11-20 |
US20080224320A1 (en) | 2008-09-18 |
US7823322B2 (en) | 2010-11-02 |
WO2006120309A2 (fr) | 2006-11-16 |
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