Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/0257—Doping during depositing
  • H01L21/02573—Conductivity type
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02373—Group 14 semiconducting materials
  • H01L21/02381—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02488—Insulating materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02513—Microstructure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02587—Structure
  • H01L21/0259—Microstructure
  • H01L21/02601—Nanoparticles
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S977/00—Nanotechnology
  • Y10S977/70—Nanostructure
  • Y10S977/773—Nanoparticle, i.e. structure having three dimensions of 100 nm or less
  • Y10S977/774—Exhibiting three-dimensional carrier confinement, e.g. quantum dots
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S977/00—Nanotechnology
  • Y10S977/902—Specified use of nanostructure
  • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application

Definitions

• the invention relates to a method for manufacturing a nanostructured pn junction light-emitting diode comprising a semiconductor substrate doped with a first dopant.
• the invention also relates to a nanostructured pn junction light emitting diode obtained by such a method.
• a waveguide is then etched into the substrate and electrical contacts are arranged at the periphery of the waveguide to ensure the injection of current through the different PN junctions.
• MJ. Chen et al. have thus been able to measure stimulated emission, at energies close to the silicon gap, in such a nanostructured pn junction diode, by current injection.
• the object of the invention is a method for manufacturing a nanostructured PN junction light-emitting diode, overcoming the drawbacks of the prior art.
• a heat treatment step intended to form, in the thin dielectric layer and from the amorphous thin film, a plurality of islands of semiconductor material doped with the second dopant, of nanometric dimension and in epitaxy with the substrate, for to form a plurality of nanoscale PN junctions
• the first phase of the heat treatment step is carried out by a rise in temperature to a first temperature threshold of the order of 350 ° C., followed by a maintenance at said first threshold for a first predetermined duration.
• the second phase of the heat treatment step is preferably carried out by a progressive rise in temperature to a second temperature threshold higher than the first threshold, followed by a maintenance at said second threshold for a second predetermined duration.
• the invention also aims a nanostructured PN junction light emitting diode, easy to produce and reliable.
• this object is achieved by the fact that it comprises at least: a semiconductor substrate doped with a first dopant and covered by a thin dielectric layer
• each island being in epitaxy with said substrate and with an additional thin film covering the dielectric thin layer.
• Figures 1 to 9 show, schematically, in section different steps of a method for manufacturing a light emitting diode nanostructured PN junction, according to the invention.
• Figures 10 and 11 show, respectively, in section of the first and second variants of a light emitting diode nanostructured PN junction according to the invention.
• a nanostructured pn junction light emitting diode is produced from a semiconductor substrate 1 doped with a first dopant and covered with a dielectric thin film 2.
• the substrate is, for example, a solid silicon substrate doped with an N-type dopant such as arsenic or phosphorus .
• the dielectric thin film 2 is preferably composed of a thermally decomposable compound and, more particularly, under the effect of a temperature of between 720 ° C. and 750 ° C.
• the decomposable compound is, for example, chosen from silicon oxide and silicon nitride.
• the dielectric thin film 2 preferably has a thickness of the order of a few nanometers. The thickness of the dielectric thin film 2 is, for example, 2 nm.
• an amorphous thin film 3 is deposited on the surface of the dielectric thin film 2 at a temperature, preferably less than or equal to 250 ° C.
• the amorphous thin film 3 consists of an amorphous semiconductor material doped with a second dopant of a type opposite to that of the first dopant and its thickness is preferably of the order of a few nanometers, for example from 1 to 2 nm.
• the amorphous thin film is doped with a P type dopant and vice versa.
• the amorphous thin film 3 is, for example, made of silicon doped with boron.
• MBE Molecular Jets Epitaxy
• silicon and boron are deposited on the surface of the dielectric thin film, by co-evaporation under ultrahigh vacuum, respectively by means of an electron gun and a high temperature evaporation cell of Knudsen type.
• the heat treatment step preferably comprises a first phase intended to form, on the dielectric thin film 2 and from the amorphous thin film 3, a plurality of polycrystalline clusters 4 of dimension nano-metric, also called polycrystalline boxes or polycrystalline clusters arranged on the dielectric thin film 2.
• the polycrystalline clusters 4 are formed by crystallization in the form of clusters or islands, the amorphous thin film 3, they are distributed over the thin layer dielectric 2 and most of them are isolated from each other.
• the first phase of the heat treatment step is preferably followed by a second phase comprising a gradual rise in temperature to a second threshold higher than that of the first phase followed by a maintenance at said second threshold during a second predetermined duration, for example of the order of 5 to 10 minutes.
• the second predetermined duration depends in particular on the thickness of the dielectric thin film 2.
• the second temperature threshold is preferably between 720 ° C. and 750 ° C.
• the second phase induces, as illustrated in FIGS. 3 and 4, the progressive transformation of the polycrystalline clusters 4 into islands 5 distributed in the dielectric thin film 2 and in epitaxy with the substrate 1.
• the formation of islands 5 in epitaxy with the substrate 1 is carried out by thermal decomposition of the regions of the dielectric thin film 2 arranged under the clusters or polycrystalline elements 4 and by epitaxial growth of said clusters with the substrate 1.
• the polycrystalline clusters 4 arranged on the surface of the dielectric thin film 2 then disappear, progressively in favor of the islands 5 in epitaxy with the substrate 1 and arranged in The dielectric thin layer 2.
• the islands 5 arranged in the dielectric thin film 2 are represented, schematically and in section, in the form of trapeziums while in FIGS. 2 and 3, the polycrystalline clusters or elements 4 arranged on the dielectric thin film 2 are represented, schematically and in section, in the form of circles.
• the distance between the two parallel planes of each island 5 shown in FIG. 4 is, more particularly, equal to the thickness of the dielectric thin film 2, this distance being also called height. In this way, one of the two parallel planes of each island forms the zone of contact with the substrate 1 while the other plane is comprised in the plane of the free surface of the dielectric thin layer 2.
• the heat treatment step is then followed by a step of forming, on the surface of the dielectric thin film 2, an additional thin film 6, by epitaxial growth from the islands 5.
• epitaxial growth step from the islands 5 firstly makes it possible to form, on the surface of the dielectric thin film 2, additional clusters in epitaxy with the islands 5, the additional clusters continuing their growth until they come into contact with each other and form a continuous thin layer. More particularly, this makes it possible to obtain an additional thin layer 6, for example constituted by the semiconductor material doped by the second dopant and constituting the islands 5.
• the additional thin layer could also consist of an undoped semiconductor material. .
• FIGS. 5 to 7 illustrate the progressive formation of the said additional thin layer 6, by taking up the epitaxial growth of the islands 5.
• discontinuous regions 7 made of semiconductor material, possibly doped and crystallized. and forming additional clusters grow, on the surface of the dielectric thin layer 2, above the areas occupied by the islands 5.
• the growth of the regions 7 continues ( Figure 6 and 7) so as to form a layer continuous constituting the additional thin layer 6.
• the thickness of the additional thin layer 6 depends on the density of the islands 5 in the dielectric layer 2 as well as their size.
• the density of islands 5 in the dielectric layer may, for example, be controlled using surfactants or surfactants such as nitrogen, hydrogen ...
• the size of islands 5 in the thin layer dielectric 2 can be controlled by the amount of silicon deposited, together with the predetermined durations of the phases of the heat treatment.
• the size and the position of the islands 5 in the dielectric thin film 2 can also be controlled by local weakening methods of the dielectric thin film 2, for example by means of a STM (Scanning Tunneling Microscopy) tip. Tunnel effect). Such methods can, for example, organize the islands 5 within the dielectric layer 2.
• the fabrication of the nanostructured pn junction light-emitting diode can be completed by forming a waveguide by structuring the additional thin film 6, the dielectric thin film 2 and a part of the substrate 1.
• the structuring can, for example, be performed by optical lithography.
• an insulating layer 8, for example silicon oxide or silicon nitride may be deposited at the periphery of the waveguide.
• First and second metal layers 9 and 10 forming electrical contact points are then deposited respectively on the additional thin layer 6 and on the free surface of the substrate 1, so as to allow the injection of electronic carriers into the junction diode.
• PN nanostructured are then deposited respectively on the additional thin layer 6 and on the free surface of the substrate 1, so as to allow the injection of electronic carriers into the junction diode.
• Such a method for manufacturing a light-emitting diode with nanostructured PN junction has the advantage of being easy to implement, the main steps of realization, that is to say until the realization of the guide. Indeed, the waveforms can be made in the same enclosure, which also avoids possible problems of contamination and oxidation of the islets.
• the fact of making the PN junctions by epitaxy makes it possible to obtain a crystalline coherence between the substrate 1, the islands 5 and the additional thin layer 6, which improves the reliability of the light-emitting diode and the definition of the PN junctions. , as well as its ability to integrate into another device.
• the temperature required to make the islands 5 and thus the PN junctions is relatively low compared to that used in the prior art.
• the junctions are most often isolated from each other by a dielectric material forcing the injection of the electronic carriers through these PN junctions.
• the second metal layer 10 is deposited on the substrate 1, in a region disposed at the periphery of the waveguide.
• the solid silicon substrate 1 is replaced by a silicon on insulator or SOI substrate.
• a silicon on insulator or SOI substrate comprises a stack comprising, successively, a support 11 made of solid silicon, an insulating layer 12 made of silicon oxide and a film 13 made of solid silicon doped with a dopant, for example of the N type, if the islands 5 are doped with P. film 13 is in contact with the islands 5 arranged in the dielectric thin film 2.
• the semiconductor material forming the islands 5 and the additional thin layer 6 may be germanium.
• the semiconductor substrate may be chosen from substrates made of silicon, germanium, silicon on insulator (SOI) and germanium on insulator.

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• 2005
  • 2005-03-15 FR FR0502530A patent/FR2883418B1/fr not_active Expired - Fee Related
• 2006
  • 2006-02-23 US US11/884,540 patent/US7736919B2/en not_active Expired - Fee Related
  • 2006-02-23 JP JP2008501349A patent/JP2008533732A/ja active Pending
  • 2006-02-23 EP EP06709371A patent/EP1859478A1/fr not_active Withdrawn
  • 2006-02-23 WO PCT/FR2006/000414 patent/WO2006097591A1/fr active Application Filing
  • 2006-02-23 CN CNA2006800082306A patent/CN101142658A/zh active Pending
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