Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
  • H01L29/861—Diodes
  • H01L29/88—Tunnel-effect diodes
  • H01L29/882—Resonant tunneling diodes, i.e. RTD, RTBD
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
  • H01L29/158—Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
  • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
  • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body

Definitions

• Electron resonant transport structures very often use geometries obtained by alternating layers of different physical properties.
• These layers are obtained, for example, by growths or successive treatments or plies of layers along the normal to the sample, as well for two-dimensional type structures as along unidimensional structures of wire type.
• such structures implement materials that differ from each other in their bandgap widths.
• micro or nano defects ordered in a crystal are used to produce resonant electron transport devices in a planar or longitudinal geometry.
• the invention relates to an electron transport device comprising:
• At least one transport layer in which at least one periodic network of dislocations and / or defects is produced at least one transport layer in which at least one periodic network of dislocations and / or defects is produced
• Such a device has one or more resonances during the transfer of electrons in the transport layer.
• At least part of the dislocations may be decorated by electric charges and / or chemical species.
• a network of dislocations can be arranged in square or rectangle, or hexagonally or more generally according to the symmetry imposed by the interactions between these dislocations.
• the fault network may also be at least partly of the type of irradiation and / or implantation defects.
• Means of electrical contact with the transport layer may be provided.
• the guide means comprise an insulating or weakly conductive layer on which the transport layer is disposed.
• Means may further be provided for applying and / or measuring an electric and / or magnetic field in the transport layer.
• the transport layer may be in the form of at least one elongated zone in a first direction, wherein the periodic network has a first period.
• It may further comprise at least a second elongate zone in a second direction, advantageously different from the first direction, according to which the periodic network has a second period, which may or may not be different from the first one.
• Different resonances are thus obtained in the different electron propagation directions, defined by the directions of the elongated zones.
• a second transport layer can be realized.
• the second transport layer may also be a dislocation network and / or defects. It is possible to produce two or more superimposed layers, with a network in each layer, the dislocations and / or defects may or may not be shifted, the network geometries may be identical or different. Such a stack makes it possible to increase the cross section of interaction between the electrons and the defects.
• Each transport layer may have a thickness of between 1 nm and 1 ⁇ m.
• the transport network is made in the superficial layer of an SOI structure, or a semiconductor-on-insulator type structure, the insulating layer being able to be used as a guiding layer.
• the invention also relates to a diode with negative differential resistance, comprising a device according to the invention, as described above.
• the invention also relates to a method for producing micro- or nanostructures by a technique which ensures good control of the distances and the modification of a crystalline material called "matrix", having few intrinsic defects.
• the invention also relates to a method for producing an electron transport device, comprising:
• a transport layer the formation of electron guiding means in the plane of said transport layer.
• the network may be of the type comprising at least one dislocation network, the method further comprising a step of decorating at least part of the dislocations with electric charges and / or chemical species.
• the network can be obtained from a bonding step of two crystalline materials and / or implantation and / or irradiation.
• a step of forming electrical contact means with the layer may further be performed.
• the step of forming the guide means preferably comprises a step of forming an insulating or weakly conductive layer on which the transport layer is disposed.
• FIGS. 1A-3 represent various aspects of a device according to the invention
• FIGS. 4A-4B represent dislocation networks
• FIGS. 5A-5C represent networks of irradiation defects
• FIG. 6 represents an application of a device according to the invention
• FIGS. 7A, 7B, 8A, 8B, 9A, 9B illustrate other examples of applications of devices according to the invention. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION
• FIG. 1 A first embodiment of the invention is illustrated in FIG. 1
• a first layer 6 is realized a periodic network of dislocations and / or defects, through which the electron transport takes place, the periodicity of the network conferring on this transport a resonant character.
• the network may be periodic in one or two dimensions.
• This network is for example made as explained in WO 99/05711 or in WO 02/054466.
• the network can be made by bonding by contacting a face of a first wafer of crystalline material with a face of a second wafer of crystalline material, so that the crystal lattices presented by said faces present at least a detuning parameter capable of allowing the formation of a lattice of crystalline defects and / or a network of stresses within a crystalline zone extending on either side of the interface of the two platelets, least one of said networks defining the micro- or nanostructure.
• the detuning parameter can be constituted by a determined angle of rotation offset of the crystal lattices presented by the two faces, and / or by a difference in crystal lattice parameter between the crystalline materials of the faces of the platelets contacted and / or determined angle according to which the face of at least one of the platelets is offset with respect to the single crystallographic plane of direction corresponding to this face.
• the contacting of the faces may be hydrophobic or hydrophilic type.
• a heat treatment step optionally makes it possible to complete the formation of the network of defects and / or stresses, and allows a reinforcement of the inter-atomic bonds between the faces of the wafers put in contact.
• a pitch network of between, for example, a few nanometers and a few tens or hundreds of nanometers or a few micrometers, for example between 1 nm and 50 nm or 100 nm or 500 nm or 1 ⁇ m or 20 ⁇ m. .
• the bonding of identical or different materials can be used to define the nature and pitch of dislocations.
• the use of bonding multilayers is possible to increase the cross section of interaction of electrons with defects. For example, one can superimpose two layers - one of thickness about 10 nm and the other thickness of 20 nm or 100 nm - on a layer of SiO 2 . The more defects there are, the greater the probability of the electrons encountering these defects and therefore of seeing their transport changed.
• a bond Si (001) / Si (001) will give a square array (as illustrated in FIG. 4A) of dislocations whereas a bonding Si (111) / Si (011) will give a hexagonal array (as illustrated on FIG. Figure 4B). If the materials are of different natures, the network will be rather rectangular.
• irradiation and / or implantation methods that is to say exposure to radiation (electrons and / or ions) which induce defects (gaps and / or interstitial defects) in the material 6 in which the transport takes place, either directly if the size of the probe is sufficiently small, or through a mask.
• the defects provided may have a passive and / or active nature with respect to the transport phenomenon.
• dislocations For example, one can have a phenomenon of diffusion or diffraction of the charge carriers on these linear defects, but one can also bring additional charges (electrons or holes) which can contribute directly to the transport.
• the character donor or acceptor of electron is defined by the nature of the defect, possibly by its decoration by elements and / or voluntarily added particles or captured in a spontaneous way.
• the electrons are confined in a plane layer, restricted in thickness around the network to promote interactions between these two entities.
• the transport is thus guided so that the interaction conditions are forced in the plane of the layer 6 containing the defects.
• the matrix with its micro- or nanostructures is thus separated from the substrate by a layer or barrier 4, insulating or weakly conductive relative to the conductivity of the layer 6 so that the majority of the current flows. in this layer 6.
• An SOI component comprising a substrate, a thin insulating layer (for example of SiO2 oxide) and a thin layer of semiconductor material, in particular of silicon, is suitable for producing a device according to the invention.
• a thin insulating layer for example of SiO2 oxide
• a thin layer of semiconductor material in particular of silicon
• the transport layer 6 has a thickness of, for example, between a few nm and 100 nm or a few hundreds of nm, for example between 1 nm or 5 nm and 100 or 200 nm or 500 nm or 1 ⁇ m.
• contacts 8, 10 can be made on the active layer 6, for example by metal deposits, to ensure lateral conduction of the charges in the layer. 6.
• the pads 8, 10 may be arranged on the layer 6 (FIG. 2), and no longer on either side as in FIG. 1B.
• the pads 8, 10 may be placed partially in the layer 6, and partially above the level or the upper surface of the layer.
• the combination of the two layers and the contacts may rest on a substrate 2.
• a lithography and an etching of the layer 6 may also be carried out and used to define in the plane of this same layer 6 one or more relative direction (s). (s) transport. It is thus possible to define transport belts, possibly of different orientations, from the plane of the layer 6.
• a confinement layer 4 may be used in combination with the definition of transport bands in the plane of the layer 6 containing the network.
• the network of dislocations and / or defects may be square, as illustrated in Figure 4A, or hexagonal, as shown in Figure 4B. These forms are only examples and the defects and / or dislocation can be distributed according to other geometric shapes, in particular rectangles.
• FIGS. 4A and 4B also show decorations of dislocation lines made by electric charges and / or chemical species 12, 14, 16, 18. As shown in FIG. 4A, the pitch or the period of the same network seen following two different directions Dl and D2 is not the same.
• FIGS. 5A to 5C show defect networks produced by irradiation and / or implantation, having a shape of pads (FIG. 5A) or strips parallel to each other (FIG. 5B) or intersecting (FIG. 5C). In the latter case, the bands are represented as being crossed orthogonally, but this is not always the case.
• the layer 6 may be used in combination with grids 20, 22 for applying an electric field (FIG. 6) which makes it possible to modulate the transport properties of the charges moving in the layer. 6.
• These grids are preferably closer to the band.
• FIGS. 7A and 7B illustrate the case of a layer 6 in which a network of defects and / or dislocations has been realized as explained above.
• Each of these strips defines a main direction of propagation of the charges, between on the one hand a stud 80 and on the other hand one of the three studs 82, 84, 86.
• FIG. 7A can illustrate, for example, a case of a dislocation network formed by molecular bonding of two crystalline semiconductor materials of different natures.
• FIG. 7B may illustrate, for example, another case of a dislocation network formed by molecular bonding of two identical crystalline semiconductor materials, for example, Si (001) / Si (001) bonding.
• a step or a specific period is associated with each direction, and therefore with each band 60, 62, 64 as explained above with reference to FIG. 4A.
• the pitch or the period of the band 60 is different from the pitch or the period seen in the band 62, which is different from the pitch or the period seen in the band 64.
• the latter could be equal to the pitch of the band 60. More generally it is possible to produce a structure comprising at least two bands having different directions, two of the bands having two identical pitch.
• the modulation of the currents in the three, or n, bands gives information on the directions and the intensities of these fields.
• the field or fields may be of any direction relative to the plane of the bands, here the plane of the figure.
• the band only gives access to the component of the projected field on this band.
• the band is in the plane of the bands, two bands are enough to define it completely.
• FIGS. 8A and 9A there will be voltage-current curves having the shape shown respectively in FIGS. 8B and 9B.
• the period of the grating and the guidance of the charges (of the electrons) result in the appearance of a resonance which results in a peak in the current curve (I) - voltage (V).
• the current and the voltage are measured between the pads 8, 10.
• the diffusion and / or diffraction on the periodic defects of the created network can also be used to realize diode type structures having negative differential resistances. It can be arranged that the curve I (v) of the device of the invention is that of a diode. It is therefore the device itself which constitutes the diode.
• the peak / valley ratio of an I / V characteristic of such a diode can then be adjusted by the period and the number of periods of the defects seen by the electrons. Again, in this application, several peaks can also be superimposed on an I / V curve, from the same network of dislocations, by fixing the direction of the transport path, or by changing the pitch of the masks with an irradiation technique. .
• the application of a magnetic or electric field may change the conditions of transport in these materials.
• the direction of the field can be any, as already explained above. It can be intentional, fixed for example by the voltages applied to the terminals 8, 10 or coming from the outside medium (this is for example the case for an application to a sensor).
• the regularity of the network and the guidance in the zone containing dislocations are advantageously used: the carriers thus have different mobilities according to the directions since the probability for them to meet the networks is different according to the direction.
• This dependence can be used to produce a magnetic field sensor sensitive to the direction of the field: indeed, the variation of the current or the voltage in the plane of the network, or in a guide band, is related to the direction and the intensity of the applied field E and / or H.
• Means may be provided for measuring a variation of a reference current flowing in the layer, or in one or more guide strips, when applying an electric and / or magnetic field.
• there may be provided means for measuring the voltage generated in said layer.
• the invention offers an ease of implementation because it requires only a few technological steps: a molecular bonding or the use of a technique of irradiation and / or implantation through mask with the ions. It does not implement elaborate deposition techniques (trench filling, complex patterns ).
• An exemplary embodiment relates to a device that uses the diffusion or diffraction of electrons by a network of dislocations of a thin layer 6 obtained by molecular bonding, this layer being separated from the support 2 by an oxide layer 4 (SiO 2 ) .
• the bonded layer is made from an SOI substrate (001) according to the technique described in the document WO 02/054466.
• a square array of regular, coherent screw dislocations is achieved over large distances (for example with a pitch of 22 nm).
• the network of identical dislocations has a well controlled step
• Thinning of the bonded layer 6, for example at 10 nm, can be carried out. Then lithography of strips parallel to one of the sides of the square formed by the lines of dislocations is carried out.
• the width of the lithographed lines will correspond to a few sides of the square (for example 50 nm, which corresponds to about 2 periods), while the length will be larger (for example 1 micron, that is to say 50 periods).
• Different orientations of the lithography pattern with respect to the dislocation network can be used to modulate the expected resonance effects.
• the defect zones result from localized irradiation with electrons ( ⁇ 50 keV) or localized implantation by He ions ( ⁇ 2 MeV) in an SOI structure.
• the location of the irradiation or implantation can be done by means of masks.
• the sizes and the spacing of the patterns will then be greater, given the technological constraints of producing the mask.
• Each pattern of the mask defines a zone of irradiation or implantation defects, the density of defects in each zone being fixed by the conditions (dose, energy, selected elements, etc.) of implantation. by irradiation. Structures obtained by these techniques are illustrated in FIGS. 5A-5C.
• the invention it is also possible to produce two or more superimposed layers, with a network in each layer, whose dislocations and / or defects may or may not be shifted, the geometries of the networks may be identical or different.
• a stack makes it possible to increase the cross section of interaction between the electrons and the defects.
• the realization of such a stack can be obtained by successive collages. Or, a first network is obtained by gluing and a second is obtained by irradiation.

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