Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
  • G06F12/0646—Configuration or reconfiguration
  • G06F12/0653—Configuration or reconfiguration with centralised address assignment
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing

Definitions

• Memory interface Memory interface, memory arrangement and method of controlling memory access
• the invention relates to a memory interface for controlling access to a program and/or data memory that is divided into a plurality of memory areas, comprising address-calculating means for converting a logic memory address into a physical memory address by performing a logic operation on the logic memory address with an offset value assigned to the given memory area.
• the invention also relates to a memory arrangement having a memory interface according to the invention.
• the invention also relates to a method of controlling access to a program and/or data memory that is divided into a plurality of memory areas, in which a memory interface converts a logic memory address into a physical memory address by performing a logic operation on ⁇ he logic memory address with an offset value assigned to the given memory area.
• Said logic division of a program memory MEM comprises a system area SROM 0..SROM 5.5 having memory blocks each 256 bytes in size and two user areas, namely a first user area EROM 0..EROM 7.5 having memory blocks each 256 bytes in size and a second user area UROM 0..UROM 3.5 having memory blocks each 256 bytes in size.
• a test area (not shown) may also be present.
• the individual memory locations in the system area and the user areas are accessed by means of logic addresses iadr[0-12], with bits iadr[O] to iadr[7] being used to address individual memory locations within a given memory block and bits iadr[8] to iadr[12] being used to select the memory blocks.
• en_sysrom provided that is used to differentiate between the logic system memory-area SROM 0..SROM 5.5 and the logic user memory-areas EROM 0..EROM 7.5 and UROM 0..UROM 3.5.
• control signal en_sysrom When the control signal en_sysrom is 1, the system memory-area SROM 0..SROM 5.5 is accessed, and when the control signal en_sysrom is 0, the user memory-areas EROM 0..EROM 7.5 and UROM 0..UROM 3.5 are accessed.
• the function of the control signal en_sysrom in principle is equivalent to a fourteenth address bit. As can be seen, only a part of the address space that can be accessed by means of the logic addressing is used. Unused memory blocks in the system memory-area SROM 0..SROM 5.5 and the user memory-areas EROM 0..EROM 7.5 and UROM 0..UROM 3.5 are marked X in Fig. 1.
• logic memory areas SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5 may also be split up among different physical memories, as shown by way of example in the right-hand part of Fig. 1, which shows two memory modules MEMl and MEM2 in schematic form.
• the logic system memory-area SROM O..SROM 5.5 and the second user area UROM 0..UROM 3.5 are accommodated in memory module MEMl, whereas only the first user memory-area EROM 0..EROM 7.5 is situated in memory module MEM2.
• first memory module MEMl is fully occupied by the system memory-area SROM O..SROM 5.5 and the second user memory-area UROM 0..UROM 3.5
• second memory module MEM2 is fully occupied by the first user memory- area EROM 0..EROM 7.5, and that there are no unused physical memory areas.
• the individual memory modules MEMl and MEM2 may be selected from different types of memory, and memory module MEMl may take the form of a once-only writable ROM and memory module MEM2 that of a rewritable EEPROM or flash memory.
• a memory interface is required that maps the logic addresses iadr[O- 12] to the correct physical addresses for the individual memory modules MEMl, MEM2.
• the relationship between logic and physical addresses in the system memory- area SROM 0..SROM 5.5 and the first user memory-area EROM O..EROM 7.5 is straightforward.
• a calculating unit is required that subtracts an offset from the logic address iadr[0-12] to determine the physical address.
• the logic address iadr[0-12] has to be assigned to the correct physical memory module MEMl.
• a memory interface of the kind detailed in the opening paragraph that additionally comprises offset control means for writing the offset values to a volatile offset memory, wherein the offset control means are arranged to read in at least one offset value from a preset address in the program and/or data memory.
• a memory arrangement comprising a memory interface according to the invention, and a program and/or data memory that is divided into a plurality of memory areas and that has preset memory locations at which offset values are stored.
• ROM-mask product hence it is possible even to re-arrange the division of the memory areas at no extra expense simply by means of a new ROM code. This is particularly advantageous if the ROM is the only memory used, because no further memory is needed to store the memory configuration.
• the hardware-based nature of the sequence of writing the offset values to the volatile offset memory by means of offset control means provides the advantage that unauthorized memory access by a user is avoided, although the memory segmentation can still be changed by software means if, for example, new system programs are being implemented, which require more memory space or a different memory division.
• the offset control means are arranged to read in an offset value from a preset address in the program and/or data memory and to write it to the volatile offset memory at the initialization of the memory interface, the memory interface being arranged to grant access to the program and/or data memory only thereafter.
• the memory interface advantageously is enabled for use by programs or to run program code only after the correct offset values have been written to the offset memory. Hence forbidden memory accesses can be ruled out.
• the address calculating means are arranged to receive at least one control signal for selecting memory areas and to take account of this control signal when the logic memory addresses are converted into physical memory addresses.
• This provides the advantage that the logic memory-areas can be configured in a very flexible way and can be selectively accessed. For example, a separate control line may be assigned to each logic memory-area (system area, user area), and a logic memory area may be selected by applying a signal selectively to one of these control lines, whereas access to other logic memory areas are prevented at the same time.
• the offset control means are arranged to write offset values to the volatile offset memory at the run time of the memory interface, because in this way the memory interface can be reconfigured at run time.
• the offset control means comprise offset control inputs and offset configuration inputs and are arranged to read in offset values from one of the offset configuration inputs and write them to the volatile offset memory, as a function of signals at the offset control inputs.
• the memory interface is reconfigurable in a preset way at the run time.
• offset control inputs which are able to be operated by programs, cause the offset control means to read in offset values via offset configuration inputs, wherein the offset configuration inputs supply the offset values by accessing non- volatile memories in which the offset values are stored.
• the non ⁇ volatile memory may comprise hard-wired circuits, mask-programmable locations, etc.
• Fig. 1 shows an example of a memory arrangement having three logic memory areas that are divided between two physical memory modules.
• Fig. 2 is a schematic block circuit diagram of a memory arrangement and a memory interface according to the invention.
• Fig. 2 is a block circuit diagram of an embodiment of a memory arrangement and of a memory interface 1 according to the invention, by which memory arrangement and memory interface 1 the logic and physical division of the memory that is shown in Fig. 1 and has been described above is implemented.
• the memory arrangement comprises a program and/or data memory MEM comprising the two memory modules MEMl and MEM2 from Fig. 1, with memory module MEMl taking the form of, for example, a one-time writable ROM and memory module MEM2 taking the form of, for example, a rewritable EEPROM or flash memory.
• the individual storage locations in the memory modules MEMl and MEM2 can be accessed via a physical address bus 9.
• the program and/or data memory MEM comprises a logic system memory-area SROM 0..SROM 5.5, and two logic user memory-areas UROM 0..UROM 3.5 and EROM 0..EROM 7.5 that are separated onto different ones of the two physical memory modules MEMl and MEM2.
• the memory interface 1 serves to make the correct conversion of the logic memory addresses iadr[O-i] into the physical memory addresses phys_adr[O-j].
• the memory interface 1 comprises address calculating means 2 in hardware form.
• the address calculating means 2 have inputs for the logic address bus 10, said logic address bus 10 having, in the embodiment shown, thirteen address lines in conformity with the memory configuration shown in Fig. 1.
• the address calculating means 2 also have an input for the control line 12, and hence for the control signal en_sysrom that is used to select either the logic system memory-area SROM 0..SROM 5.5 or the logic user memory-areas UROM 0..UROM 3.5 and EROM 0..EROM 7.5.
• control line 12 is equivalent to that of an additional address line, because the system memory-area SROM O..SROM 5.5 is accessed if the control signal en_sysrom is at the logic 1 level and the user memory-areas UROM 0..UROM 3.5 and EROM 0..EROM 7.5 are accessed if the control signal en_sysrom is at the logic O level. Individual memory locations are addressed via the logic memory address iadr[O-i].
• control lines there may also be a plurality of control lines provided (not shown in the drawing).
• each of these control lines may be used for communication with one logic memory area SROM 0..SROM 5.5, UROM 0..UROM 3.5, EROM 0..EROM 7.5, or a combination of signals on these control lines is used for communication with a combination of logic memory areas SROM 0..SROM 5.5, UROM 0..UROM 3.5, EROM 0..EROM 7.5.
• the logic memory addresses iadr[O-i] of the system memory locations and the user memory locations are fed into the address calculating means 2.
• selecting information is passed to them on whether it is a system memory-area SROM 0..SROM 5.5 or one of the user memory-areas UROM 0..UROM 3.5 or EROM 0..EROM 7.5 that is to be addressed.
• These logic memory addresses iadr[O-i] and the selecting information are converted in the address calculating means 2 into physical memory addresses phys_adr[O-j] of the physical memory modules MEMl and MEM2.
• the address calculating means 2 generate chip selecting signals CSl and CS2 by means of which the individual memory modules MEMl and MEM2 can be selectively accessed.
• the address calculating means 2 convert the logic memory addresses iadr[O-i] received via the logic address bus 10 into physical memory addresses phys_adr[O-j] that are assigned to the memory locations in the memory modules MEMl and MEM2. In doing so the address calculating means perform a logic operation on the logic memory addresses iadr[O-I] with preset offset values OFFSETJBOOT, OFFSET-RTl, 0FFSET_RT2. In a preferred, simple embodiment the logic operation comprises the addition or subtraction of the offset OFFSET_BOOT, OFFSET_RT1, 0FFSET_RT2 to or from the logic memory addresses iadr[O-i]. The invention however is not limited to a logic operation of this form.
• the address outputs of the address calculating means 2 are connected to the physical address bus 9 via which the determined physical memory addresses phys_adr[O-j] are written.
• the physical address bus 9 via which the determined physical memory addresses phys_adr[O-j] are written.
• the memory interface 1 comprises a volatile offset memory 3 that may take the form of, for example, a flip-flop or latch and to which the offset values OFFSETJBOOT,
• OFFSET_RT1, OFFSET_RT2 may be written, which subsequently are read out of the offset memory 3 by the address calculating means 2 for a logic operation with the memory addresses iadr[0-i].
• the writing of the offset values OFFSET BOOT, OFFSET_RT1, OFFSET_RT2 to the offset memory 3 is performed in this case by offset control means 4 that are implemented in the memory interface 1 in the form of hardware.
• the offset control means 4 read in an offset value OFFSET_BOOT from preset storage locations in the program and/or data memory MEM (from the memory module MEMl in the present example, as indicated symbolically by the arrow 5) and write this offset value OFFSET_BOOT to the volatile offset memory 3, thus causing the memory interface 1 to be booted with a correct offset value OFFSET_BOOT.
• the offset value OFFSET_BOOT it is useful for the offset value OFFSET_BOOT to be written to the memory module MEMl, which is segmented into a plurality of memory areas, wherein preferably also the particular offset configuration for the said memory module MEMl is stored in said memory module MEMl .
• the address calculating means 2 are disenabled by the offset control means 4 until the writing of the offset values OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 to the volatile offset memory 3 has been completed, and only then access to the program and/or data memory MEM is granted, as indicated symbolically by the enabling signal en_ad.
• the memory interface 1 which is performed by hardware means, the correct segmenting of the program and/or data memory MEM is set before any code from the said memory can be executed. Unauthorized memory access by a user is effectively prevented in this way.
• the memory interface 1 itself no longer needs to be modified if amended program and/or data memory configurations are to be used. Instead the configuration merely has to be reprogrammed in an easy way by writing amended offset values OFFSET_BOOT to the new program and/or data memory MEM that is to be used. This of course speeds up the design process when new products are created. In this way, the allocation of the memory areas can be changed simply by a change of the ROM mask. Hence, in the case of a ROM-mask product, the division of the memory areas SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5 can also be rearranged, at no extra expense, with each new ROM code.
• the offset control means 4 are arranged to write offset values OFFSET_RT1, OFFSET_RT2 to the volatile offset memory 3 at the run time of the memory interface 1, thus enabling a memory segmentation to be changed by software means.
• the > offset control means 4 have an offset control input 6 and two offset configuration inputs 7, 8.
• the offset control means 4 read in offset values OFFSET_RT1 (via offset configuration input 7) or OFFSET_RT2 (via offset configuration input 8) and write these offset values to the volatile offset memory 3. In this way, the memory segmentation can be changed at the run time.
• the offset configuration inputs 7, 8 obtain the offset values OFFSET_RT1, OFFSET_RT2 by accessing non- volatile memories (not shown) in which the offset values OFFSET_RT1, OFFSET_RT2 are stored, the non-volatile memories comprising hard-wired circuits, mask- programmable locations, etc.

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• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
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• 2005
  • 2005-08-25 KR KR1020077007615A patent/KR20070101208A/ko not_active Application Discontinuation
  • 2005-08-25 JP JP2007529400A patent/JP2008511896A/ja not_active Withdrawn
  • 2005-08-25 WO PCT/IB2005/052790 patent/WO2006024999A1/en active Application Filing
  • 2005-08-25 CN CNB2005800374988A patent/CN100520711C/zh not_active Expired - Fee Related
  • 2005-08-25 EP EP05781155A patent/EP1789870A1/en not_active Withdrawn

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