WO2006024999A1

WO2006024999A1 - Memory interface, memory arrangement and method of controlling memory access

Info

Publication number: WO2006024999A1
Application number: PCT/IB2005/052790
Authority: WO
Inventors: Martin Posch
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-09-03
Filing date: 2005-08-25
Publication date: 2006-03-09
Also published as: CN101057216A; JP2008511896A; KR20070101208A; CN100520711C; EP1789870A1

Abstract

A memory interface (1) for controlling access to a program and/or data memory (MEM) is disclosed that is divided into a plurality of memory areas (SROM O..SROM 5.5, EROM O..EROM 7.5, UROM O..UROM 3.5). The memory interface (1) comprises address calculating means (2) for converting a logic memory address (iadr[O-i] into a physical memory address (phys adr[0 j]) by performing a logic operation on the logic memory address (iadr[O-i]) with an offset value (OFFSET BOOT, OFFSET RT1, OFFSET RT2) that is assigned to the given memory area (SROM O..SROM 5.5, EROM O..EROM 7.5, UROM O..UROM 3.5) and that is stored in a volatile offset memory (3). At least one offset value (OFFSET BOOT) is read from a preset address in the program and/or data memory (MEM) therefore.

Description

Memory interface, memory arrangement and method of controlling memory access

FIELD OF THE INVENTION

The invention relates to a memory interface for controlling access to a program and/or data memory that is divided into a plurality of memory areas, comprising address-calculating means for converting a logic memory address into a physical memory address by performing a logic operation on the logic memory address with an offset value assigned to the given memory area.

The invention also relates to a memory arrangement having a memory interface according to the invention.

Finally, the invention also relates to a method of controlling access to a program and/or data memory that is divided into a plurality of memory areas, in which a memory interface converts a logic memory address into a physical memory address by performing a logic operation on^he logic memory address with an offset value assigned to the given memory area.

BACKGROUND OF THE INVENTION

Program and data memories that have areas that differ both logically and physically are well known in prior art. In this way there exists, for example, a logic division of a program memory MEM in a microcontroller-based integrated circuit (IC) developed by ^■ the present applicant for the implementation of a motor vehicle immobilizer, as shown in the left-hand part of Fig. 1. Said logic division of a program memory MEM comprises a system area SROM 0..SROM 5.5 having memory blocks each 256 bytes in size and two user areas, namely a first user area EROM 0..EROM 7.5 having memory blocks each 256 bytes in size and a second user area UROM 0..UROM 3.5 having memory blocks each 256 bytes in size. As an option, a test area (not shown) may also be present. The individual memory locations in the system area and the user areas are accessed by means of logic addresses iadr[0-12], with bits iadr[O] to iadr[7] being used to address individual memory locations within a given memory block and bits iadr[8] to iadr[12] being used to select the memory blocks. In addition, there is a control signal en_sysrom provided that is used to differentiate between the logic system memory-area SROM 0..SROM 5.5 and the logic user memory-areas EROM 0..EROM 7.5 and UROM 0..UROM 3.5. When the control signal en_sysrom is 1, the system memory-area SROM 0..SROM 5.5 is accessed, and when the control signal en_sysrom is 0, the user memory-areas EROM 0..EROM 7.5 and UROM 0..UROM 3.5 are accessed. In the embodiment shown, the function of the control signal en_sysrom in principle is equivalent to a fourteenth address bit. As can be seen, only a part of the address space that can be accessed by means of the logic addressing is used. Unused memory blocks in the system memory-area SROM 0..SROM 5.5 and the user memory-areas EROM 0..EROM 7.5 and UROM 0..UROM 3.5 are marked X in Fig. 1. In addition, the logic memory areas SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5 may also be split up among different physical memories, as shown by way of example in the right-hand part of Fig. 1, which shows two memory modules MEMl and MEM2 in schematic form. The logic system memory-area SROM O..SROM 5.5 and the second user area UROM 0..UROM 3.5 are accommodated in memory module MEMl, whereas only the first user memory-area EROM 0..EROM 7.5 is situated in memory module MEM2. It can be seen that the first memory module MEMl is fully occupied by the system memory-area SROM O..SROM 5.5 and the second user memory-area UROM 0..UROM 3.5, and the second memory module MEM2 is fully occupied by the first user memory- area EROM 0..EROM 7.5, and that there are no unused physical memory areas. The individual memory modules MEMl and MEM2 may be selected from different types of memory, and memory module MEMl may take the form of a once-only writable ROM and memory module MEM2 that of a rewritable EEPROM or flash memory.

Because of the logic addressing of the system memory-area SROM 0..SROM 5.5 and the user memory-areas EROM 0..EROM 7.5 and UROM O..UROM 3.5, a memory interface is required that maps the logic addresses iadr[O- 12] to the correct physical addresses for the individual memory modules MEMl, MEM2. In the embodiment shown in Fig. 1, the relationship between logic and physical addresses in the system memory- area SROM 0..SROM 5.5 and the first user memory-area EROM O..EROM 7.5 is straightforward. For the second user memory-area UROM 0..UROM 3.5 however, a calculating unit is required that subtracts an offset from the logic address iadr[0-12] to determine the physical address. In addition, the logic address iadr[0-12] has to be assigned to the correct physical memory module MEMl.

It has been found to be a disadvantage that, to date, a separate memory interface has to be designed for each product having a different memory configuration. Accordingly, the circuit design has to be adapted at the time of any change of the sizes and/or types of the memories. A subsequent change of the allocation of the memory areas is not possible. In a ROM-mask product, only the program and not the physical size of the memory can be changed. There is equally little possibility of balancing the sizes of the memory areas. Hence it may happen that there is memory left unused in one memory area that is needed in some other area.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the invention to provide a memory interface of the kind specified in the first paragraph above, a memory arrangement of the kind specified in the second paragraph above and a method of controlling memory access of the kind specified in the third paragraph above in which the disadvantages stated above are avoided.

To achieve the above-mentioned object, a memory interface of the kind detailed in the opening paragraph is specified that additionally comprises offset control means for writing the offset values to a volatile offset memory, wherein the offset control means are arranged to read in at least one offset value from a preset address in the program and/or data memory.

To achieve the above-mentioned object, there is also specified a memory arrangement comprising a memory interface according to the invention, and a program and/or data memory that is divided into a plurality of memory areas and that has preset memory locations at which offset values are stored.

Finally, a method of the kind detailed at the beginning is specified in which, before an address conversion, at least one offset value is read in from a preset address in the program and/or data memory and is stored in a volatile offset memory.

What is achieved by means of the features according to the invention is that, if a different memory configuration is required for a new product, the memory interface itself no longer needs to be changed. It is merely the memory configuration that has to be reprogrammed. This speeds up the design process when new products are being created. For ROM variants, it is therefore merely necessary to replace the memory and to reprogram the configuration, which is done by writing new offset values to preset memory location in the program and/or data memory in a non-volatile fashion. No further steps of a design change are required. The allocation of the memory areas can be changed simply by a changing the ROM mask. For a ROM-mask product hence it is possible even to re-arrange the division of the memory areas at no extra expense simply by means of a new ROM code. This is particularly advantageous if the ROM is the only memory used, because no further memory is needed to store the memory configuration. In addition, the hardware-based nature of the sequence of writing the offset values to the volatile offset memory by means of offset control means provides the advantage that unauthorized memory access by a user is avoided, although the memory segmentation can still be changed by software means if, for example, new system programs are being implemented, which require more memory space or a different memory division.

It is beneficial if the offset control means are arranged to read in an offset value from a preset address in the program and/or data memory and to write it to the volatile offset memory at the initialization of the memory interface, the memory interface being arranged to grant access to the program and/or data memory only thereafter. The memory interface advantageously is enabled for use by programs or to run program code only after the correct offset values have been written to the offset memory. Hence forbidden memory accesses can be ruled out.

It is also beneficial if the address calculating means are arranged to receive at least one control signal for selecting memory areas and to take account of this control signal when the logic memory addresses are converted into physical memory addresses. This provides the advantage that the logic memory-areas can be configured in a very flexible way and can be selectively accessed. For example, a separate control line may be assigned to each logic memory-area (system area, user area), and a logic memory area may be selected by applying a signal selectively to one of these control lines, whereas access to other logic memory areas are prevented at the same time.

It is also advantageous in the offset control means are arranged to write offset values to the volatile offset memory at the run time of the memory interface, because in this way the memory interface can be reconfigured at run time. Finally, it is also of advantage if the offset control means comprise offset control inputs and offset configuration inputs and are arranged to read in offset values from one of the offset configuration inputs and write them to the volatile offset memory, as a function of signals at the offset control inputs. In this way, the memory interface is reconfigurable in a preset way at the run time. For this purpose offset control inputs, which are able to be operated by programs, cause the offset control means to read in offset values via offset configuration inputs, wherein the offset configuration inputs supply the offset values by accessing non- volatile memories in which the offset values are stored. The non¬ volatile memory may comprise hard-wired circuits, mask-programmable locations, etc. These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter, to which however the invention is not limited.

BRIEF DESCRIPTION OF THE DRAWINGS In the drawings:

Fig. 1 shows an example of a memory arrangement having three logic memory areas that are divided between two physical memory modules.

Fig. 2 is a schematic block circuit diagram of a memory arrangement and a memory interface according to the invention.

DESCRIPTION OF EMBODIMENTS

Fig. 2 is a block circuit diagram of an embodiment of a memory arrangement and of a memory interface 1 according to the invention, by which memory arrangement and memory interface 1 the logic and physical division of the memory that is shown in Fig. 1 and has been described above is implemented. The memory arrangement comprises a program and/or data memory MEM comprising the two memory modules MEMl and MEM2 from Fig. 1, with memory module MEMl taking the form of, for example, a one-time writable ROM and memory module MEM2 taking the form of, for example, a rewritable EEPROM or flash memory. The individual storage locations in the memory modules MEMl and MEM2 can be accessed via a physical address bus 9. Their data (shown as "data") can be read out via the data bus 11 and, in the case of the rewritable memory module MEM2, can also be read in via the said data bus 11. It should be mentioned that for the purposes of the invention it is not essential whether the logic or physical division of the memory MEM is organized into blocks or whether the addressing is linear. The size of the memory blocks is equally not essential in case of a block organized memory MEM. As explained above in the description of Fig. 1, the program and/or data memory MEM comprises a logic system memory-area SROM 0..SROM 5.5, and two logic user memory-areas UROM 0..UROM 3.5 and EROM 0..EROM 7.5 that are separated onto different ones of the two physical memory modules MEMl and MEM2. The memory interface 1 according to the invention serves to make the correct conversion of the logic memory addresses iadr[O-i] into the physical memory addresses phys_adr[O-j].

The memory interface 1 comprises address calculating means 2 in hardware form. The address calculating means 2 have inputs for the logic address bus 10, said logic address bus 10 having, in the embodiment shown, thirteen address lines in conformity with the memory configuration shown in Fig. 1. The address calculating means 2 also have an input for the control line 12, and hence for the control signal en_sysrom that is used to select either the logic system memory-area SROM 0..SROM 5.5 or the logic user memory-areas UROM 0..UROM 3.5 and EROM 0..EROM 7.5. In the embodiment shown, the function of the control line 12 is equivalent to that of an additional address line, because the system memory-area SROM O..SROM 5.5 is accessed if the control signal en_sysrom is at the logic 1 level and the user memory-areas UROM 0..UROM 3.5 and EROM 0..EROM 7.5 are accessed if the control signal en_sysrom is at the logic O level. Individual memory locations are addressed via the logic memory address iadr[O-i].

However, it should be mentioned that, in accordance with the invention, there may also be a plurality of control lines provided (not shown in the drawing). In this case each of these control lines may be used for communication with one logic memory area SROM 0..SROM 5.5, UROM 0..UROM 3.5, EROM 0..EROM 7.5, or a combination of signals on these control lines is used for communication with a combination of logic memory areas SROM 0..SROM 5.5, UROM 0..UROM 3.5, EROM 0..EROM 7.5.

Via the logic address bus 10 and the control line 12, the logic memory addresses iadr[O-i] of the system memory locations and the user memory locations are fed into the address calculating means 2. In addition, selecting information is passed to them on whether it is a system memory-area SROM 0..SROM 5.5 or one of the user memory-areas UROM 0..UROM 3.5 or EROM 0..EROM 7.5 that is to be addressed. These logic memory addresses iadr[O-i] and the selecting information are converted in the address calculating means 2 into physical memory addresses phys_adr[O-j] of the physical memory modules MEMl and MEM2. In addition, the address calculating means 2 generate chip selecting signals CSl and CS2 by means of which the individual memory modules MEMl and MEM2 can be selectively accessed.

The address calculating means 2 convert the logic memory addresses iadr[O-i] received via the logic address bus 10 into physical memory addresses phys_adr[O-j] that are assigned to the memory locations in the memory modules MEMl and MEM2. In doing so the address calculating means perform a logic operation on the logic memory addresses iadr[O-I] with preset offset values OFFSETJBOOT, OFFSET-RTl, 0FFSET_RT2. In a preferred, simple embodiment the logic operation comprises the addition or subtraction of the offset OFFSET_BOOT, OFFSET_RT1, 0FFSET_RT2 to or from the logic memory addresses iadr[O-i]. The invention however is not limited to a logic operation of this form. Merely by way of example other forms of logic operation will be mentioned, namely the addition of a plurality of offsets OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 to the logic memory addresses iadr[0-i] and the addition or subtraction of the sum of the offsets to or from the said logic memory addresses iadr[0-i], or the taking into account of additional memory address displacements, or the additional multiplication of memory block sizes, when converting into the physical memory addresses phys_adr[O-j].

The address outputs of the address calculating means 2 are connected to the physical address bus 9 via which the determined physical memory addresses phys_adr[O-j] are written. In place of one physical address bus 9 and a plurality of chip selecting signals CSl, CS2, there may also be a plurality of physical address buses 9 or combinations of these possibilities.

Whereas in the prior art the offset value used for the logic operation was fixed and was stored in a non- volatile memory of the memory interface 1, the memory interface 1 according to the invention comprises a volatile offset memory 3 that may take the form of, for example, a flip-flop or latch and to which the offset values OFFSETJBOOT,

OFFSET_RT1, OFFSET_RT2 may be written, which subsequently are read out of the offset memory 3 by the address calculating means 2 for a logic operation with the memory addresses iadr[0-i]. The writing of the offset values OFFSET BOOT, OFFSET_RT1, OFFSET_RT2 to the offset memory 3 is performed in this case by offset control means 4 that are implemented in the memory interface 1 in the form of hardware.

According to the invention it is provided that during the initialization of the memory interface 1, the offset control means 4 read in an offset value OFFSET_BOOT from preset storage locations in the program and/or data memory MEM (from the memory module MEMl in the present example, as indicated symbolically by the arrow 5) and write this offset value OFFSET_BOOT to the volatile offset memory 3, thus causing the memory interface 1 to be booted with a correct offset value OFFSET_BOOT. It should be mentioned that it is useful for the offset value OFFSET_BOOT to be written to the memory module MEMl, which is segmented into a plurality of memory areas, wherein preferably also the particular offset configuration for the said memory module MEMl is stored in said memory module MEMl . In addition it is provided that the address calculating means 2 are disenabled by the offset control means 4 until the writing of the offset values OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 to the volatile offset memory 3 has been completed, and only then access to the program and/or data memory MEM is granted, as indicated symbolically by the enabling signal en_ad. By initialization of the memory interface 1, which is performed by hardware means, the correct segmenting of the program and/or data memory MEM is set before any code from the said memory can be executed. Unauthorized memory access by a user is effectively prevented in this way.

Due to this provision according to the invention, the memory interface 1 itself no longer needs to be modified if amended program and/or data memory configurations are to be used. Instead the configuration merely has to be reprogrammed in an easy way by writing amended offset values OFFSET_BOOT to the new program and/or data memory MEM that is to be used. This of course speeds up the design process when new products are created. In this way, the allocation of the memory areas can be changed simply by a change of the ROM mask. Hence, in the case of a ROM-mask product, the division of the memory areas SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5 can also be rearranged, at no extra expense, with each new ROM code.

In a further, very flexible, embodiment of the memory interface 1 according to the invention, the offset control means 4 are arranged to write offset values OFFSET_RT1, OFFSET_RT2 to the volatile offset memory 3 at the run time of the memory interface 1, thus enabling a memory segmentation to be changed by software means. For this purpose, the > offset control means 4 have an offset control input 6 and two offset configuration inputs 7, 8. As a function of software-controlled signals at the offset control input 6, the offset control means 4 read in offset values OFFSET_RT1 (via offset configuration input 7) or OFFSET_RT2 (via offset configuration input 8) and write these offset values to the volatile offset memory 3. In this way, the memory segmentation can be changed at the run time. The offset configuration inputs 7, 8 obtain the offset values OFFSET_RT1, OFFSET_RT2 by accessing non- volatile memories (not shown) in which the offset values OFFSET_RT1, OFFSET_RT2 are stored, the non-volatile memories comprising hard-wired circuits, mask- programmable locations, etc.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims. In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice- versa. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware or software. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A memory interface (1) for controlling access to a program and/or data memory (MEM) that is divided into a plurality of memory areas (SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5), comprising:

- address calculating means (2) for converting a logic memory address (iadr[O- i]) into a physical memory address (phys_adr[O-j]) by performing a logic operation on the logic memory address (iadr[O-i]) with an offset value (OFFSET_BOOT, OFFSET_RT1, 0FFSET_RT2) that is stored in a volatile offset memory (3) and that is assigned to the given memory area (SROM 0..SROM 5.5, EROM 0..EROM 7.5 and UROM 0..UROM 3.5), and

- offset control means (4) for writing the offset values (OFFSET_BOOT, OFFSET RTl , OFFSET_RT2) to the volatile offset memory (3), the offset control means (4) being arranged to read in at least one offset value (OFFSET_BOOT) from a preset address in the program and/or data memory (MEM).

2. A memory interface (1) as claimed in claim 1, wherein the offset control means are arranged to read in an offset value (OFFSETJBOOT) from a preset address in the program and/or data memory (MEM) and to write it to the volatile offset memory (3) at the initialization of the memory interface (1), and wherein the memory interface (1) is arranged to grant access to the program and/or data memory (MEM) only thereafter.

3. A memory interface (1) as claimed in claim 1, wherein the address calculating means (2) are arranged to receive at least one control signal (en_sysrom) for selecting memory areas (SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5) and to take account of the control signal in the conversion of the logic memory addresses (iadr[O-i]) into physical memory addresses (phys_adr[O-j]).

4. A memory interface (1) as claimed in claim 1, wherein the offset control means (4) are arranged to write offset values (OFFSETJRTl, 0FFSET_RT2) to the volatile offset memory (3) at the run time of the memory interface (1).

5. A memory interface (1) as claimed in claim 4, wherein the offset control means (4) comprise offset control inputs (6) and offset configuration inputs (7, 8) and are arranged to read in offset values (OFFSET-RTl, OFFSET_RT2) from one of the offset configuration inputs (7, 8) and to write them to the volatile offset memory (3), as a function of signals at the offset control inputs (6).

6. A memory arrangement, comprising a memory interface (1) as claimed in any of claims 1 to 5, and a program and/or data memory (MEM) that is divided into a plurality of memory areas (SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5) and that has preset memory locations at which offset values (OFFSET_BOOT) are stored.

7. A method of controlling access to a program and/or data memory (MEM) that is divided into a plurality of memory areas (SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5), a memory interface (1) performing the following steps: - read-in of at least one offset value (OFFSET_BOOT) from a preset address in the program and/or data memory (MEM),

- storage of the at least one offset value (OFFSET_BOOT) in a volatile offset memory (3),

- conversion of a logic memory address (iadr[O-i]) into a physical memory address (phys_adr[O-j]) by the performance of a logic operation on the logic memory address (iadr[O-i]) with an offset value (OFFSET_BOOT, OFFSET_RT1, 0FFSET_RT2) that is assigned to the given memory area (SROM 0..SROM 5.5, EROM 0..EROM 7.5, UROM 0..UROM 3.5) and that is stored in the offset memory (3).

8. A method as claimed in claim 7, wherein the read- in and storage of the offset value (OFFSET_BOOT) take place at the initialization of the memory interface (1) and access to the program and/or data memory (MEM) is granted only thereafter.

9. A method as claimed in claim 7, wherein at least one control signal (en_sysrom) for selecting the memory areas (SROM O..SROM 5.5,

EROM 0..EROM 7.5, UROM 0..UROM 3.5) is evaluated and taken into account when converting the logic memory addresses (iadr[O-i]) into physical memory addresses (phys_adr[O-j]).

10. A method as claimed in claim 7, wherein offset values (OFFSETJRT1,

OFFSET_RT2) are written to the volatile offset memory (3) at the run time of the memory interface (1).