CN109343794B - Configuration method and configuration device of memory - Google Patents
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Abstract
The invention discloses a configuration method and a configuration device of a memory. The memory configuration method comprises the following steps: determining a high potential chip selection in a plurality of chip selections of a memory; reading a configuration item of a sub-area of the memory at a low potential chip selection, and returning the configuration item to be written into the corresponding sub-area of the low potential chip selection; and when the write enable signal of the memory is at a high potential, reading and/or writing configuration items in the sub-area corresponding to the high-level chip selection. By the configuration method, data can be conveniently read and/or written only aiming at one subarea on the memory.
Description
Technical Field
The present invention relates to the field of computing and storage technologies, and in particular, to a configuration method and a configuration device for a memory.
Background
In an FPGA (Field-Programmable Gate Array), when there are a plurality of data to be configured, each data usually occupies a block of memory, and when the configuration bit width occupied by the data is much smaller than the width of the memory, space waste of the memory may be caused. For this reason, multiple configurations are placed on the same block of memory, however, this configuration approach does not facilitate the processor to issue or change a single configuration.
Disclosure of Invention
In order to solve the above problems, the present invention provides a memory configuration method and a memory configuration device.
In order to solve the above problem, the method for configuring a memory according to the present invention includes:
determining a high potential chip selection in a plurality of chip selections of a memory;
reading a configuration item of a sub-area of the memory at a low potential chip selection, and returning the configuration item to be written into the corresponding sub-area of the low potential chip selection;
and when the write enable signal of the memory is at a high potential, reading and/or writing configuration items in the sub-area corresponding to the high-level chip selection.
In the configuration method, the number of the high-potential chip selects is one, among the plurality of chips of the memory.
In the foregoing configuration method, the reading and/or writing of the configuration item in the sub-area corresponding to the high-level chip select includes:
the configuration item assignment on the sub-area corresponding to the high-level chip selection is output to the processor; and/or
And receiving an issuing configuration input by a processor, and filling the issuing configuration into a sub-area corresponding to the high-level chip selection.
In the above configuration method, the bit width of any one of the sub-regions is suitable for being filled in the issued configuration input by the processor.
Before determining a high-potential chip selection among a plurality of chips of the memory, the configuration method further includes:
configuring a plurality of sub-regions on a storage region according to width, wherein one sub-region corresponds to one group of configurations;
and setting a chip selection for each sub-area.
In the above configuration method, bit widths of the plurality of sub-regions are equal; or the bit widths of a plurality of said sub-regions are not completely equal.
In the configuration method, the memory is a memory of an FPGA.
To solve the above problems, the present invention provides a memory configuration device, comprising:
the determining module is used for determining high-potential chip selection in a plurality of chips of the memory;
the return module is used for reading the configuration items of the sub-area of the low-potential chip selection on the memory and returning the configuration items to be written into the corresponding sub-area of the low-potential chip selection;
and the read-write module is used for reading and/or writing the configuration items in the sub-area corresponding to the high-level chip selection when the write enable signal of the memory is at a high potential.
The above configuration device further includes:
the configuration module is used for configuring a plurality of sub-regions on a storage region according to width, and one sub-region corresponds to one group of configurations;
and the chip selection setting module is used for setting a chip selection for each sub-area.
The configuration method on the memory provided by the invention comprises the following steps: determining a high potential chip selection in a plurality of chip selections of a memory; reading a configuration item of a sub-area of the memory at a low potential chip selection, and returning the configuration item to be written into the corresponding sub-area of the low potential chip selection; and when the write enable signal of the memory is at a high potential, reading and/or writing configuration items in the sub-area corresponding to the high-level chip selection. By the configuration method, the configuration items can be conveniently read and/or written only aiming at one subarea on the memory.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a timing diagram of a cpu in an exemplary embodiment of the invention;
FIG. 2 is a flow chart of a method for configuring a memory according to an exemplary embodiment of the invention;
FIG. 3 is a diagram illustrating a configuration apparatus of a memory according to another exemplary embodiment of the invention.
Reference numerals:
100-configuring the device; 10-a determination module; 20-a return module; 30-read-write module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the specific embodiments of the present invention and the accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a timing diagram of a cpu interface, which is a relatively general cpu interface inside an FPGA. The interface consists of five sets of signals, which are cpu _ cs for the cpu chip select, cpu _ wen for the cpu write enable, cpu address cpu _ addr, data cpu _ din to be written by the cpu, and data cpu _ dout to be read by the cpu, respectively. As can be seen from fig. 1, cpu _ wen switches to the high level some time after cpu _ cs switches to the high level, and stays at the high level during the period that cpu _ cs stays at the high level.
Fig. 2 is a flowchart of a method for configuring a storage area according to an exemplary embodiment of the present invention. As shown in fig. 2, the method includes:
s1: determining a high potential chip selection in a plurality of chip selections of a memory;
s2: reading a configuration item of a sub-area of the memory at a low potential chip selection, and returning the configuration item to be written into the corresponding sub-area of the low potential chip selection;
and S3, when the write enable signal of the memory is at a high potential, reading and/or writing the configuration item in the sub-area corresponding to the high-level chip selection.
In S1, the memory has a plurality of chip selects, but normally, only one chip select is a high level chip select, and the remaining chip selects are low level chip selects.
In S2, for a low level chip select, the configuration item of the sub-region corresponding to the low level is read, and the configuration item is returned into the sub-region of the corresponding low level chip select. That is, in the sub-area of the low potential chip select, the configuration items thereon remain unchanged.
For example, the memory has 4 sub-regions, the bit width of each sub-region is assumed to be 1bit, then the 4 sub-regions are bit [0], bit [1], bit [2] and bit [3], respectively, in step S1, when the chip selection cpu _ cs0 corresponding to bit [0] is at a high level, meaning that cpu _ cs1, cpu _ cs2 and cpu _ cs3 are at a low level, then in step S2, the configuration items on bit [1], bit [2] and bit [3] remain unchanged.
In S3, the write enable signal of the memory is pulled high, and the write enable signal is pulled high after the cup _ cs signal is pulled high (see fig. 1). Due to the fact that the write enable is pulled high, the sub-area corresponding to the high-level chip selection can be read and/or written with the configuration item.
Specifically, S3 may include S31: and receiving an issuing configuration input by the processor, and filling the issuing configuration into the sub-area corresponding to the high-level chip selection, so that the processor only writes data into the sub-area corresponding to the high-level chip selection. S32 may also be included in S3: and assigning the configuration items on the sub-area corresponding to the high-level chip selection and outputting the assignment items to the processor, thereby realizing the output of the sub-area corresponding to the high-level chip selection to the processor.
In S3, the bit width of each sub-region can be suitable for filling the issued configuration input by the processor, in other words, the bit width of any sub-region should not be smaller than the bit width of the issued configuration.
For example, the memory has 4 sub-regions, namely bit [0], bit [1], bit [2] and bit [3], in step S1, when the chip select cpu _ cs0 corresponding to bit [0] is at a high level, meaning that cpu _ cs1, cpu _ cs2 and cpu _ cs3 are at a low level, in step S2, the configuration items on bit [1], bit [2] and bit [3] remain unchanged, i.e., ram _ din [1] ═ ram _ out [1], ram _ din [2] ═ ram _ out [2], and ram _ din [3] ═ ram _ out [3 ]. After the write enable is at the high level in step S3, in S4, ram _ din [0] ═ cpu _ din [0], and cpu _ dout [0] ═ ram _ dout [0 ].
When the chip select cpu _ cs1 corresponding to bit [1] is at a high level, which means that cpu _ cs0, cpu _ cs2 and cpu _ cs3 are at a low level, in step S2, the configuration items on bit [0], bit [2] and bit [3] remain unchanged, that is, ram _ din [0] ═ ram _ out [0], ram _ din [2] ═ ram _ out [2], ram _ din [3] ═ ram _ out [3], and ram _ din [1] ═ cpu _ din [0], and cpu _ dout [0] ═ ram _ dout [1 ].
In the embodiment of the present invention, the first and second substrates,
ram write enable equation:
ram_wen＝(cpu_cs3|cpu_cs2|cpu_cs1|cpu_cs0)&cpu_wen；
ram write address equation:
ram_addr[10:0]＝cpu_addr[10:0]；
ram write data equation:
ram_din[0]＝(cpu_cs0＝＝1'd1)？cpu_din[0]:ram_dout[0]；
ram_din[1]＝(cpu_cs1＝＝1'd1)？cpu_din[0]:ram_dout[1]；
ram_din[2]＝(cpu_cs2＝＝1'd1)？cpu_din[0]:ram_dout[2]；
ram_din[3]＝(cpu_cs3＝＝1'd1)？cpu_din[0]:ram_dout[3]；
cpu reads data equation:
cpu_dout[0]＝(cpu_cs0＝＝1'd1)？ram_dout[0]:1'd0；
cpu_dout[0]＝(cpu_cs1＝＝1'd1)？ram_dout[1]:1'd0；
cpu_dout[0]＝(cpu_cs2＝＝1'd1)？ram_dout[2]:1'd0；
cpu_dout[0]＝(cpu_cs3＝＝1'd1)？ram_dout[3]:1'd0；
before step S1, S01 and S02 are also included.
Wherein, S01: on one memory region, a plurality of sub-regions are arranged according to width, and one sub-region corresponds to one group of arrangement. The bit widths of the sub-regions may be completely equal, may not be completely equal, or may be in an equal difference form, which is not described in detail herein.
And S02, setting a chip selection for each sub-region to facilitate independent reading and writing of any sub-region in the follow-up process, and facilitating the issue or change of a single configuration by the processor.
The memory in the embodiment of the present invention may be a memory of an FPGA (Field-Programmable Gate Array).
Fig. 3 is a schematic structural diagram of a configuration apparatus of a storage area in a further exemplary embodiment of the invention. As shown in fig. 3, the configuration apparatus 100 of the memory includes a determination module 10, a return module 20, and a read/write module 30.
And the determining module 10 is used for determining a high potential chip selection in a plurality of chips of the memory. In the determination process of the determination module 10, the memory has a plurality of chip selects, but normally, only one chip select is a high-level chip select, and the other chip selects are low-level chip selects.
A returning module 20, configured to read a configuration item of the sub-area on the memory at the low-potential chip select, and return the configuration item to be written into the corresponding sub-area of the low-potential chip select. Specifically, for a low-level chip selection, the configuration item of the sub-region corresponding to the low level is read, and the configuration item is returned to the sub-region of the corresponding low-level chip selection. That is, in the sub-area of the low potential chip select, the configuration items thereon remain unchanged.
And a read-write module 30, configured to, when a write enable signal of the memory is at a high potential, perform configuration item reading and/or writing in a sub-area corresponding to the high-level chip select.
Wherein the write enable signal of the memory is pulled high, the clock of which is after the cup _ cs signal is pulled high (see fig. 1).
The read-write module 30 may include a read sub-module and a write sub-module. The write sub-module is used for receiving the issuing configuration input by the processor and filling the issuing configuration into the sub-area corresponding to the high-level chip selection, so that the processor can write data into the sub-area corresponding to the high-level chip selection only. And the reading submodule is used for assigning the configuration items on the sub-area corresponding to the high-level chip selection and outputting the assignment items to the processor, so that the sub-area corresponding to the high-level chip selection is output to the processor.
In the read/write module 30, the bit width of each sub-region should be suitable for filling the issued configuration input by the processor, in other words, the bit width of any sub-region should not be smaller than the bit width of the issued configuration.
For example, the memory has 4 sub-regions, the bit width of each sub-region is assumed to be 1bit, then the 4 sub-regions are bit [0], bit [1], bit [2] and bit [3], respectively, and in step S1, when the chip selection cpu _ cs0 corresponding to bit [0] is at a high level, meaning that cpu _ cs1, cpu _ cs2 and cpu _ cs3 are at a low level, then in step S2, the configuration items on bit [1], bit [2] and bit [3] remain unchanged, that is, ram _ din [1] ═ ram _ out [1], ram _ din [2] ═ ram _ out [2], and ram _ din [3] ═ ram _ out [3 ]. After the write enable is at the high level in step S3, in S4, ram _ din [0] ═ cpu _ din [0], and cpu _ dout [0] ═ ram _ dout [0 ].
When the chip select cpu _ cs1 corresponding to bit [1] is at a high level, which means that cpu _ cs0, cpu _ cs2 and cpu _ cs3 are at a low level, in step S2, the configuration items on bit [0], bit [2] and bit [3] remain unchanged, ram _ din [0] ═ ram _ out [0], ram _ din [2] ═ ram _ out [2], ram _ din [3] ═ ram _ out [3], and ram _ din [1] ═ cpu _ din [0], and cpu _ dout [0] ═ ram _ dout [1 ].
In the embodiment of the present invention, ram write enable equation:
ram_wen＝(cpu_cs3|cpu_cs2|cpu_cs1|cpu_cs0)&cpu_wen；
ram write address equation:
ram_addr[10:0]＝cpu_addr[10:0]；
ram write data equation:
ram_din[0]＝(cpu_cs0＝＝1'd1)？cpu_din[0]:ram_dout[0]；
ram_din[1]＝(cpu_cs1＝＝1'd1)？cpu_din[0]:ram_dout[1]；
ram_din[2]＝(cpu_cs2＝＝1'd1)？cpu_din[0]:ram_dout[2]；
ram_din[3]＝(cpu_cs3＝＝1'd1)？cpu_din[0]:ram_dout[3]；
cpu reads data equation:
cpu_dout[0]＝(cpu_cs0＝＝1'd1)？ram_dout[0]:1'd0；
cpu_dout[0]＝(cpu_cs1＝＝1'd1)？ram_dout[1]:1'd0；
cpu_dout[0]＝(cpu_cs2＝＝1'd1)？ram_dout[2]:1'd0；
cpu_dout[0]＝(cpu_cs3＝＝1'd1)？ram_dout[3]:1'd0；
the configuration apparatus 100 of the memory according to the embodiment of the present invention further includes a configuration module and a chip select setting module.
The configuration module is used for configuring a plurality of sub-regions on one storage region according to width, and one sub-region corresponds to one group of configurations. The bit widths of the sub-regions may be completely equal, may not be completely equal, or may be in an equal difference form, which is not described in detail herein.
And the chip selection setting module is used for setting a chip selection for each sub-area so as to facilitate independent reading and writing of any sub-area subsequently and facilitate the issue or change of a single certain configuration by the processor.
The memory in the embodiment of the present invention may be a memory of an FPGA (Field-Programmable Gate Array).
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method of configuration on a memory, comprising:
determining a high potential chip selection in a plurality of chip selections of a memory;
reading a configuration item of a sub-area of the memory at a low potential chip selection, and returning the configuration item to be written into the corresponding sub-area of the low potential chip selection;
when the write enable signal of the memory is at a high potential, reading and/or writing configuration items in a sub-region corresponding to the high potential chip selection;
and one high-potential chip is selected from a plurality of chips of the definite memory.
2. The configuration method according to claim 1, wherein the reading and/or writing of the configuration item in the sub-region corresponding to the high-potential chip select comprises:
assigning and outputting configuration items on the sub-regions corresponding to the high-potential chip selection to a processor; and/or
And receiving an issuing configuration input by a processor, and writing the issuing configuration into a sub-area corresponding to the high-potential chip selection.
3. The method of claim 2, wherein the bit width of any of said sub-regions is adapted to fill in a down-send configuration of said processor input.
4. The method of claim 1, wherein prior to determining a high chip select among a plurality of chips of the memory, further comprising:
configuring a plurality of sub-regions on a storage region according to width, wherein one sub-region corresponds to one group of configurations;
and setting a chip selection for each sub-area.
5. The method of claim 4, wherein a plurality of said sub-regions are equal in bit width; or the bit widths of a plurality of said sub-regions are not completely equal.
6. The method of claim 1, wherein the memory is a memory of an FPGA.
7. An apparatus for configuring a memory, comprising:
the determining module is used for determining high-potential chip selection in a plurality of chips of the memory;
the return module is used for reading the configuration items of the sub-area of the low-potential chip selection on the memory and returning the configuration items to be written into the corresponding sub-area of the low-potential chip selection;
the read-write module is used for reading and/or writing configuration items in a sub-area corresponding to the high-potential chip selection when a write enable signal of the memory is at a high potential;
and one high-potential chip is selected from a plurality of chips of the definite memory.
8. The configuration device according to claim 7, further comprising:
the configuration module is used for configuring a plurality of sub-regions on a storage region according to width, and one sub-region corresponds to one group of configurations;
and the chip selection setting module is used for setting a chip selection for each sub-area.
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