JP2008511896A - MEMORY INTERFACE, MEMORY CONFIGURATION, AND MEMORY ACCESS CONTROL METHOD - Google Patents

Abstract

  A memory interface (1 that controls access to a program memory and / or data memory (MEM) divided into a plurality of memory areas (SROM0 to SROM5.5, EROM0 to EROM7.5, UROM0 to UROM3.5) ) Is disclosed. The memory interface (1) is assigned to a given memory area (SROM-SROM5.5, EROM0-EROM7.5, UROM0-UROM3.5) and stored in a volatile offset memory (3) The logical memory address (iadr [0-i] is changed to the physical memory address (iadr [0-i]) by performing a logical operation on the logical memory address (iadr [0-i]) using the values (OFFSET BOOT, OFFSET RT1, OFFSET RT2). address calculation means (2) for converting into phys adr [0-j]), so that at least one offset value (OFFSET BOOT) is read from a preset address in the program memory and / or data memory (MEM) It is.

Description

  The present invention relates to a memory interface for controlling access to a program memory and / or a data memory divided into a plurality of memory areas, and using a offset value assigned to a given memory area as a logical memory The present invention relates to a memory interface including address calculation means for converting a logical memory address into a physical memory address by performing a logical operation on the address.

  The invention also relates to a memory arrangement comprising a memory interface according to the invention.

  Finally, the present invention is also a method for controlling access to a program memory and / or data memory divided into a plurality of memory areas, wherein a memory interface is assigned to a given memory area The present invention relates to a method for converting a logical memory address into a physical memory address by performing a logical operation on the logical memory address using an offset value.

  Program memory and data memory having logically and physically different areas are well known in the prior art. Thus, for example, a microcontroller-based integrated circuit (IC) developed by the Applicant for the implementation of an automotive immobilizer has the logic of the program memory MEM as shown in the left part of FIG. There is a split. The above logical division of the program memory MEM has a system area SROM0-SROM5.5 each having a memory block of size 256 bytes and two user areas, i.e. each having a memory block size of 256 bytes. A first user area EROM0 to EROM7.5 and a second user area UROM0 to UROM3.5 each having a memory block size of 256 bytes. As an option, a test area (not shown) may be present. Individual memory locations in the system area and user area are accessed by logical addresses iadr [0-12], and bits iadr [0] through iadr [7] address individual memory locations within a given memory block. Bits iadr [8] to iadr [12] are used to select a memory block. In addition, a control signal en_system used to distinguish the logical system memory areas SROM0 to SROM5.5 from the logical user memory areas EROM0 to EROM7.5 and UROM0 to UROM3.5 is provided. When the control signal en_system is 1, the system memory areas SROM0 to SROM5.5 are accessed, and when the control signal en_system is 0, the user memory areas EROM0 to EROM7.5 and UROM0 to UROM3.5 are accessed. In the illustrated embodiment, the function of the control signal en_system is in principle equivalent to the 14th address bit. As can be seen, only a portion of the address space that can be accessed using logical addressing is used. An unused memory block in the system memory areas SROM0 to SROM5.5, and the user memory areas EROM0 to EROM7.5 and URON0 to UROM3.5 is indicated by X in FIG. Furthermore, the logical memory areas SROM0 to SROM5.5, EROM0 to EROM7.5, UROM0 to UROM3.5 are shown by way of example in the right part of FIG. 1 showing two memory modules MEM1 and MEM2 in the form of a schematic diagram. Also, it may be divided between different physical memories. The logical system memory areas SROM0 to SROM5.5 and the second user areas UROM0 to UROM3.5 are accommodated in the memory module MEM1, but only the first user memory areas EROM0 to EROM7.5 are stored in the memory module MEM2. Placed in. The first memory module MEM1 is completely occupied by the system memory areas SROM0 to SROM5.5 and the second user memory areas UROM0 to UROM3.5, and the second memory module MEM2 is the first user memory. It can be seen that there are no unused physical memory areas that are completely occupied by the areas EROM0 to EROM7.5. The individual memory modules MEM1 and MEM2 can be selected from various types of memory, the memory module MEM1 can take the form of a ROM that can be written only once, and the memory module MEM2 can be rewritten. It can take the form of possible EEPROM or flash memory.

  Since the system memory areas SROM0 to SROM5.5 and the user memory areas EROM0 to EROM7.5 and UROM0 to UROM3.5 are logically addressed, the memory interface assigns logical addresses iadr [0-12] to the individual addresses. It is necessary to map to the correct physical address of the memory modules MEM1, MEM2. In the embodiment shown in FIG. 1, the relationship between logical addresses and physical addresses in the system memory areas SROM0 to SROM5.5 and the first user memory areas EROM0 to EROM7.5 is straightforward. However, for the second user memory areas UROM0 to UROM3.5, a calculation unit for subtracting the offset from the logical address iadr [0 to 12] is required to determine the physical address. Furthermore, the logical address iadr [0-12] needs to be assigned to the correct physical memory module MEM1.

  To date, it has been known that it is disadvantageous that a separate memory interface needs to be designed for each product having various memory configurations. Therefore, the circuit design had to be adapted when there was a change in memory size and / or type. It is impossible to change the memory area allocation later. In ROM mask products, only the program can be changed, and the physical size of the memory cannot be changed. There is also almost no possibility of balancing the size of the memory area. Thus, memory required in some other area may remain unused in a memory area.

  It is an object of the present invention to provide a memory interface of the type specified in the first paragraph in which the above disadvantages are avoided, a memory configuration of the type specified in the second paragraph, and the third And a memory access control method of the kind specified in the paragraph.

  To achieve the above object, a memory interface as detailed in the first paragraph is an offset control means for writing an offset value into a volatile offset memory, comprising a program memory and / or a data memory. It is defined that the apparatus further comprises an offset control means configured to read at least one offset value from the preset address.

  To achieve the above object, a memory interface according to the present invention, a program memory and / or a data memory having a preset memory location divided into a plurality of memory areas and storing offset values; A memory configuration comprising

  Finally, a method as detailed in the beginning, wherein at least one offset value is read from a preset address in the program memory and / or data memory before the address translation. The method stored in is defined.

  What is achieved with the features according to the present invention is that when a different memory configuration is required for a new product, it is not necessary to change the memory interface itself. All that needs to be reprogrammed is the memory configuration. This speeds up the design process as new products are made. Thus, in the case of ROM equivalents, it is only necessary to replace the memory and reprogram the configuration, which is a non-volatile scheme at the preset memory location in the program memory and / or data memory. This is done by writing a new offset value. No further design change steps are required. The memory area allocation can be changed simply by changing the ROM mask. Therefore, in the case of a ROM mask product, it is even possible to reconfigure the memory area division with only a new ROM code without extra cost. This is particularly advantageous if the ROM is the only memory used, since no other memory is required to store the memory configuration. Furthermore, the hardware-based nature of the sequence of writing the offset value to the volatile offset memory by the offset control means offers the advantage that unauthorized memory access by the user is avoided, but for example more memory If new system programs are implemented that require space or different memory partitioning, the memory segmentation can still be modified by software means.

  The offset control means is configured to read the offset value from the preset address of the program memory and / or data memory and write it to the volatile offset memory at the initialization of the memory interface, and only after that the memory It is advantageous if the interface is configured to allow access to program memory and / or data memory. Advantageously, the memory interface can only be used by the program or execute program code after the correct offset value has been written to the offset memory. Thus, forbidden memory accesses can be eliminated.

  It is advantageous if the address calculating means is configured to receive at least one control signal for selecting a memory area and to take this control signal into account when the logical memory address is converted into a physical memory address. It is. This provides the advantage that the logical memory area is configured in a very flexible manner and can be selectively accessed. For example, an individual control line is assigned to each logical memory area (system area, user area), and a logical memory area is selected by selectively applying a signal to one of those control logic lines. While access to other logical memory areas is blocked at the same time.

  It is also advantageous if the offset control means is arranged to write the offset value to the volatile offset memory at the time of execution of the memory interface, since in this way the memory interface can be reconfigured at runtime.

  Finally, the offset control means comprises an offset control input and an offset configuration input, configured to read the offset value from one of the offset configuration inputs and write the offset value to the volatile offset memory in response to the signal of the offset control input This is also advantageous. In this way, the memory interface can be reconfigured at runtime in a preset manner. For this purpose, the offset control input operable by the program causes the offset control means to read the offset value via the offset configuration input, and the offset configuration input accesses the nonvolatile memory in which the offset value is stored to obtain the offset value. Supply. The non-volatile memory can include a hard-wired circuit, a mask programmable storage location, and the like.

  These and other aspects of the invention will be apparent from and will be elucidated with reference to the embodiments described hereinafter, but the invention is not limited thereto.

  FIG. 2 is a block circuit diagram illustrating one embodiment of a memory configuration and memory interface 1 according to the present invention, by which the logical and physical partitioning of the memory shown in FIG. Is given. This memory arrangement comprises a program memory and / or a data memory MEM with the two memory modules MEM1 and MEM2 of FIG. 1, the memory module MEM1 taking the form of a once writable ROM, for example, Module MEM2 takes the form of a rewritable EEPROM or flash memory, for example. Individual storage locations in the memory modules MEM 1 and MEM 2 are accessible by the physical address bus 9. Those data (indicated as “data”) can be read by the data bus 11, and in the case of the rewritable memory module MEM 2, can also be read via the data bus 11. . Note that for the purposes of the present invention, it is not an essential issue whether the logical or physical partition of the memory MEM is composed of blocks or whether the addressing is linear. In the case of the block configuration memory MEM, the size of the memory block is also not essential. As previously described in the related description of FIG. 1, the program memory and / or data memory MEM is separated into different logical system memory areas on different modules consisting of two physical memory modules MEM1 and MEM2. SROM0 to SROM5.5, and two logical user memory areas UROM0 to UROM3.5 and EROM0 to EROM7.5 are provided. The memory interface 1 according to the present invention operates to perform a correct translation from the logical memory address iadr [0-i] to the physical memory address phys_adr [0-j].

  The memory interface 1 comprises address calculation means 2 in the form of hardware. The address calculation means 2 has an input of a logical address bus 10, which in the illustrated embodiment comprises 13 address lines that match the memory configuration shown in FIG. . The address calculation means 2 is also used to select the input of the control line 12, ie logical system memory area SROM0-SROM5.5, or logical user memory area UROM0-UROM3.5 and EROM0-EROM7.5. The control signal en_system is also provided. In the illustrated embodiment, the system memory areas SROM0-SROM5.5 are accessed when the control signal en_system is at logic 1 level, and the user memory areas UROM0-UROM3.5 and EROM0-EROM7.5 are controlled by the logic control signal en_system. Since it is accessed at the 0 level, the function of the control line 12 is equivalent to the function of the additional address line. Individual memory locations are addressed by logical memory addresses iadr [0-i].

  However, it should be noted that multiple control lines may be provided according to the present invention (not shown in the figure). In this case, each of these control lines can be used to communicate with one logical memory area SROM0-SROM5.5, UROM0-UROM3.5, EROM0-EROM7.5, or on these control lines. Signal combinations can also be used to communicate with combinations of logical memory areas SROM0-SROM5.5, UROM0-UROM3.5, EROM0-EROM7.5.

  Through the logical address bus 10 and control line 12, the logical memory addresses iadr [0-i] at the system memory location and the user memory location are supplied to the address calculation means 2. In addition, selection information is sent to the means regarding whether the addressed system memory area SROM0-SROM5.5, or one of the user memory areas UROM0-UROM3.5 or EROM0-EROM7.5. These logical memory addresses iadr [0 to i] and selection information are converted by the address calculation means 2 into physical memory addresses phys_adr [0 to j] of the physical memory modules MEM1 and MEM2. Furthermore, the address calculation means 2 generates chip select signals CS1 and CS2 that allow the individual memory modules MEM1 and MEM2 to be selectively accessed.

  The address calculation means 2 transfers the logical memory address iadr [0-i] received through the logical address bus 10 to the physical memory address phys_adr [0-j] assigned to each memory location of the memory modules MEM1 and MEM2. Convert. At that time, the address calculation means performs a logical operation on the logical memory address iadr [0 to I] using the preset offset values OFFSET_BOOT, OFFSET_RT1, and OFFSET_RT2. In a preferred simple embodiment, the logical operation comprises the addition or subtraction of the offsets OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 to or from the logical memory addresses iadr [0-i]. However, the present invention is not limited to this type of logical operation. As another example, a logical operation in another form will be described. A plurality of offsets OFFSET_BOOT, OFFSET_RT1, and OFFSET_RT2 to the logical memory address iadr [0 to i] when converted to the physical memory address phys_adr [0 to j] Addition and addition or subtraction of the sum of offsets to or from the logical memory address iadr [0-i], or additional memory address replacement considerations, or additional memory block size There is multiplication.

  The address output of the address calculation means 2 is connected to the physical address bus 9, and the determined physical memory address phys_adr [0-j] is written through the bus. Instead of one physical address bus 9 and a plurality of chip select signals CS1, CS2, a plurality of physical address buses 9 or possible combinations thereof may be used.

  In the prior art, the offset value used for the logical operation is fixed and stored in the non-volatile memory of the memory interface 1, but the memory interface 1 according to the present invention takes the form of, for example, a flip-flop or a latch. Volatile offset memory 3 can be provided, and offset values OFFSET_BOOT, OFFSET_RT1, OFFSET_RT2 can be written to the offset memory 3, and these offset values are stored in memory addresses iadr [0 to i]. Is read out from the offset memory 3 by the address calculation means 2 later. In this case, the offset values OFFSET_BOOT, OFFSET_RT1, and OFFSET_RT2 are written into the offset memory 3 by the offset control means 4 mounted on the memory interface 1 in the form of hardware.

  According to the invention, during the initialization of the memory interface 1, the offset control means 4 is indicated symbolically by the arrow 5 in this example from the preset storage location in the program memory and / or the data memory MEM. To read the offset value OFFSET_BOOT from the memory module MEM1 and write the offset value OFFSET_BOOT to the volatile offset memory 3, thereby causing the memory interface 1 to boot with the correct offset value OFFSET_BOOT. Is done. It is useful that the offset value OFFSET_BOOT is written to the memory module MEM1 segmented into a plurality of memory areas, preferably the individual offset configuration of the memory module MEM1 is also stored in the memory module MEM1. Please note that. Further, as indicated symbolically by the enable signal en_ad, the offset calculation means 4 disables the address calculation means 2 until the offset values OFFSET_BOOT, OFFSET_RT1 and OFFSET_RT2 are completely written to the volatile offset memory 3. It is also provided that access to the program memory and / or data memory MEM is only allowed after completion. Any code from the memory cannot be executed until the correct segmentation of the program memory and / or data memory has been set by initialization of the memory interface 1 implemented by hardware means. In this way, unauthorized memory access by the user is actually prevented.

  With this correspondence according to the invention, it is no longer necessary to change the memory interface 1 itself, even if a modified program memory and / or data memory configuration is used. Instead, the configuration need only be reprogrammed in an easy way by writing the modified offset value OFFSET_BOOT to the new program memory and / or data memory MEM to be used. is there. Of course, this speeds up the design process as new products are made. In this way, the memory area allocation can be changed simply by changing the ROM mask. Therefore, in the case of ROM mask products, the division of the memory areas SROM0 to SROM5.5, EROM0 to EROM7.5, UROM0 to UROM3.5 can also be reconfigured using each new ROM code without extra cost. Be able to be.

  In a further very flexible embodiment of the memory interface 1 according to the invention, the offset control means 4 is arranged to write the offset values OFFSET_RT1, OFFSET_RT2 to the volatile offset memory 3 when the memory interface 1 is executed. , Whereby the memory segmentation is changed by software means. For this purpose, the offset control means 4 comprises one offset control input 6 and two offset configuration inputs 7, 8. Depending on the software-controlled signal at the offset control input 6, the offset control means 4 reads the offset value OFFSET_RT1 (from the offset configuration input 7) or OFFSET_RT2 (from the offset configuration input 8) and reads those offset values. Write to volatile offset memory 3. In this way, the memory segmentation can be changed at runtime. Offset configuration inputs 7 and 8 obtain offset values OFFSET_RT1 and OFFSET_RT2 by accessing a nonvolatile memory (not shown) in which offset values OFFSET_RT1 and OFFSET_RT2 are stored, including hard-wired circuits and mask programmable positions. To do.

  The embodiments described above are illustrative rather than limiting on the present invention, and thus many alternative embodiments will occur to those skilled in the art without departing from the scope of the invention as defined by the appended claims. Note that can be designed. In the claims, any reference signs placed between parentheses shall not be construed as limiting the scope of the claim. Terms such as “comprising” or “comprising” do not exclude the presence of elements or steps other than those listed in any claim or specification. A reference to an element in the singular does not exclude a reference to the element in the plural and vice versa. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware or software. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.

It is a figure which shows an example of a memory structure provided with the three logical memory area | region divided | segmented into two physical memory modules. FIG. 3 is a schematic block circuit diagram of a memory configuration and a memory interface according to the present invention.

Claims (10)

A memory interface for controlling access to a program memory and / or a data memory divided into a plurality of memory areas,
Address calculating means for converting the logical memory address into a physical memory address by performing a logical operation on the logical memory address using an offset value stored in a volatile offset memory and assigned to the given memory area When,
Offset control means for writing the plurality of offset values to the volatile offset memory, wherein the offset control is configured to read at least one offset value from a preset address of the program memory and / or data memory And a memory interface.   Upon initialization of the memory interface, the offset control means is configured to read an offset value from a preset address of the program memory and / or data memory and write the offset value to the volatile offset memory. The memory interface of claim 1, wherein the memory interface is configured to allow access to the program memory and / or data memory only after the writing.   The address calculating means receives at least one control signal for selecting a plurality of memory areas and considers the control signal when converting the plurality of logical memory addresses to a plurality of physical memory addresses. The memory interface of claim 1, wherein:   The memory interface of claim 1, wherein the offset control means is configured to write a plurality of offset values to the volatile offset memory during execution of the memory interface.   The offset control means comprises a plurality of offset control inputs and a plurality of offset configuration inputs, and reads a plurality of offset values from one of the plurality of offset configuration inputs, and a plurality of offset control inputs. The memory interface of claim 4, wherein the offset control means is configured to write the plurality of offset values to the volatile offset memory in response to a signal.   6. The memory interface according to claim 1 and a program memory and / or data memory comprising a plurality of preset memory locations which are divided into a plurality of memory areas and in which a plurality of offset values are stored. Memory configuration with memory. A method for controlling access to a program memory and / or data memory divided into a plurality of memory areas, the memory interface comprising:
Reading at least one offset value from a preset address of the program memory and / or data memory;
Storing the at least one offset value in a volatile offset memory;
Converting the logical memory address to a physical memory address by performing a logical operation on the logical memory address using an offset value stored in the offset memory and assigned to the given memory area; How to implement.   8. The method of claim 7, wherein the reading and storing of the offset value is performed at initialization of the memory interface, and only thereafter is access to the program memory and / or data memory permitted.   8. The method of claim 7, wherein at least one control signal for selecting the plurality of memory regions is evaluated and taken into account when converting the plurality of logical memory addresses to a plurality of physical memory addresses. .   The method of claim 7, wherein a plurality of offset values are written to the volatile offset memory during execution of the memory interface.

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