EP1620858A1 - Composant pourvu d'un ensemble circuit logique a fonctionnalite configurable - Google Patents

Composant pourvu d'un ensemble circuit logique a fonctionnalite configurable

Info

Publication number
EP1620858A1
EP1620858A1 EP04722859A EP04722859A EP1620858A1 EP 1620858 A1 EP1620858 A1 EP 1620858A1 EP 04722859 A EP04722859 A EP 04722859A EP 04722859 A EP04722859 A EP 04722859A EP 1620858 A1 EP1620858 A1 EP 1620858A1
Authority
EP
European Patent Office
Prior art keywords
component according
resistance
data line
tmr
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP04722859A
Other languages
German (de)
English (en)
Other versions
EP1620858B1 (fr
Inventor
Joachim Bangert
Christian Siemers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP1620858A1 publication Critical patent/EP1620858A1/fr
Application granted granted Critical
Publication of EP1620858B1 publication Critical patent/EP1620858B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/80—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches

Definitions

  • the invention relates to a component with a logic circuit arrangement that can be configured in terms of its functionality, comprising a plurality of data lines.
  • Configurable components have been known for a long time and, after they preferably perform logic functions, they are generally referred to as programmable logic devices (PLDs). Such PLD components are mainly used for less complex tasks.
  • PLDs programmable logic devices
  • Such logic modules are e.g. B. from US 4,870,302 or the publication “Ranmuthu, IW et al.; Magneto-resistive elements - An Alternative to Floating Gate Technology; In: Proceedings of the Midwest Symposiums on Circuits and Systems, 1992, pg (s). 134-136 vol. 1 "known.
  • the application program for such logic modules is defined during booting: a program is read from a program memory, configurable areas are configured.
  • the configurable areas have the following properties: Either they define links between specified points (routing areas) or they define the processing of logical input signals to logical output signals (logic cell areas).
  • the programming information is thus distributed in the area.
  • the configurability of the PLD 's is limited to a few configurable parameters that are permanently set during booting.
  • Two memories are required: an external boot memory chip (discrete chip, e.g. an EEPRO 113 in US 4,870,302) and internal, memory cells distributed over a large area (e.g. according to FIGS. 3a and 10a in US 4,870,302 or 5 in the publication by Ranmuthu at al.).
  • the local memory cells contain the information for the links and for the logic functions of the cells.
  • Essential parameters for evaluating the performance of these storage systems are the space requirement and the static (leakage) energy consumption as static "costs" as well as the switching speed and capacity as dynamic "costs".
  • SRAM non-volatile, reconfigurable architectures
  • Boot-ROM EEPROM
  • the SRAM is a relatively large cell, has a fast operating speed and is volatile memory, whereas the boot ROM is slow and non-volatile.
  • the EEPROM is a medium-sized cell with slow working speed, high configuration power requirements and low "reading" power consumption.
  • the area and power dissipation efficiency of the distributed memory cells is approximately up to two orders of magnitude worse than that of discrete memory chips with the same performance.
  • the application program requires less performance than the chips provide, the unused areas also inevitably consume power loss.
  • Typical levels of utilization of the existing logic blocks of PLDs are approx. 30% to 70%. At a certain point in time, only a fraction of them are actively involved in processing logic information.
  • a component in particular in the form of a logic circuit arrangement, has a large number of data lines which link the individual functional elements of the circuit arrangement to one another, that is to say to connect logic cells to one another, to define the routing area or to determine other signal connections.
  • the data lines thus define the data or signal transfer path, that is the link between predetermined points and the signal processing.
  • the configured course of the data lines therefore plays an important role in the configuration.
  • the invention is based on the problem of specifying a possibility of being able to influence the course or state of a data line in the configuration in a simple manner.
  • a component of the type mentioned is provided, at least one part of the data lines being assigned at least one element which can be switched between two states with different discrete resistances, via which element the data line is released or blocked, depending on the switched state, the switching state the element is non-volatile and can be switched quickly.
  • the data line depending on the circuit-related resistance of the element either being released, that is to say data can be transferred, or else being blocked, ie the data transfer being interrupted.
  • the data line can be released or opened very quickly.
  • the data line connecting a source and a part connected downstream thereof, for example a gate is enabled (low resistance) or blocked (high resistance) by the change in resistance of the element.
  • the signal is either short-circuited (low resistance) or the element does not appear (high resistance), the signal is passed unhindered over the data line.
  • low-resistance behavior means data line is constant (eg positive pole), information is blocked. If the component is switched to high resistance, it behaves as a pull-up resistor, the source signal runs over the data line.
  • the change in resistance can be stored in a suitable manner without further energy supply and is therefore always available. It would be advantageous if the change could be carried out at any time, without restricting the number of cycles and also at high speed.
  • the changeover speed should be ⁇ 3ns.
  • TMR tunnel magnetoresistive
  • Such magnetoresistive elements are characterized in that their resistance behavior is determined by the position of the magnetization of a soft magnetic information layer with respect to a hard magnetic reference layer. Depending on whether the magnetizations are parallel or antiparallel to each other, a low or high resistance is realized across the element.
  • the change in the direction of magnetization of the soft magnetic layer can be carried out in a simple and quick manner, for which purpose a configuration current pulse, which is conducted via a configuration conductor and which generates a magnetic field acting on the magnetization of the soft magnetic layer, is used.
  • the element can also show a change in resistance due to a phase change generated during switching, in particular from an amorphous state to a crystalline state.
  • OUM Ovonic Unified Memory
  • a phase change cell based on this effect is a memory whose storage mechanism is based on a reversible structural phase change from an amorphous phase to a crystalline phase.
  • a chalcogenide alloy material in the form of a thin film can be used as the phase change material.
  • the resistance changes between two discrete values, ie here, too, there is a change between a high and a low resistance when switching. It is therefore a quickly programmable resistance memory.
  • Binary systems e.g. GaSb, InSb, InSe, Sb 2 Te 3 , GeTe
  • tertiary systems e.g.
  • the switching process can take place with low switching voltages, with a current pulse with a control voltage above the threshold voltage of the cell being used for switching.
  • the cell information is also read out here via the set resistance.
  • a phase change cell is for example in the published website http: // www. Ovonyx. com / tech_html .html.
  • a pass transistor (connected in the data line) is blocked or released via the element.
  • This pass transistor is switched via the element assigned to it.
  • the Opening or releasing the data line is thus controlled indirectly or indirectly via the element that switches the pass transistor connected directly into the data line.
  • the current or total current conducted via one element or, for example, two coupled elements is applied to the gate input of the pass transistor, which is preferably designed as a MOS transistor. Depending on how large this control voltage is, the pass transistor is switched through or blocked. If it is switched through, the data line into which the transistor is connected is released.
  • the data line is blocked at the same time, information cannot be transmitted via it. If the element is connected in parallel to the data line, it short-circuits it in the low-resistance state, and it is transparent in the high-resistance state.
  • only one element can be provided for actuating the pass transistor, provided the resistance ratio, that is to say the ratio between the low switchable resistance and the high switchable resistance, is sufficiently high so that a sufficiently high voltage ratio at the gate input for control purposes of the transistor can be placed.
  • the resistance ratio that is to say the ratio between the low switchable resistance and the high switchable resistance
  • the two elements in particular the two TMR cells, have a resistance ratio between the two state-related resistances not equal to 1: 1, in particular 1: 2 or higher.
  • the higher the resistance ratio the further the control voltages dependent on the respective resistances are separated from one another.
  • an element is immediate is connected to the data line and opens or blocks it directly. According to this embodiment of the invention, such an element is used directly as a pass transistor.
  • the data line would be enabled if the low resistance was set, and it would be blocked if the high resistance was set.
  • the component according to the invention offers a number of advantages compared to technologies or architectures previously used.
  • the common technologies use configuration storage with an SRAM memory or an EEPROM memory.
  • SRAM cells can only control one pass transistor.
  • the reason for this lies in the principle of operation of this cell, which is based on the flip-flop principle.
  • transistors are mutually coupled so that the circuit knows two stable states and these states are visible to the outside as a voltage.
  • the use of an element according to the invention reduces the number of transistors per pass element.
  • When using two elements for switching a pass transistor only three surface units are necessary (the two elements and the pass transistor itself) or become only one surface unit needed if an item itself is used as a pass transistor.
  • the area size of a TMR cell is ⁇ the area size of a transistor.
  • Another advantage is the fact that the configuration is retained if the supply voltage fails, which makes an additional boot memory unnecessary. This means that in comparison to the SRAM, no energy supply is required for permanent storage. Nevertheless, very fast switchover times ( ⁇ 3ns) can be realized because the resistor can be switched very quickly.
  • An EEPROM (including flash) also consists of several transistors that are complex and slow to be reprogrammed and have poor runtimes compared to a simple pass transistor.
  • the EEPROM transistors are larger than normal transistors because an additional conductor path is required for the tunnel route.
  • the use of the elements, especially the TMR cell offers the advantage of quick and uncomplicated reprogramming. This advantage is central, since dynamically reconfigurable components will be used in the future. This is not conceivable or possible with EEPROM cells, since EEPROM cells only show a slow switching speed of the floating gate in the ⁇ s range, but probably with the cells whose resistance can be changed, in particular in the form of the TMR cells.
  • 1 is a schematic diagram of a layer system of a TMR cell
  • FIG. 2 is a schematic diagram of the series connection of two elements for controlling a pass transistor
  • FIG. 3 shows a more detailed illustration of the arrangement from FIG. 2, 4 shows a section through the arrangement from FIG. 3,
  • FIG. 5 shows a schematic diagram of an element which is arranged directly in the data line and serves as a pass transistor
  • Fig. 6 is a schematic diagram of a parallel connection of the pass transistor to the data line.
  • FIG. 1 shows in the form of a schematic diagram an element 1 in the form of a TMR cell 2, consisting of a soft magnetic information layer 3, an electronic barrier layer 4 and a hard magnetic reference layer 5.
  • the soft magnetic layer or a layer of layers with a soft magnetic effect that forms this information layer 3 can be remagnetized by means of currents or current pulses on conductor tracks, which currents or current pulses generate a magnetic field or a magnetic pulse that acts on the layer magnetization.
  • the base materials are known magnetic materials of low or medium coercive field strength.
  • the double arrow indicates the anisotropy axis in which the magnetization can be set. Two discrete magnetization states can thus be set.
  • the barrier layer 4 forms an electronic barrier, it arises from an abrupt change in the band structure.
  • the electronic barrier enables the direct tunneling of charge carriers between the adjacent electrodes.
  • the properties of the electronic barrier determine the "basic resistance" of the elements, and also the voltage dependence of the characteristic.
  • Another criterion is the maintenance of spin polarization during tunneling or a total spin flip (e.g. spin-up becomes spin-down).
  • the following insulator materials are frequently used as barrier materials for the TMR effect: A10 X , AlN, TaO x , BN, MgO; semiconducting materials: ZnS, GaO x ; other materials: NiO, NbO, Hf0 2 , Ti0 2 , Si0 2 , Fe 2 0 3 , Fe 3 0 4 .
  • the material thickness is a few atomic layers up to a few nanometers. Crystalline and amorphous barriers are used.
  • Layer actively interacts with the electrons. This is the layer that is adjacent to the non-magnetic intermediate layer. Since it is part of the magnetically hard layer, its magnetization is specified and it contains the reference magnetization for the TMR effect (or the
  • Typical magnetic materials are layers with high spin polarization (e.g. CoFe, Py, Fe) and at the same time high exchange interaction with the neighboring layer in the hard layer.
  • the hard layer can also have two reference layers, for example in the case of a hard layer in the middle of a symmetrical GMR structure.
  • FIG. 2 shows a section of a circuit arrangement 6 according to the invention of a component according to the invention, which can be any component, primarily a logic circuit arrangement.
  • a data line 7 is shown, into which a pass transistor 8 is connected in the exemplary embodiment shown, via which the data line 7, which, for. B. any two logic elements, e.g. B. an amplifier V and a gate G or individual logic cells can be linked together, opened or locked.
  • two TMR cells 2 are provided, the resistance of which can be set via a configuration current, which is conducted via a configuration current conductor track 9 and which generates a corresponding magnetic field.
  • the control voltage that drops due to the resistance via the two mutually coupled TMR cells 2 (which can also be called a twin cell) is connected to the gate input of the pass transistor 8 via the connection 10. Depending on the size of this control voltage, the pass transistor 8 is either blocked or switched through.
  • FIGS. 3 and 4 show the circuit arrangement 6 from FIG. 2 in detail. Shown are the two TMR cells 2, which are coupled to one another at their reference layer-side output via a coupling line 11. On the opposite side, each TMR cell 2 is coupled to one pole of a power supply 12, so that a total of a current can be conducted through the twin cell arrangement. Also shown is the configuration current conductor 9, which is reversely routed above the TMR cells 2. A configuration current can be passed through it, as shown by the curved arrow in FIG. 3. After the current direction is opposite due to the conductor routing above the two TMR cells 2, anti-parallel magnetic fields are generated, as shown by the two arrows in FIG.
  • the two cells are operated anti-parallel to one another.
  • the direction of the magnetic fields generated in each case can be set and, via this, the magnetization of the adjacent soft magnetic layer 3 of both TMR cells 2.
  • the respective resistance of a TMR cell can be switched very easily between a state-dependent low and high value.
  • a resistance ratio of 1: 2 this always results in three times the minimum resistance of an element as a load resistance for the supply voltage and a control voltage value of 2/3 of the Supply voltage or 1/3 of the supply voltage.
  • the control voltage generated at the twin cell arrangement is applied to the input 14 of the gate 15 of the pass transistor 8 via a corresponding connection 13.
  • the function of such a transistor is known, depending on the size of the control voltage applied to the gate 15, the transistor becomes conductive, that is, it is switched on or it is blocked. The transistor state can thus be switched in a simple manner by changing the resistance conditions on the twin cell arrangement.
  • the distance between the two TMR cells 2 is of the same order of magnitude as the gate length (a few 100 nm). Source and drain currents in the source region 16 and drain region 17 of the pass transistor 8 are negligible in comparison to the configuration currents, therefore the distance between the two TMR cells 2 and the gate 15 can be determined by the necessary insulation distances become.
  • the structure is therefore very compact. It seems sensible to implement large TMR resistors to minimize the cross current between the poles of the power supply 12, which is possible via a thick barrier layer and a small area.
  • a TMR cell 2 is connected directly to the data line 7.
  • the prerequisite is that the TMR cell 2 has a high resistance ratio of preferably about 1:10 and more. It can then be used directly as a pass transistor, which further reduces the number of transistors required for switching the data line 7.
  • the data line is opened when a low resistance is set on the TMR cell, to which a configuration current conductor 9 is likewise assigned in order to be able to switch the resistance of the soft magnetic layer. It is blocked when the high resistance is set by switching the magnetization of the soft magnetic layer accordingly.
  • the configurable circuit is wired through the TMR cell 2.
  • the configuration conductor track 9 is part of the wiring and can run above, below or in combination above and below the TMR cell 2.
  • the connections of the TMR cell can be led into the silicon or remain in the wiring layer.
  • FIG. 6 finally shows a circuit arrangement in which a transistor 18 which can be switched via two TMR cells (not shown in any more detail) is shown, these TMR cells and the transistor parallel to the data line 19 to be "switched" which a gate G has via a pull-up Resistor 20 are connected to the positive pole of a voltage supply, that is, a source. A pulldown resistor 21 is also provided. Depending on whether the TMR cells are switched to high or low resistance, the gate is at the source or not.
  • TMR cells with high resistance so they behave transparently, the transistor does not act as a sink and is also transparent. If the TMR cell has a low resistance, the transistor acts as a sink, the gate is not connected to the positive pole.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention concerne un composant pourvu d'un ensemble circuit logique à fonctionnalité configurable, comprenant plusieurs lignes de données (7). Selon ladite invention, au moins un élément (1) pouvant être commuté entre deux états à résistances discrètes différentes est associé à au moins une partie des lignes de données (7), élément (1) par l'intermédiaire duquel la ligne de données (7) est libérée ou bloquée en fonction de l'état commuté.
EP04722859A 2003-05-08 2004-03-24 Composant pourvu d'un ensemble circuit logique a fonctionnalite configurable Expired - Fee Related EP1620858B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10320701A DE10320701A1 (de) 2003-05-08 2003-05-08 Bauelement mit einer in ihrer Funktionalität konfigurierbaren Schaltungsanordnung, insbesondere Logikschaltungsanordnung
PCT/EP2004/003134 WO2004100170A1 (fr) 2003-05-08 2004-03-24 Composant pourvu d'un ensemble circuit logique a fonctionnalite configurable

Publications (2)

Publication Number Publication Date
EP1620858A1 true EP1620858A1 (fr) 2006-02-01
EP1620858B1 EP1620858B1 (fr) 2012-01-04

Family

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EP04722859A Expired - Fee Related EP1620858B1 (fr) 2003-05-08 2004-03-24 Composant pourvu d'un ensemble circuit logique a fonctionnalite configurable

Country Status (5)

Country Link
US (1) US7933144B2 (fr)
EP (1) EP1620858B1 (fr)
JP (1) JP4455584B2 (fr)
DE (1) DE10320701A1 (fr)
WO (1) WO2004100170A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005036066B3 (de) * 2005-08-01 2006-09-21 Siemens Ag Bauelement mit einer in ihrer Funktionalität konfigurierbaren Schaltungsanordnung
US7397277B2 (en) * 2005-10-17 2008-07-08 Northern Lights Semiconductor Corp. Magnetic transistor circuit with the EXOR function
US7539046B2 (en) 2007-01-31 2009-05-26 Northern Lights Semiconductor Corp. Integrated circuit with magnetic memory
US7847586B2 (en) * 2007-08-20 2010-12-07 Northern Lights Semiconductor Corp. Integrate circuit chip with magnetic devices
JP2009059884A (ja) * 2007-08-31 2009-03-19 Tokyo Institute Of Technology 電子回路
US8243502B2 (en) 2007-12-14 2012-08-14 Nec Corporation Nonvolatile latch circuit and logic circuit using the same
JP5573850B2 (ja) * 2010-01-15 2014-08-20 独立行政法人国立高等専門学校機構 論理回路および集積回路
JP5664105B2 (ja) 2010-10-12 2015-02-04 富士通株式会社 半導体メモリおよびシステム
US8373438B2 (en) 2010-10-29 2013-02-12 Alexander Mikhailovich Shukh Nonvolatile logic circuit
JP5651632B2 (ja) * 2012-03-26 2015-01-14 株式会社東芝 プログラマブルロジックスイッチ
JP5969109B2 (ja) * 2012-03-29 2016-08-10 インテル コーポレイション 磁気状態素子及び回路
US9704576B2 (en) * 2014-02-28 2017-07-11 Rambus Inc. Complementary RRAM applications for logic and ternary content addressable memory (TCAM)

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3700311A (en) * 1971-11-22 1972-10-24 American Optical Corp Eight component 100x microscope objective
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US5469299A (en) * 1990-05-15 1995-11-21 Olympus Optical Co., Ltd. Objective lens system
US5925904A (en) * 1996-04-03 1999-07-20 Altera Corporation Two-terminal electrically-reprogrammable programmable logic element
US6542000B1 (en) * 1999-07-30 2003-04-01 Iowa State University Research Foundation, Inc. Nonvolatile programmable logic devices
US6314014B1 (en) * 1999-12-16 2001-11-06 Ovonyx, Inc. Programmable resistance memory arrays with reference cells
DE10053206C1 (de) 2000-10-26 2002-01-17 Siemens Ag Logikschaltungsanordnung
JP2002299584A (ja) * 2001-04-03 2002-10-11 Mitsubishi Electric Corp 磁気ランダムアクセスメモリ装置および半導体装置
DE10144384C1 (de) * 2001-09-10 2003-01-02 Siemens Ag Logikbaustein
DE10144385C2 (de) * 2001-09-10 2003-07-24 Siemens Ag Standardzellenanordnung für ein magneto-resistives Bauelement und hierauf aufbauende elektronisch magneto-resistive Bauelemente
DE10144395C1 (de) * 2001-09-10 2002-10-10 Siemens Ag Baustein der programmierbaren magnetischen Logik
JP2003174149A (ja) * 2001-12-07 2003-06-20 Mitsubishi Electric Corp 磁気抵抗記憶素子および磁気ランダムアクセスメモリ装置
FR2834348B1 (fr) 2001-12-28 2004-02-27 Mauna Kea Technologies Tete optique de focalisation miniaturisee, notamment pour endoscope
DE60307425T2 (de) 2002-01-28 2006-12-14 Rohm Co., Ltd., Kyoto Schaltung für logische operationen und verfahren für logische operationen
JP2004133990A (ja) * 2002-10-09 2004-04-30 Renesas Technology Corp 薄膜磁性体記憶装置
KR100479810B1 (ko) 2002-12-30 2005-03-31 주식회사 하이닉스반도체 불휘발성 메모리 장치
US7684134B2 (en) 2003-01-21 2010-03-23 The General Hospital Corporation Microscope objectives
JP4383080B2 (ja) * 2003-04-15 2009-12-16 オリンパス株式会社 対物レンズ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004100170A1 *

Also Published As

Publication number Publication date
JP4455584B2 (ja) 2010-04-21
DE10320701A1 (de) 2004-12-23
WO2004100170A1 (fr) 2004-11-18
JP2006526907A (ja) 2006-11-24
US7933144B2 (en) 2011-04-26
EP1620858B1 (fr) 2012-01-04
US20070164781A1 (en) 2007-07-19

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