EP1577774A2 - Segmentation de données dans une mémoire à semi-conducteurs - Google Patents

Segmentation de données dans une mémoire à semi-conducteurs Download PDF

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Publication number
EP1577774A2
EP1577774A2 EP05003069A EP05003069A EP1577774A2 EP 1577774 A2 EP1577774 A2 EP 1577774A2 EP 05003069 A EP05003069 A EP 05003069A EP 05003069 A EP05003069 A EP 05003069A EP 1577774 A2 EP1577774 A2 EP 1577774A2
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EP
European Patent Office
Prior art keywords
data
physical storage
error correction
error
regions
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EP05003069A
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German (de)
English (en)
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EP1577774A3 (fr
Inventor
Takashi Tachikawa
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NEC Corp
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NEC Corp
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Publication of EP1577774A3 publication Critical patent/EP1577774A3/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G06F11/108—Parity data distribution in semiconductor storages, e.g. in SSD

Definitions

  • the present invention relates to a method of data writing to and data reading from a storage device. More specifically, the invention relates to the method of data writing to and data reading from a semiconductor memory device such as a flash memory.
  • the storage capacity of a data storage device typified by a semiconductor memory in an information device such as a computer, a PDA (Personal Data Assistance, Personal Digital Assistants: Personal Portable Type Information Communication Device), a household game device, a digital camera, or a cellular phone, or a PHS (Personal Hand-phone System) keeps on increasing year by year.
  • the flash memory in particular, which is a ROM (Read Only Memory) that can perform electrical erasure of and electrical writing to storage, is a nonvolatile memory from which the storage does not vanish even if external power is not supplied thereto, and is used a lot in various fields.
  • the flash memory also has a characteristic in which all data are collectively erased or erasure is performed block by block which is a unit of data erasure, and data writing or data reading is performed on a block-by-block basis (refer to JP-P2000-173289A (Patent Document 1) and JP-P2002-288034A (Patent Document 2)).
  • the mounted capacity of the flash memory has hitherto been smaller than that of other storage device due to constraints in view of its manufacture and price.
  • a large capacity type memory resulting from development of a NAND-type flash memory enabling manufacture of a comparatively cheap and large-capacity memory and an NOR-type flash memory of a multi-value logical type, and an increase in the demand of a large capacity nonvolatile memory due to the spread of digital cameras and higher functions of cellar phones, the storage capacity of the nonvolatile-type semiconductor memory has been remarkably increased.
  • the NAND-type memory is based on the premise that a certain defective region may be included therein at the time of shipment to a manufacturer. Further, the NAND-type memory is often based on the premise that defects may be generated with a certain probability or in a certain amount after shipped to the manufacturer. Further, the reliability of the NOR-type flash memory, which has hitherto had higher reliability than that of other storage device, in terms of data storage, is more reduced than before because of multivaluing or the like.
  • an object of the present invention is therefore to provide measures for enhancing reliability of stored data in a semiconductor storage device such as a flash memory and also enabling efficient use of storage regions through reuse of a region which has become defective as well.
  • a method of data writing to and data reading from a storage device comprising storage means constituted from a plurality of physical storage regions each including a plurality of data storage areas, an operation of the data writing or the data reading being collectively performed for each of the plurality of physical storage regions.
  • an error correcting physical storage region with error correction data written therein the error correction data being provided for correcting errors of the data respectively written into corresponding positions of the plurality of physical storage regions.
  • one of the plurality of physical storage regions is registered as an alternative candidate storage region for being usable again as the alternative physical storage region, and when the erasure of all the data in one of the plurality of physical storage regions in which the data error has been detected has failed, one of the plurality of physical storage regions is registered as a defective physical storage region and managed not to be used from then on.
  • a data storage system According to a fourth aspect of the present invention, there is provided a data storage system.
  • the data storage system comprises:
  • an error correcting physical storage region with error correction data written therein is provided for the storage means, the error correction data being provided for correcting errors of the data respectively written into corresponding positions of the plurality of physical storage region, and
  • control means has a function of performing control so that when one of the errors is detected in one of the data stored in the storage means, all of the data in one of the plurality of physical storage regions with one of the errors detected therein are checked, the data determined to be normal as a result of the check is saved and written into a corresponding position in an alternative physical storage region and the data determined to have the error is corrected using the error correction data in the error correcting physical storage region and is written into a corresponding position in the alternative physical storage region, and all the data in one of the plurality of physical storage regions in which the data error has been detected are erased.
  • each data has a configuration in which the data and error correction information thereof are arranged across physical units of storage regions in which a defect may occur.
  • a sequence of data to be stored in one physical storage region is split across a plurality of physical storage regions, for storage, and error correction data thereof is also stored in another physical storage region.
  • the device can be used with a certain degree of reliability.
  • the data storage method is different from a conventional data storage method: a sequence of data that should be originally stored in one physical storage region is split across (or over) a plurality of physical storage regions for storage.
  • a configuration can be made in which data cannot be read out normally even if only the storage device for which writing has been performed is connected to other system. Therefore, the present invention can also be utilized for security applications.
  • Fig. 1 is a block diagram of a data storage system showing a first embodiment of the present invention.
  • the data storage system in this embodiment has storage means (unit) 104 including n physically divided storage regions constituted from a physical storage region 111, a physical storage region 112, and a physical storage region 11n.
  • Each physical storage region is the storage region having a group of functions that simultaneously operate during either or all of operations such as data writing, data reading, and data erasure, and shows a group of areas in which various defects may occur. These defects include a defect at the time of manufacture, a malfunction generated in a specific area such as damage caused by electrical migration or static electricity, a defective control circuit, and a malfunction caused by the influence of stability of a supply voltage.
  • Fig. 2 shows a configuration of data storage in a flash memory.
  • a minimum unit of data for data reading such as the unit of a byte or a word, is grouped from data 1 to data X, and the group of these consecutive X units of data is stored as one page. Then, generally, the flash memory supporting high-speed reading often includes the function of reading in the unit of this page.
  • a group of these Y pages is defined as one block. Being different from an EEPROM (Electronically Erasable and Programmable Read Only Memory), the flash memory can only perform erasing in the unit of this block. In addition to this, generally, the NAND-type flash memory can only perform reading and writing by this block by block.
  • a group of Z blocks constitutes one flash memory.
  • the block defined herein is regarded as the unit of the physical storage region, and a description is directed to a storage device including Z physical storage regions, as a specific example.
  • the data storage system in this embodiment is characterized by including data rearrangement means (unit) 103.
  • This data rearrangement means 103 performs rearrangement of a sequence of data sequentially input to a plurality of (n) physical storage regions (blocks) in storage means 104 for storage, and splits the data that should be originally stored in one physical storage region as one group of continuous data across the plurality (n) physical storage regions, for storage.
  • the flash memory has only the function of reading and writing data within one physical storage region as continuous data, such as reading page by page. Then, if reading and writing that are the same as before are performed on the storage device stored according to this embodiment, a supervisory host 101 such as a common CPU (Central Arithmetic Processing Unit), cannot handle the data without alteration, because arrangement of the data is different. For this reason, a data string readout from the plurality (n) physical storage regions, respectively, is rearranged by the data rearrangement means 103 again and then converted to a data string that can be handled by the common CPU or the like. The data can be thereby handled by the supervisory host 101 without alteration.
  • a supervisory host 101 such as a common CPU (Central Arithmetic Processing Unit)
  • a data string readout from the plurality (n) physical storage regions, respectively is rearranged by the data rearrangement means 103 again and then converted to a data string that can be handled by the common CPU or the like. The data can be thereby handled by the supervisory host
  • Control means (unit) 102 is the means for controlling the storage means 104 and the data rearrangement means 103, and performs control over reading of data from the storage means (unit) 104 and control over writing of data to the storage means 104 in response to data reading and writing requests from the supervisory host 101, respectively. Further, switching between data reading and data writing and transmission and reception of various control signals such as a chip select signal and an address specification signal are also performed by this control means 102.
  • a data signal for performing transmission and reception of readout data and written data is assumed to be connected to the data rearrangement means 103, while an address signal indicating an address for execution of data reading and writing is assumed to be connected to the storage means 104.
  • the data signal (data bus) is connected between the data rearrangement means 103 and the storage means 104, and data to be written into the storage means 104 or data to be read out from the storage means 104 are invariably rearranged by the data rearrangement means 103 and then output to the storage means 104 or the supervisory host 101.
  • the supervisory host 101 is the means for requesting data reading and data writing to the control means 102, and is a data processing device such as the CPU or a memory controller.
  • Figs. 3 and 4 are diagrams for explaining a conventional data storage method and a data storage method in this embodiment, respectively.
  • Figs. 5 and 6 are configuration diagrams showing examples of the data rearrangement means for implementing the data storage method in this embodiment. An operation of this embodiment will be described below with reference to Figs. 1 to 6.
  • the storage means 104 includes the n physical storage regions such as a first physical storage region (301), a second physical storage region (302), and ... an nth physical storage region (30n).
  • the physical storage region herein corresponds to the block, which is the minimum unit of erasure in the flash memory having a structure as shown in Fig. 2, for example.
  • one physical storage region (block) has m data storage areas.
  • the storage means 104 has m x n data storage areas, in this example.
  • data is stored in the physical storage region contiguous thereto: data constituted from (data 1) to (data m) are stored in the first physical storage region (301), (data m+1) to (data 2m) are stored in the second physical storage region (302) contiguous thereto, (data 2m +1) to (data 3m) are stored in a third physical storage region (303), and (data (n-1)m + 1) to (data nm) are included in the nth physical storage region (30n), as shown in Fig. 3.
  • the data are sequentially stored across the areas of different physical storage regions as follows:
  • the data storage method in this embodiment data is stored in the storage means 104 in an order different from that for the prior art.
  • the data without alteration is difficult to use as they be (without specific modification or rearrangement).
  • the data collectively read out from the respective physical storage regions of the storage means 104 are rearranged by the data rearrangement means 103, for output to the supervisory host 101 or write data sent from the supervisory host 101 are rearranged and then written into the storage means 104.
  • the areas for storing (m x n) units of data or the n physical storage regions) function as the size for collective data writing or collective data reading.
  • Figs. 5a and 5b show an image of data rearrangement at the time of data reading and an image of data rearrangement at the time of data writing, respectively, in this embodiment.
  • Reference numerals 501 and 502 in Fig. 5a and reference numerals 504 and 505 in Fig. 5b correspond to the data rearrangement means 103 in Fig. 1
  • reference numeral 503 in Fig. 5 corresponds to the storage means 104 in Fig. 1.
  • it is assumed in Fig. 5 that there are four physical storage regions each having four data storage areas, and the four physical storage regions have 4 x 4 16 data storage areas.
  • the data stored in the four physical storage regions in the storage means 503 are temporarily stored in four routes provided in the data rearrangement means 502, respectively, at the time of data reading. Then, during transition from the means 502 to the means 501, rearrangement in the order of the data 1, the data 2, the data 3, and data 4 is performed, for output, first. Then, fifth data to eighth data, ninth data to twelfth data, and thirteenth data to sixteenth data are sequentially read out.
  • write data is stored in the storage means 503 through the data rearrangement means 505 and 504.
  • a data string (1, 2, 3, 4) is input to the means 505, for example, data rearrangement is so performed that these four units of data pass through different routes within the means 504, respectively, and then, four units of data in (5, 6, 7, 8), (9, 10, 11, 12), and (13, 14, 15, 16) pass through the different routes within the means 504, respectively.
  • each data string in each route is collectively stored in each of the physical storage regions of the storage means 503.
  • Fig. 6 shows an example in which the data rearrangement means at the time of the data reading in Fig. 5a has been implemented by a shift register.
  • Fig. 6a shows a common circuit of a four-bit shift register constituted from four D-type flip-flops. Assume that this is illustrated by a diagram as shown in Fig. 6b. Then, the circuit for data rearrangement shown in Fig. 5a can be implemented by a circuit in which respective outputs from the four four-bit shift registers are connected to respective preset terminals of another one four-bit shift register.
  • the storage means 104 data are stored, as shown in the means 503 in Fig. 5a, for example, and the storage means 104 has the function of performing collective reading in the unit of the physical storage region.
  • data are collectively read out in the order of (1, 5, 9, 13) as the data before rearrangement.
  • switches S1 to S4 only the switch S 1 is switched ON, and data are sequentially stored in FF11 to FF14.
  • a data string (2, 6, 10, 14) with only the switch S2 switched ON is read out.
  • a data string (3, 7, 11, 15) is sequentially read out with only the switch S3 switched ON
  • a data string (4, 8, 12, 16) is sequentially read out with only the switch S4 switched ON.
  • a rearrangement circuit for data writing can also be readily implemented by a circuit configuration using a shift register in the same manner as in Fig. 6 according to the image in Fig. 5b.
  • a sequence of data is split across a plurality of physical storage regions for storage without being stored in one physical storage region in the storage device constituted from the plurality of physical storage regions and in which data writing operations or data reading operations are collectively executed in the unit of one physical storage region.
  • Fig. 7 is a diagram showing a second embodiment of the present invention, and a method of storing data and error correction data in this embodiment.
  • Fig. 8 shows an alternative image of a physical storage region when an error occurs, in this embodiment.
  • error detection and error correction are performed by adding redundant data such as a parity to each arbitrary data unit for data error correction. Part or all of data to be paired with this error correction data is stored in one physical storage region.
  • redundant data such as a parity
  • Part or all of data to be paired with this error correction data is stored in one physical storage region.
  • a sequence of data is split across and spread over a plurality of physical storage regions for storage without being stored in the unit of one physical storage region, a physical storage region for storing error correction data is added, and the error correction data for the data stored in the plurality of physical regions are collectively stored in this physical storage region.
  • Fig. 7 shows storage means having (n + 1) physical storage regions each having m data storage areas, and this storage means includes a total of (m) x (n + 1) data storage areas.
  • this storage means includes a total of (m) x (n + 1) data storage areas.
  • error correction data for the group of data is stored in another (n + 1)th physical storage region as data p1.
  • error correction data p2 for the data n + 1 to the data 2n, ..., and error correction data pm for the data (m-1)n + 1 to the data mn are stored.
  • the data 1 is constituted from a bit 1-1, a bit 1-2, a bit 1-3, and a bit 1-4
  • the data 2 is constituted from a bit 2-1, ...
  • the nth data is constituted from a bit n-1, a bit n-2, a bit n-3, and a bit n-4
  • a parity 1 is determined for a data string grouping the bit 1-1, bit 2-1, ..., and bit n-1.
  • a parity 2, a parity 3, and a parity 4 are determined, thereby enabling error correction.
  • Fig. 10 is a flowchart showing a procedure for error correction in this embodiment, and Fig. 11 includes image diagrams about this data restoration operation.
  • the data restoration operation in this embodiment will be described with reference to Figs. 7 to 11.
  • the block that has caused the error is registered in an alternative candidate block (at 1009).
  • This alternative candidate block is the candidate for a block to be used in place of a defective block when the defective block has occurred, and is usually managed by a memory management system implemented by software.
  • the block in question is registered (at 1010) as the defective block and is managed so as not to be used from then on.
  • an alternative block is assigned (at 1011).
  • data is restored to the alternative block.
  • it is checked (at 1012) whether there is the data saved at step (1006) is or not.
  • all the data stored in the defective block are simply restored (at 1013), based on the data and the error correction data (parities) of the remainder of the blocks (as shown in Fig. 11b).
  • the saved data is written into the alternative block (at 1014), and only error data that is not saved is restored by error correction (as shown in Fig. 11a).
  • this embodiment has the operation of identifying the defective block, such as reading other data in the same block that has caused an error.
  • a parity detection bit of one bit by which only error detection can be normally performed as shown in Fig. 9 error detection becomes possible.
  • data can be quickly restored when a defect has occurred in a group of the physical storage areas in which various defects may occur.
  • various defects include a defect at the time of manufacture, a malfunction generated in a specific area such as damage caused by electrical migration or static electricity, a defective control circuit, and a malfunction due to the influence of stability of the supply voltage.
  • the supervisory host can cause data reading and writing to be stably performed without being aware of it.
  • the defect is the one in which even the defective block can be reused by erasure or the like, the defective block can be utilized as the alternative candidate block.
  • the defective block was described to be made to be the alternative candidate block if it is reusable by erasure or the like. Reliability, however, can also be enhanced by performing control so that when a defect has occurred in the same block arbitrary set times or more, the defective block will not be used from then on.
  • Fig. 12 is a block diagram of a data storage system showing other embodiment of the present invention.
  • this embodiment is characterized by adding hardware error correction means (unit) 105.
  • the error correction means 105 is the means for performing error correction on data input to the data rearrangement means 103. Further, the error correction means 102 receives directions about control over whether to perform error correction or not and control over an error correction method, from the control means 102.
  • the error correction means 105 also has the function of error detection.
  • Fig. 13 shows an example of a method of storing data and error correction data in this embodiment
  • Fig. 14 shows an error correcting operation in this embodiment. An operation of this embodiment will be described with reference to Figs. 12 to 14.
  • error correction data for a data string constituted from the data 1, data 2, data 3, ..., and nth data, extending across the physical storage regions is stored as p1, for storage, as in Fig. 7.
  • error correction data for a data string constituted from the data 1, data n + 1, data 2n + 1, ..., and data (m-1)n + 1, which are the data in the first physical storage region is stored as q1.
  • p2 to pm, and q2 to q(n + 1) are stored.
  • reference numeral 1403 denotes storage means
  • reference numerals 1401 and 1402 denote data rearrangement means (unit).
  • error detection is performed by the error correction means 105.
  • error correction is performed.
  • the parity or the like is used, error detection and correction are performed using the error correction data p2 and q2, as shown in Fig. 14.
  • the hardware error correction means is provided in this embodiment.
  • the effect of the fast error correction processing speed can be obtained.
  • the data rearrangement means is not limited to this example, and by using an SRAM (Static RAM), the flash memory, an EEPROM (Electronically Erasable and Programmable ROM), or the like, rearrangement using software can also be performed.
  • SRAM Static RAM
  • EEPROM Electrically Erasable and Programmable ROM
  • rearrangement using software can also be performed.
  • the error correction data in biaxial directions (e.g. orthogonal ordinates), as shown in Fig. 13, the effect is obtained in which, even if a defect for each of the physical storage regions is present in the memory as the rearrangement means, similar restoration becomes possible.
  • error correction data for one data storage area was used.
  • the error correction data for a plurality of data storage areas can also be provided for one data string, according to the method of error correction.
  • the physical storage region from a narrow point of view is the block, and the physical storage region from a larger broader of view is one flash memory itself.
  • the present invention can be applied through division into two hierarchy layers. Further, since it takes time to perform data rearrangement and error correction in this embodiment, this embodiment produces the greatest effect when used to be applied to only one portion of a file management area, important user data, or the like that will be much damaged due to data destruction.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
EP05003069A 2004-02-19 2005-02-14 Segmentation de données dans une mémoire à semi-conducteurs Withdrawn EP1577774A3 (fr)

Applications Claiming Priority (2)

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JP2004043101 2004-02-19
JP2004043101A JP4595342B2 (ja) 2004-02-19 2004-02-19 記憶装置のデータ書き込み、読み出し方法およびデータ記憶システム

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EP1577774A2 true EP1577774A2 (fr) 2005-09-21
EP1577774A3 EP1577774A3 (fr) 2010-06-09

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US10614019B2 (en) 2017-04-28 2020-04-07 EMC IP Holding Company LLC Method and system for fast ordered writes with target collaboration
US10936497B2 (en) 2017-04-28 2021-03-02 EMC IP Holding Company LLC Method and system for writing data to and read data from persistent storage

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CN1658163A (zh) 2005-08-24
CN100357899C (zh) 2007-12-26

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