EP1573804A1 - Verfahren zur bildung einer struktur und eines abstandselements und diesbezüglicher finfet - Google Patents
Verfahren zur bildung einer struktur und eines abstandselements und diesbezüglicher finfetInfo
- Publication number
- EP1573804A1 EP1573804A1 EP02798557A EP02798557A EP1573804A1 EP 1573804 A1 EP1573804 A1 EP 1573804A1 EP 02798557 A EP02798557 A EP 02798557A EP 02798557 A EP02798557 A EP 02798557A EP 1573804 A1 EP1573804 A1 EP 1573804A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- spacer
- gate
- fin
- forming
- overhang
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000000463 material Substances 0.000 claims description 93
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052792 caesium Inorganic materials 0.000 claims description 2
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 230000003628 erosive effect Effects 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 abstract description 4
- 238000010276 construction Methods 0.000 abstract description 2
- 238000004513 sizing Methods 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005755 formation reaction Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Definitions
- the present invention relates generally to CMOS processing.
- CMOS complementary metal-oxide-semiconductor
- FinFETs Fin Field Effect Transistors
- MesaFETs structurally includes, among other things, a gate that extends over and along a portion of each sidewall of a thin, vertical, silicon "fin.”
- a spacer is required for blocking implants at the gate edge and preventing suicide shorts to the gate.
- Conventional planar CMOS spacer processing presents a number of problems relative to the fin. In particular, conventional processing to form the spacer for the gate results in application to the fin. If conventional spacer processes are used, fin erosion during spacer etch is a potential problem.
- any additional etching can prevent attainment of the desired fin size.
- Another challenge is formation of a spacer along the gate without formation on the fin sidewalls and the top of the fin such that the part the part of the fin not adjacent to the gate can be exposed to implantation.
- a spacer formed on the gate also forms on the sidewalls of the fin due to the three-dimensional nature of the FinFET. In some cases, such as during sidewall implantation or source drain extension, this sidewall spacer is undesirable. Attempts to remove the fin sidewall spacer result in removing the spacer on the gate where a spacer is needed. Similar problems exist relative to other CMOS devices such as MesaFETs.
- the invention relates to methods for forming a spacer for a first structure, such as a gate structure of a FinFET, and at most a portion of a second structure, such as a region of the fin adjacent to the gate, without detrimentally altering (e.g., eroding or forming a spacer thereon) the second structure.
- the methods generate a first structure (gate structure) having a top portion that overhangs a lower portion and a spacer under the overhang.
- the overhang may be removed after spacer processing.
- the overhang protects the first structure and may protect parts of the second structure if the first structure overlaps the second structure.
- FIG. 1 An example of this is a fin region adjacent and under the gate structure in a FinFET protected by a spacer, where the sidewalls of the fin are exposed to other processing such as selective silicon growth and implantation.
- the methods allow sizing of the second structure and construction of the first structure and spacer without detrimentally altering the second structure during spacer processing.
- the invention also relates to a FinFET including a gate structure and spacer formed by the methods.
- Figure 1 shows a perspective view of a precursor structure of a FinFET including a fin without a gate material.
- Figures 2-A-B show cross-sectional views of a first and second step of the methods.
- Figures 3A-B show cross-sectional views of a third step of the methods.
- Figures 4A-B show cross-sectional views of a fourth step according to a first embodiment of the methods.
- Figures 5A-B show cross-sectional views of a fourth step according to a second embodiment of the methods.
- Figures 6A-B show cross-sectional views of a fifth step of the methods.
- Figures 7A-B show cross-sectional views of a sixth step of the methods and the resulting gate structure and associated spacer.
- first structure such as a gate structure and an associated spacer without detrimentally altering a second structure
- the gate structure is the "first structure”
- the fin is the "second structure.”
- a spacer is formed' for the gate and on a portion of the fin adjacent the gate because the fin goes through the gate.
- the methods described can be used for any device in which it is desired to form a spacer for a first stiiicture and form a spacer for at most a portion
- the methods would enable formation of a spacer on one structure without forming a spacer on the other structure at all.
- the two structures may both be gates and a spacer may be desired on one of the gates but not at all on the other gate. Accordingly, the first and second structure terms may be applicable to a variety of different CMOS formations.
- FIG. 1 is a perspective view of a precursor structure 10 of a FinFET after gate etch.
- structure 10 includes a substrate 12 upon which is formed a fin 14 of mono-crystalline silicon.
- the gate structure (not shown) will eventually be constructed over fin 14.
- a hardmask 16 is also provided to protect fin 14 during processing.
- Hardmask 16 may be, for example, silicon dioxide (oxide) or silicon nitride.
- Actual processing to establish this precursor structure 10 may include deposition of a hardmask 16, etching hardmask 16 and the underlying silicon to generate fin 14, conducting a sacrificial oxidation and gate oxidation of the silicon to generate structure oxide 18.
- FIGS. 2-7 illustrate methods for forming a spacer for a gate and a spacer for at most a portion of a fin during the spacer processing.
- those figures labeled 'A' show a cross-sectional view A-A across fin 14 as shown in FIG. 1, and those labeled 'B' show a cross-sectional view B-B as shown in FIG. 1 (through the gate structure once formed).
- FIGS. 2A-B In a first step, shown in FIGS. 2A-B, a first material 20 for generation of a gate structure is deposited over fin 14.
- FIGS. 2A-B also show a second step in which a second material 22, 122 is formed over first material 20.
- second material 22, 122 includes the dual designation because the material may be provided in two different forms, as will be described in more detail below.
- second material 22, 122 is different than first material 20.
- FIGS. 3A-3B show the next step in which a gate structure 24 is formed in first material 20 and second material 22, 122.
- Forming may include applying and patterning (e.g., with lithography) a hardmask 26, e.g., oxide (TEOS), over first material and second material 22, 122, and etching the materials to form gate structure 24. As shown in FIG. 3B, these steps are also applied to eventual source and drain regions 28 of fin 14. Subsequently, hardmask 26 is removed in a known fashion.
- a hardmask 26 e.g., oxide
- FIGS. 4A-B and 5A-B illustrate two embodiments of the next step in which second material 22, 122 is made to overhang first material 20. As noted above, second material 22, 122 is different than first material 20.
- FIGS. 4A-B show a first embodiment in which second material 22 is formed
- second material 22 may be a portion of first material 20 that is implanted with a dopant in a known fashion.
- the dopant may be any material that causes polysilicon second material 22 to oxidize at a faster rate than non-doped polysilicon.
- the dopant may be, for example, Arsenic (As) (preferred), Germanium (Ge), Cesium (Cs), Argon (Ar) or Flourine (F) or a combination thereof.
- second material 22 that has a faster oxidation rate than first material 20 may be deposited on the first material, e.g., as polycrystalline silicon-germanium alloy.
- First material 20 may be, for example, non-doped polysilicon.
- second material 22 is made to overhang first material 20 by conducting an oxidation, e.g., at 800 to 950°C. The differential oxidation rate between materials generates a thicker oxide from second material 22 of gate structure 24 relative to fin 14 and first material 20. The result is generation of an overhang 40 of fin 14 adjacent to first material 20.
- FIGS. 4A-B show the resulting structure in which second material 22 forms a top portion 30 of gate structure 24 that overhangs an electrically conductive lower portion 32 thereof.
- the oxidation process may also cause thin oxide layers 34 (e.g., approximately ten times thinner than second material 22) to form on the sides of first material 20 (i.e., lower portion 32) and the sides of fin 14 outside of gate structure 24.
- Oxide layer 34 allows for preservation of fin 14 width without oxidizing the fin away.
- FIGS. 5A-B show a second, alternative embodiment for making second material 122 overhang first material 20.
- second material 122 is provided (in the step shown in FIGS. 2A-B) as any material having different thermal reflow properties than first material 20.
- first material 20 is provided as polysilicon or a metal such as cobalt-silicide or tungsten
- second material 122 is provided as a glass such as boro-phospho-silicate glass (BPSG) or phospho-silicate glass (PSG).
- the step of making second material 122 overhang first material 20 then includes conducting a thermal process to cause material 122 to reflow and form an overhang 140.
- the thermal process may include, for example, heating at least the second material at approximately 850°C for approximately ten minutes in a non-oxidizing ambient.
- FIGS. 5A-B show the resulting structure in which second material 122 forms a top portion 130 of a gate structure 124 that overhangs an electrically conductive lower portion 132 thereof.
- second materials 22, 122 may vary depending on the embodiment used and the specific processing provided. Accordingly, while the figures illustrate a bulbous or umbrella-like shape for materials 20, 22, 122, other shapes that provide the overhang may be possible.
- the next step includes forming a spacer under overhang 40, 140.
- the spacer may be formed on the structure of either embodiment above. However, FIGS. 6A-B and 7A- B show only the embodiment of FIGS. 4A-B for brevity sake.
- a spacer material 42 is conformally deposited, as shown in FIGS. 6A-B. Spacer material may be, for example, silicon nitride, silicon oxide or a combination thereof.
- spacer material 42 is etched using a directional reactive ion etching process which removes material everywhere except under overhang 40, 140 to form a spacer 44.
- Finishing processing may follow. This processing may include, for example, removal of oxide 34 from the sides of fin 14 (oxide remains as top portion 30 if doped polysilicon used) or removal of top portion 130, i.e., the glass, from gate structure 124 (if used).
- final processing may include, for example, implanting to set threshold voltage (Nt), doping the source/drain regions 28 of fin 14, selective silicon growth to widen the source/drain regions 28 on fin 14, removing remaining oxide and forming cobalt-silicide (CoSi), conventional contact processing, finishing with appropriate metal levels, etc.
- Nt threshold voltage
- CoSi cobalt-silicide
- the resulting FinFET 100 includes, among other things, a gate structure 24, 124 including an electrically conductive lower portion 32, 132 and an overhanging top portion 30, 130, a fin 14 extending through the lower portion, and a spacer 44 positioned under top portion 30, 130 of gate structure 24, 124 adjacent to conducting lower portion 32, 132.
- Top portion 30, 130 is made of a material (e.g., oxide or glass) that is different than the material (e.g., polysilicon) of lower portion 32, 132 as described above.
- "gate structure" 24, 124 has been described as including a top portion 30, 130 and a lower portion 32, 132.
- top portion 30, 130 may not ultimately form an operative or active part of the actual gate used. For instance, at least a part of top portion 30, 130 and/or overhang 40, 140 may be removed to allow for contacts to be made to lower portion 32, 132 of gate structure 24, 124.
- the invention is useful for forming a spacer for a gate of a FinFET, and at most a portion of a fin without detrimentally altering the fin.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2002/040869 WO2004059727A1 (en) | 2002-12-19 | 2002-12-19 | Methods of forming structure and spacer and related finfet |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1573804A1 true EP1573804A1 (de) | 2005-09-14 |
EP1573804A4 EP1573804A4 (de) | 2006-03-08 |
Family
ID=32679934
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02798557A Withdrawn EP1573804A4 (de) | 2002-12-19 | 2002-12-19 | Verfahren zur bildung einer struktur und eines abstandselements und diesbezüglicher finfet |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1573804A4 (de) |
JP (1) | JP4410685B2 (de) |
CN (1) | CN1320641C (de) |
AU (1) | AU2002364088A1 (de) |
WO (1) | WO2004059727A1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6951783B2 (en) * | 2003-10-28 | 2005-10-04 | Freescale Semiconductor, Inc. | Confined spacers for double gate transistor semiconductor fabrication process |
US7473593B2 (en) | 2006-01-11 | 2009-01-06 | International Business Machines Corporation | Semiconductor transistors with expanded top portions of gates |
US7341902B2 (en) * | 2006-04-21 | 2008-03-11 | International Business Machines Corporation | Finfet/trigate stress-memorization method |
KR100838378B1 (ko) * | 2006-09-29 | 2008-06-13 | 주식회사 하이닉스반도체 | 핀트랜지스터의 제조 방법 |
KR100801315B1 (ko) | 2006-09-29 | 2008-02-05 | 주식회사 하이닉스반도체 | 돌기형트랜지스터가 구비된 반도체소자의 제조 방법 |
US8889495B2 (en) * | 2012-10-04 | 2014-11-18 | International Business Machines Corporation | Semiconductor alloy fin field effect transistor |
KR102030329B1 (ko) * | 2013-05-30 | 2019-11-08 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US9773869B2 (en) * | 2014-03-12 | 2017-09-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
MY188715A (en) | 2014-09-26 | 2021-12-25 | Intel Corp | Selective gate spacers for semiconductor devices |
US9564370B1 (en) | 2015-10-20 | 2017-02-07 | International Business Machines Corporation | Effective device formation for advanced technology nodes with aggressive fin-pitch scaling |
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US5567639A (en) * | 1996-01-04 | 1996-10-22 | Utron Technology Inc. | Method of forming a stack capacitor of fin structure for DRAM cell |
US5899746A (en) * | 1995-09-08 | 1999-05-04 | Sony Corporation | Method of forming pattern |
US5994192A (en) * | 1998-05-29 | 1999-11-30 | Vanguard International Semiconductor Corporation | Compensation of the channel region critical dimension, after polycide gate, lightly doped source and drain oxidation procedure |
US6051485A (en) * | 1997-04-24 | 2000-04-18 | Siemens Aktiengesellschaft | Method of producing a platinum-metal pattern or structure by a lift-off process |
WO2001069686A1 (de) * | 2000-03-13 | 2001-09-20 | Infineon Technologies Ag | Steg-feldeffekttransistor und verfahren zum herstellen eines steg-feldeffekttransistors |
US20020135041A1 (en) * | 1997-12-24 | 2002-09-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit and semiconductor device |
US6492212B1 (en) * | 2001-10-05 | 2002-12-10 | International Business Machines Corporation | Variable threshold voltage double gated transistors and method of fabrication |
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---|---|---|---|---|
US6562665B1 (en) * | 2000-10-16 | 2003-05-13 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology |
US6475890B1 (en) * | 2001-02-12 | 2002-11-05 | Advanced Micro Devices, Inc. | Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology |
US6475869B1 (en) * | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
-
2002
- 2002-12-19 WO PCT/US2002/040869 patent/WO2004059727A1/en active Search and Examination
- 2002-12-19 CN CNB028300432A patent/CN1320641C/zh not_active Expired - Fee Related
- 2002-12-19 AU AU2002364088A patent/AU2002364088A1/en not_active Abandoned
- 2002-12-19 EP EP02798557A patent/EP1573804A4/de not_active Withdrawn
- 2002-12-19 JP JP2004563141A patent/JP4410685B2/ja not_active Expired - Fee Related
Patent Citations (7)
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US5899746A (en) * | 1995-09-08 | 1999-05-04 | Sony Corporation | Method of forming pattern |
US5567639A (en) * | 1996-01-04 | 1996-10-22 | Utron Technology Inc. | Method of forming a stack capacitor of fin structure for DRAM cell |
US6051485A (en) * | 1997-04-24 | 2000-04-18 | Siemens Aktiengesellschaft | Method of producing a platinum-metal pattern or structure by a lift-off process |
US20020135041A1 (en) * | 1997-12-24 | 2002-09-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit and semiconductor device |
US5994192A (en) * | 1998-05-29 | 1999-11-30 | Vanguard International Semiconductor Corporation | Compensation of the channel region critical dimension, after polycide gate, lightly doped source and drain oxidation procedure |
WO2001069686A1 (de) * | 2000-03-13 | 2001-09-20 | Infineon Technologies Ag | Steg-feldeffekttransistor und verfahren zum herstellen eines steg-feldeffekttransistors |
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JP2006511092A (ja) | 2006-03-30 |
WO2004059727A1 (en) | 2004-07-15 |
CN1714441A (zh) | 2005-12-28 |
JP4410685B2 (ja) | 2010-02-03 |
CN1320641C (zh) | 2007-06-06 |
AU2002364088A1 (en) | 2004-07-22 |
EP1573804A4 (de) | 2006-03-08 |
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