Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/26—Power supply means, e.g. regulation thereof
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/10—Distribution of clock signals, e.g. skew

Definitions

• the invention relates to an integrated circuit comprising at least one digital part comprising a large number of elementary transistors, connected together so as to form a plurality of elementary functional elements, the elementary functional elements being grouped in sub-assemblies, each comprising first and second electrical supply terminals and a clock input, the sub-assemblies being connected in series, via their supply terminals, to the terminals of a supply voltage source.
• Digital integrated circuits such as microprocessors, microcontrollers, memories, etc. are made up of an ever-increasing number of elementary transistors, of increasingly smaller size. It is well known that according to Moore's law, the number of transistors on a silicon surface doubles every 18 months. Thus, every 18 months, on the same silicon substrate, the number of integrated circuits doubles and the size of each of them decreases. This reduction in size allows increased operating frequencies.
• the decrease in size of the transistors means that the maximum supply voltage that can be supported by the transistors decreases.
• the increase in the number of transistors imposes higher supply currents. This current also increases when the clock frequency is higher.
• the current supply voltages are of the order of a volt.
• the generations following integrated circuits will be supplied with voltages lower than one volt. Generally, the integrated circuits are supplied by a supply voltage of value identical to that of each of the elementary functional elements.
• US Pat. No. 5,703,790 proposes placing power supply terminals of two processors in series, making it possible to supply them with a higher supply voltage.
• the frequency of the clock of the second processor is controlled by a regulation circuit as a function of the supply voltage of this second processor.
• the regulation is carried out by comparing the supply voltage of the second processor with a reference voltage. The difference in the two voltages then determines the clock frequency of the second processor.
• a shunt regulator placed in parallel with the second processor makes it possible to absorb part of the current coming from the first processor when the clock frequency control of the second processor does not make it possible to absorb a sufficient current.
• the clocks of the two processors being different, the current peaks of the two processors are not synchronized.
• the regulation circuit intervenes only on the frequency of recurrence of the second peaks so as to control the average current of the second processor. It is therefore not possible to operate without decoupling capacitors connected to the power supply terminals of the processors. Indeed, a current peak of the second processor would give rise to a destructive overvoltage at the terminals of the first processor, while at the same time the second processor would not have at its terminals a voltage of sufficient value.
• the problem is similar during current peaks of the first processor unless the second processor is protected by the shunt regulator, if the latter is sized for this current and if it is capable of dissipating the corresponding energy. Indeed, in this case, the energy sent to the supply terminals of the second processor could be dissipated instead of being stored in the decoupling capacitor.
• the decoupling capacitors are energy reserves at the terminals of the processors. These energy reserves must be sufficient to supply the current to the processors during the transient phases of the voltage regulation which acts by variation of the current consumed by the second processor.
• the dimensioning of these decoupling capacitors and the energy reserve they constitute must be adapted to the time response performance of the regulation. As the regulation by action on the current of the second processor is carried out by controlling the clock frequency of the latter, the decoupling capacitors must be dimensioned to supply energy during several clock cycles. If the control circuit switches between operation at a high frequency and operation at a low frequency according to patent US Pat. No. 5,703,790, the decoupling capacitors .
• the object of the invention is to remedy these drawbacks and, more particularly, to avoid design problems and energy losses of low voltage high current power supplies, while ensuring synchronization of the subassemblies of an integrated circuit and a simple architecture of an integrated circuit.
• this object is achieved by the fact that the clock input of each subset is connected to a common clock circuit and in that the clock input of at least one assembly is connected to the common clock circuit via a device capable of shifting the levels of the clock signal.
• the sub-assemblies are constituted so that the sum of the instantaneous supply currents passing through the elementary functional elements of a sub-assembly is close to those of the other sub-assemblies.
• the clock inputs of at least two adjacent subsets are connected by a device capable of shifting the levels of the clock signal.
• the device capable of shifting the levels of the clock signal may comprise at least one capacitor and / or at least one transistor.
• each of the sub-assemblies comprises a voltage limiting circuit connected between its supply terminals and preferably comprising a diode or a transistor.
• FIGS 1 and 2 show two particular embodiments of an integrated circuit according to the invention.
• Figures 3,4 and 5 show different particular embodiments of a subset of an integrated circuit according to the invention.
• the integrated circuit shown in FIG. 1 comprises several sub-assemblies 2 (five sub-assemblies 2a to 2e in FIG. 1).
• the sub-assemblies each comprise a first supply terminal B1, a second supply terminal B2 and a clock input, respectively H1 to H5.
• the subassemblies are connected in series, via their supply terminals B1 and B2, to the terminals of a supply voltage source 3, connected in parallel with a decoupling capacitor 4.
• the various sub- sets are traversed by the same current, noted I.
• the clock inputs H1 to H5 of the sub-sets 2a to 2e are connected to a common clock circuit 5 by means of devices 6,7 capable of shifting the levels of the clock signal.
• the shift of the levels of the clock signal consists in applying to the different subsets 2 clock signals whose voltage level is adapted to the different supply voltages. present at terminals B1 and B2 of the different sub-assemblies 2. It is not only, as in certain known systems, applying the same clock signal to different circuits of the system, supplied in parallel or independently (see in particular US5486783).
• the voltage offset of the clock signal levels is necessary to compensate for the potential differences due to the series supply of the different sub-assemblies 2.
• the clock inputs of two adjacent sub-assemblies are connected by a device 6 capable of shifting the levels of the signal d clock, respectively 6a between the clock inputs H1 and H2, 6b between the clock inputs H2 and H3, 6c between the clock inputs H3 and H4, and 6d between the clock inputs H4 and H5.
• the clock input (H5) of one of the sub-assemblies (2e) located at one end of the series can be advantageously connected by a device 6e capable of shifting the levels of the clock signal at the output of the circuit d common clock 5.
• the device 6 capable of shifting the levels of the clock signal known to those skilled in the art, makes it possible to transmit the clock signal (or any other signal) while shifting the levels so identical or independent.
• a device 6 capable of shifting the levels of the clock signal can for example be constituted by a simple capacitor, or by a circuit based on transistors or by a circuit based on transistors and capacitors, for example of the type described in l article “Low power CMOS level shifters by bootstrapping technique” (Electronics Letters 1 st August 2002, Vol. 38 No. 16).
• connection represents only certain types of connection: power and clock connections.
• Other connections can coexist between the subsets for example for data transmission, these other connections may include complex devices such as for example devices capable of shifting signal levels.
• the clock input, respectively H1 to H5, of a subset, respectively 2a to 2e, is connected to an output of the clock circuit 5 by by means of a device 7 capable of shifting the levels of the clock signal (respectively 7a to 7e), of the same type as the device 6 in FIG. 1.
• a sub-assembly 2 includes a decoupling capacitor 8 and a voltage limiting circuit 9, connected in parallel between the supply terminals B1 and B2, thus making it possible to avoid an excessively high voltage between the supply terminals of the corresponding sub-assembly.
• the voltage limiting circuits 9 are for example constituted, in a known manner, by diodes or transistors.
• the voltage limiting circuit 9 is constituted by a Zener diode, in FIG. 4 by a direct polarized diode junction, and in FIG. 5, by a device based on transistors.
• Each sub-assembly can be composed of several elementary functional elements 1 0, connected in parallel between the supply terminals B1 and B2.
• the elementary functional elements themselves comprise a large number of elementary transistors.
• the particular internal architecture of an integrated circuit allows the supply of the circuit at voltages greater than or equal to the standard voltages (for example 3.3V) and ensures the supply of the various transistors at voltages significantly lower by example at the volt, while ensuring a synchronization of the subsets thanks to the common clock.
• the standard voltages for example 3.3V
• all of the sub-assemblies 2 are at different electrical potentials.
• the difference in potential between the two extreme sub-assemblies is all the greater, compared with the supply voltage across one of the sub-assemblies, as the number of sub-assemblies increases. Consequently, the sub-assemblies must be separated by means of electrical insulation.
• This electrical isolation can be carried out in any known manner, for example by the use of reverse polarized diode junctions and / or dielectric zones and / or by the production of silicon islands, isolated by dielectric zones, produced from a silicon on insulator substrate (“SOI: silicon-on-insulator”).
• SOI silicon-on-insulator
• the transmission of the clock signal to the different subsets by the devices 6,7 capable of shifting the levels of the clock signal (6a to 6d in FIG. 1 or 7a to 7e in FIG. 2) makes it possible to provide a very good synchronization.
• the embodiment in FIG. 2 is a preferred mode, because it ensures better synchronization of the sub-assemblies in principle. Indeed, in the embodiment of Figure 1, the devices 6 are in series and cause a summation of the delays, while in the embodiment of Figure 2, the devices 7 are in parallel and the delays can be identical for each of the subsets.
• a subset tends to consume slightly less current at a given instant than the other subsets, as the current flowing through it is defined, the voltage across the subsets increases. This operating mode can be tolerated. Otherwise, it can be adapted to include in each of the sub-assemblies a voltage limiting circuit 9, of the type described above, through which the excess current of the corresponding sub-assembly passes. This is why the invention is also particularly interesting. when all the elementary functional elements 10 are identical in all the sub-assemblies: the consumptions are therefore then all identical. This is the case, for example, of SIMD type architectures (abbreviation of the English term "single instruction multiple data streams").
• this excess current should be less than 20% of the average current passing through the subassembly. In this case, it is not bothersome to dissipate the energy corresponding to this current and to the voltage of the sub-assembly.
• the voltage limiting circuit 9 can be produced by a Zener diode (FIG. 3), a direct polarized diode junction (FIG. 4) or a transistor of controlled MOSFET type (FIG. 5).
• the grid of the MOSFET can in particular be controlled by the output of a voltage comparator, comparing the voltage across the terminals of a sub-assembly with a reference voltage.
• the voltage limiting circuit 9 can be integrated into the semiconductor.
• the additional decoupling capacitor 8 which can be included in each sub-assembly, makes it possible to supply or absorb brief transient differences in currents between the sub-assemblies. These additional capacitors must supply or absorb only a small part of the current pulses. As a result, these low-value capacitors can be integrated into the semiconductor.
• This additional decoupling function can be provided in whole or in part by the parasitic capacitance of the subassembly and of the device used for limiting the voltage. This represents an important advantage compared to the prior art, which requires the realization on each subset of high energy storage in the decoupling capacitors.
• An integrated circuit according to the invention can be powered by a conventional switching power supply 3 at a voltage of five volts for example. The invention
• the isolation of the sub-assemblies from each other, the circuit 9 for limiting the voltage of each sub-assembly, the decoupling means 8) can be produced in an integrated semiconductor circuit and use a small part of the surface semiconductor, which amounts to a low additional cost of production.
• An SOI type substrate is particularly suitable for carrying out the invention.
• the elementary functional elements not used in a circuit can be disconnected from the supply by transistors used as switches and the value of the supply voltage supplied to the integrated circuit. by the switching power supply or by the step-down regulator dedicated to the integrated circuit can be controlled.
• the consumption of a circuit according to the invention can be minimized by using one or more of the following three means:
• the criterion of identical current consumption of the subassemblies must be fulfilled.
• Short-circuit the supply terminals B1 and B2 of a sub-assembly with an auxiliary transistor to cancel the consumption of this sub-assembly and adapt the voltage supplied to the integrated circuit accordingly.

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• 2002
  • 2002-11-25 FR FR0214763A patent/FR2847715B1/fr not_active Expired - Fee Related
• 2003
  • 2003-11-21 US US10/534,462 patent/US20060006913A1/en not_active Abandoned
  • 2003-11-21 WO PCT/FR2003/003449 patent/WO2004051446A1/fr not_active Application Discontinuation
  • 2003-11-21 EP EP03786047A patent/EP1565804A1/de not_active Withdrawn

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