EP1565804A1 - Integrated circuit comprising series-connected subassemblies - Google Patents

Integrated circuit comprising series-connected subassemblies

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Publication number
EP1565804A1
EP1565804A1 EP03786047A EP03786047A EP1565804A1 EP 1565804 A1 EP1565804 A1 EP 1565804A1 EP 03786047 A EP03786047 A EP 03786047A EP 03786047 A EP03786047 A EP 03786047A EP 1565804 A1 EP1565804 A1 EP 1565804A1
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
sub
assemblies
clock
supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03786047A
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German (de)
French (fr)
Inventor
Daniel Chatroux
Marc Belleville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1565804A1 publication Critical patent/EP1565804A1/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Definitions

  • the invention relates to an integrated circuit comprising at least one digital part comprising a large number of elementary transistors, connected together so as to form a plurality of elementary functional elements, the elementary functional elements being grouped in sub-assemblies, each comprising first and second electrical supply terminals and a clock input, the sub-assemblies being connected in series, via their supply terminals, to the terminals of a supply voltage source.
  • Digital integrated circuits such as microprocessors, microcontrollers, memories, etc. are made up of an ever-increasing number of elementary transistors, of increasingly smaller size. It is well known that according to Moore's law, the number of transistors on a silicon surface doubles every 18 months. Thus, every 18 months, on the same silicon substrate, the number of integrated circuits doubles and the size of each of them decreases. This reduction in size allows increased operating frequencies.
  • the decrease in size of the transistors means that the maximum supply voltage that can be supported by the transistors decreases.
  • the increase in the number of transistors imposes higher supply currents. This current also increases when the clock frequency is higher.
  • the current supply voltages are of the order of a volt.
  • the generations following integrated circuits will be supplied with voltages lower than one volt. Generally, the integrated circuits are supplied by a supply voltage of value identical to that of each of the elementary functional elements.
  • US Pat. No. 5,703,790 proposes placing power supply terminals of two processors in series, making it possible to supply them with a higher supply voltage.
  • the frequency of the clock of the second processor is controlled by a regulation circuit as a function of the supply voltage of this second processor.
  • the regulation is carried out by comparing the supply voltage of the second processor with a reference voltage. The difference in the two voltages then determines the clock frequency of the second processor.
  • a shunt regulator placed in parallel with the second processor makes it possible to absorb part of the current coming from the first processor when the clock frequency control of the second processor does not make it possible to absorb a sufficient current.
  • the clocks of the two processors being different, the current peaks of the two processors are not synchronized.
  • the regulation circuit intervenes only on the frequency of recurrence of the second peaks so as to control the average current of the second processor. It is therefore not possible to operate without decoupling capacitors connected to the power supply terminals of the processors. Indeed, a current peak of the second processor would give rise to a destructive overvoltage at the terminals of the first processor, while at the same time the second processor would not have at its terminals a voltage of sufficient value.
  • the problem is similar during current peaks of the first processor unless the second processor is protected by the shunt regulator, if the latter is sized for this current and if it is capable of dissipating the corresponding energy. Indeed, in this case, the energy sent to the supply terminals of the second processor could be dissipated instead of being stored in the decoupling capacitor.
  • the decoupling capacitors are energy reserves at the terminals of the processors. These energy reserves must be sufficient to supply the current to the processors during the transient phases of the voltage regulation which acts by variation of the current consumed by the second processor.
  • the dimensioning of these decoupling capacitors and the energy reserve they constitute must be adapted to the time response performance of the regulation. As the regulation by action on the current of the second processor is carried out by controlling the clock frequency of the latter, the decoupling capacitors must be dimensioned to supply energy during several clock cycles. If the control circuit switches between operation at a high frequency and operation at a low frequency according to patent US Pat. No. 5,703,790, the decoupling capacitors .
  • the object of the invention is to remedy these drawbacks and, more particularly, to avoid design problems and energy losses of low voltage high current power supplies, while ensuring synchronization of the subassemblies of an integrated circuit and a simple architecture of an integrated circuit.
  • this object is achieved by the fact that the clock input of each subset is connected to a common clock circuit and in that the clock input of at least one assembly is connected to the common clock circuit via a device capable of shifting the levels of the clock signal.
  • the sub-assemblies are constituted so that the sum of the instantaneous supply currents passing through the elementary functional elements of a sub-assembly is close to those of the other sub-assemblies.
  • the clock inputs of at least two adjacent subsets are connected by a device capable of shifting the levels of the clock signal.
  • the device capable of shifting the levels of the clock signal may comprise at least one capacitor and / or at least one transistor.
  • each of the sub-assemblies comprises a voltage limiting circuit connected between its supply terminals and preferably comprising a diode or a transistor.
  • FIGS 1 and 2 show two particular embodiments of an integrated circuit according to the invention.
  • Figures 3,4 and 5 show different particular embodiments of a subset of an integrated circuit according to the invention.
  • the integrated circuit shown in FIG. 1 comprises several sub-assemblies 2 (five sub-assemblies 2a to 2e in FIG. 1).
  • the sub-assemblies each comprise a first supply terminal B1, a second supply terminal B2 and a clock input, respectively H1 to H5.
  • the subassemblies are connected in series, via their supply terminals B1 and B2, to the terminals of a supply voltage source 3, connected in parallel with a decoupling capacitor 4.
  • the various sub- sets are traversed by the same current, noted I.
  • the clock inputs H1 to H5 of the sub-sets 2a to 2e are connected to a common clock circuit 5 by means of devices 6,7 capable of shifting the levels of the clock signal.
  • the shift of the levels of the clock signal consists in applying to the different subsets 2 clock signals whose voltage level is adapted to the different supply voltages. present at terminals B1 and B2 of the different sub-assemblies 2. It is not only, as in certain known systems, applying the same clock signal to different circuits of the system, supplied in parallel or independently (see in particular US5486783).
  • the voltage offset of the clock signal levels is necessary to compensate for the potential differences due to the series supply of the different sub-assemblies 2.
  • the clock inputs of two adjacent sub-assemblies are connected by a device 6 capable of shifting the levels of the signal d clock, respectively 6a between the clock inputs H1 and H2, 6b between the clock inputs H2 and H3, 6c between the clock inputs H3 and H4, and 6d between the clock inputs H4 and H5.
  • the clock input (H5) of one of the sub-assemblies (2e) located at one end of the series can be advantageously connected by a device 6e capable of shifting the levels of the clock signal at the output of the circuit d common clock 5.
  • the device 6 capable of shifting the levels of the clock signal known to those skilled in the art, makes it possible to transmit the clock signal (or any other signal) while shifting the levels so identical or independent.
  • a device 6 capable of shifting the levels of the clock signal can for example be constituted by a simple capacitor, or by a circuit based on transistors or by a circuit based on transistors and capacitors, for example of the type described in l article “Low power CMOS level shifters by bootstrapping technique” (Electronics Letters 1 st August 2002, Vol. 38 No. 16).
  • connection represents only certain types of connection: power and clock connections.
  • Other connections can coexist between the subsets for example for data transmission, these other connections may include complex devices such as for example devices capable of shifting signal levels.
  • the clock input, respectively H1 to H5, of a subset, respectively 2a to 2e, is connected to an output of the clock circuit 5 by by means of a device 7 capable of shifting the levels of the clock signal (respectively 7a to 7e), of the same type as the device 6 in FIG. 1.
  • a sub-assembly 2 includes a decoupling capacitor 8 and a voltage limiting circuit 9, connected in parallel between the supply terminals B1 and B2, thus making it possible to avoid an excessively high voltage between the supply terminals of the corresponding sub-assembly.
  • the voltage limiting circuits 9 are for example constituted, in a known manner, by diodes or transistors.
  • the voltage limiting circuit 9 is constituted by a Zener diode, in FIG. 4 by a direct polarized diode junction, and in FIG. 5, by a device based on transistors.
  • Each sub-assembly can be composed of several elementary functional elements 1 0, connected in parallel between the supply terminals B1 and B2.
  • the elementary functional elements themselves comprise a large number of elementary transistors.
  • the particular internal architecture of an integrated circuit allows the supply of the circuit at voltages greater than or equal to the standard voltages (for example 3.3V) and ensures the supply of the various transistors at voltages significantly lower by example at the volt, while ensuring a synchronization of the subsets thanks to the common clock.
  • the standard voltages for example 3.3V
  • all of the sub-assemblies 2 are at different electrical potentials.
  • the difference in potential between the two extreme sub-assemblies is all the greater, compared with the supply voltage across one of the sub-assemblies, as the number of sub-assemblies increases. Consequently, the sub-assemblies must be separated by means of electrical insulation.
  • This electrical isolation can be carried out in any known manner, for example by the use of reverse polarized diode junctions and / or dielectric zones and / or by the production of silicon islands, isolated by dielectric zones, produced from a silicon on insulator substrate (“SOI: silicon-on-insulator”).
  • SOI silicon-on-insulator
  • the transmission of the clock signal to the different subsets by the devices 6,7 capable of shifting the levels of the clock signal (6a to 6d in FIG. 1 or 7a to 7e in FIG. 2) makes it possible to provide a very good synchronization.
  • the embodiment in FIG. 2 is a preferred mode, because it ensures better synchronization of the sub-assemblies in principle. Indeed, in the embodiment of Figure 1, the devices 6 are in series and cause a summation of the delays, while in the embodiment of Figure 2, the devices 7 are in parallel and the delays can be identical for each of the subsets.
  • a subset tends to consume slightly less current at a given instant than the other subsets, as the current flowing through it is defined, the voltage across the subsets increases. This operating mode can be tolerated. Otherwise, it can be adapted to include in each of the sub-assemblies a voltage limiting circuit 9, of the type described above, through which the excess current of the corresponding sub-assembly passes. This is why the invention is also particularly interesting. when all the elementary functional elements 10 are identical in all the sub-assemblies: the consumptions are therefore then all identical. This is the case, for example, of SIMD type architectures (abbreviation of the English term "single instruction multiple data streams").
  • this excess current should be less than 20% of the average current passing through the subassembly. In this case, it is not bothersome to dissipate the energy corresponding to this current and to the voltage of the sub-assembly.
  • the voltage limiting circuit 9 can be produced by a Zener diode (FIG. 3), a direct polarized diode junction (FIG. 4) or a transistor of controlled MOSFET type (FIG. 5).
  • the grid of the MOSFET can in particular be controlled by the output of a voltage comparator, comparing the voltage across the terminals of a sub-assembly with a reference voltage.
  • the voltage limiting circuit 9 can be integrated into the semiconductor.
  • the additional decoupling capacitor 8 which can be included in each sub-assembly, makes it possible to supply or absorb brief transient differences in currents between the sub-assemblies. These additional capacitors must supply or absorb only a small part of the current pulses. As a result, these low-value capacitors can be integrated into the semiconductor.
  • This additional decoupling function can be provided in whole or in part by the parasitic capacitance of the subassembly and of the device used for limiting the voltage. This represents an important advantage compared to the prior art, which requires the realization on each subset of high energy storage in the decoupling capacitors.
  • An integrated circuit according to the invention can be powered by a conventional switching power supply 3 at a voltage of five volts for example. The invention
  • the isolation of the sub-assemblies from each other, the circuit 9 for limiting the voltage of each sub-assembly, the decoupling means 8) can be produced in an integrated semiconductor circuit and use a small part of the surface semiconductor, which amounts to a low additional cost of production.
  • An SOI type substrate is particularly suitable for carrying out the invention.
  • the elementary functional elements not used in a circuit can be disconnected from the supply by transistors used as switches and the value of the supply voltage supplied to the integrated circuit. by the switching power supply or by the step-down regulator dedicated to the integrated circuit can be controlled.
  • the consumption of a circuit according to the invention can be minimized by using one or more of the following three means:
  • the criterion of identical current consumption of the subassemblies must be fulfilled.
  • Short-circuit the supply terminals B1 and B2 of a sub-assembly with an auxiliary transistor to cancel the consumption of this sub-assembly and adapt the voltage supplied to the integrated circuit accordingly.

Abstract

The invention concerns an integrated circuit comprising series-connected subassemblies (2), to provide simple synchronization of the subassemblies. Each subassembly includes a first line terminal (B1) and a second line terminal (B2) and a clock input (H1 to H5). The subassemblies are connected in series to the terminals of a supply voltage source (3), such that the various subassemblies circulate the same current (I). The clock input (H1 to H5) of each subassembly (2a to 2e) is connected to a common clock circuit (5) via devices (6a to 6e) adapted to offset the clock signal levels, for example comprising capacitors and/or transistors. Each subassembly can include one by-pass capacitor and one voltage limiting circuit between its first and second line terminals.

Description

Circuit intégré comportant des sous-ensembles connectés en sérieIntegrated circuit comprising sub-assemblies connected in series
Domaine technique de l'inventionTechnical field of the invention
L'invention concerne un circuit intégré comportant au moins une partie numérique comportant un grand nombre de transistors élémentaires, connectés entre eux de manière à former une pluralité d'éléments fonctionnels élémentaires, les éléments fonctionnels élémentaires étant groupés en sous- ensembles, comportant chacun des première et seconde bornes d'alimentation électrique et une entrée d'horloge, les sous-ensembles étant connectés en série, par l'intermédiaire de leurs bornes d'alimentation, aux bornes d'une source de tension d'alimentation.The invention relates to an integrated circuit comprising at least one digital part comprising a large number of elementary transistors, connected together so as to form a plurality of elementary functional elements, the elementary functional elements being grouped in sub-assemblies, each comprising first and second electrical supply terminals and a clock input, the sub-assemblies being connected in series, via their supply terminals, to the terminals of a supply voltage source.
Etat de la techniqueState of the art
Les circuits intégrés numériques comme les microprocesseurs, les microcontrôleurs, les mémoires, etc .. sont constitués d'un nombre sans cesse croissant de transistors élémentaires, de taille de plus en plus petite. Il est bien connu que selon la loi de Moore, le nombre de transistors sur une surface de silicium double tous les 18 mois. Ainsi, tous les 18 mois, sur le même substrat de silicium, le nombre de circuits intégrés double et la taille de chacun d'eux diminue. Cette diminution de taille permet des fréquences de fonctionnement accrues. La décroissance de taille des transistors impose que la tension d'alimentation maximale supportable par les transistors baisse. L'augmentation du nombre de transistors impose des courants d'alimentation plus élevés. Ce courant augmente aussi lorsque la fréquence d'horloge est plus élevée. Les tensions d'alimentation actuelles sont de l'ordre du volt. Les générations suivantes de circuits intégrés seront alimentées par des tensions inférieures au volt. Généralement, les circuits intégrés sont alimentés par une tension d'alimentation de valeur identique à celle de chacun des éléments fonctionnels élémentaires.Digital integrated circuits such as microprocessors, microcontrollers, memories, etc. are made up of an ever-increasing number of elementary transistors, of increasingly smaller size. It is well known that according to Moore's law, the number of transistors on a silicon surface doubles every 18 months. Thus, every 18 months, on the same silicon substrate, the number of integrated circuits doubles and the size of each of them decreases. This reduction in size allows increased operating frequencies. The decrease in size of the transistors means that the maximum supply voltage that can be supported by the transistors decreases. The increase in the number of transistors imposes higher supply currents. This current also increases when the clock frequency is higher. The current supply voltages are of the order of a volt. The generations following integrated circuits will be supplied with voltages lower than one volt. Generally, the integrated circuits are supplied by a supply voltage of value identical to that of each of the elementary functional elements.
La diminution des tensions d'alimentation de ces circuits intégrés numériques et l'augmentation simultanée du courant consommé donne lieu à des problèmes de conception et de pertes d'énergie des alimentations de tension au niveau des fils et des pistes de transmission du courant et des connexions d'alimentation du composant.The reduction in the supply voltages of these digital integrated circuits and the simultaneous increase in the current consumed gives rise to problems of design and of energy losses of the voltage supplies at the level of the wires and of the transmission tracks of the current and the component power connections.
Le brevet US5703790 propose la mise en série de bornes d'alimentation de deux processeurs, permettant de les alimenter par une tension d'alimentation plus élevée. La fréquence de l'horloge du second processeur est pilotée par un circuit de régulation en fonction de la tension d'alimentation de ce second processeur. La régulation est effectuée par comparaison de la tension d'alimentation du second processeur avec une tension de référence. L'écart des deux tensions détermine ensuite la fréquence de l'horloge du second processeur. Un régulateur shunt placé en parallèle avec le second processeur permet d'absorber une partie du courant provenant du premier processeur lorsque le pilotage de fréquence d'horloge du second processeur ne permet pas d'absorber un courant suffisant.US Pat. No. 5,703,790 proposes placing power supply terminals of two processors in series, making it possible to supply them with a higher supply voltage. The frequency of the clock of the second processor is controlled by a regulation circuit as a function of the supply voltage of this second processor. The regulation is carried out by comparing the supply voltage of the second processor with a reference voltage. The difference in the two voltages then determines the clock frequency of the second processor. A shunt regulator placed in parallel with the second processor makes it possible to absorb part of the current coming from the first processor when the clock frequency control of the second processor does not make it possible to absorb a sufficient current.
Les horloges des deux processeurs étant différentes, les pics de courant des deux processeurs ne sont pas synchronisés. Le circuit de régulation intervient uniquement sur la fréquence de récurrence des seconds pics de manière à contrôler le courant moyen du second processeur. Il n'est alors pas possible de fonctionner sans condensateurs de découplage connectés aux bornes d'alimentation des processeurs. En effet, un pic de courant du second processeur donnerait lieu à une surtension destructrice aux bornes du premier processeur, alors que dans le même temps le second processeur n'aurait pas à ses bornes une tension de valeur suffisante. Le problème est similaire lors des pics de courant du premier processeur sauf si le second processeur est protégé par le régulateur shunt, si celui-ci est dimensionné pour ce courant et s'il est capable de dissiper l'énergie correspondante. En effet, dans ce cas, l'énergie envoyée sur les bornes d'alimentation du second processeur pourrait être dissipée au lieu d'être stockée dans le condensateur de découplage.The clocks of the two processors being different, the current peaks of the two processors are not synchronized. The regulation circuit intervenes only on the frequency of recurrence of the second peaks so as to control the average current of the second processor. It is therefore not possible to operate without decoupling capacitors connected to the power supply terminals of the processors. Indeed, a current peak of the second processor would give rise to a destructive overvoltage at the terminals of the first processor, while at the same time the second processor would not have at its terminals a voltage of sufficient value. The problem is similar during current peaks of the first processor unless the second processor is protected by the shunt regulator, if the latter is sized for this current and if it is capable of dissipating the corresponding energy. Indeed, in this case, the energy sent to the supply terminals of the second processor could be dissipated instead of being stored in the decoupling capacitor.
Les condensateurs de découplage sont des réserves d'énergie aux bornes des processeurs. Il est nécessaire que ces réserves d'énergie soient suffisantes pour fournir le courant aux processeurs pendant les phases transitoires de la régulation de tension qui agit par variation du courant consommé par le second processeur. Le dimensionnement de ces condensateurs de découplage et de la réserve d'énergie qu'ils constituent doit être adapté aux performances de réponse temporelle de la régulation. Comme la régulation par action sur le courant du second processeur s'effectue par contrôle de la fréquence d'horloge de celui-ci, les condensateurs de découplage doivent être dimensionnés pour fournir l'énergie pendant plusieurs cycles d'horloge. Si le circuit de régulation commute entre un fonctionnement à une fréquence haute et un fonctionnement à une fréquence basse selon le brevet US5703790, les condensateurs de découplage. doivent être de valeur élevée pour être adaptés aux constantes de temps souvent longues de ce mode de régulation puisque l'on fonctionne en trains d'onde successivement à fréquence haute et fréquence basse. On se heurte alors aux problèmes technologiques de réalisation de ces condensateurs de découplage, de forte valeur sous basse tension, devant fournir les impulsions de courant. Objet de l'inventionThe decoupling capacitors are energy reserves at the terminals of the processors. These energy reserves must be sufficient to supply the current to the processors during the transient phases of the voltage regulation which acts by variation of the current consumed by the second processor. The dimensioning of these decoupling capacitors and the energy reserve they constitute must be adapted to the time response performance of the regulation. As the regulation by action on the current of the second processor is carried out by controlling the clock frequency of the latter, the decoupling capacitors must be dimensioned to supply energy during several clock cycles. If the control circuit switches between operation at a high frequency and operation at a low frequency according to patent US Pat. No. 5,703,790, the decoupling capacitors . must be of high value to be adapted to the often long time constants of this mode of regulation since one operates in wave trains successively at high frequency and low frequency. We then come up against the technological problems of producing these decoupling capacitors, of high value under low voltage, having to supply the current pulses. Subject of the invention
L'invention a, pour but de remédier à ces inconvénients et, plus particulièrement, d'éviter des problèmes de conception et de pertes d'énergie des alimentations de basse tension à courant fort, tout en assurant une synchronisation des sous- ensembles d'un circuit intégré et une architecture simple d'un circuit intégré.The object of the invention is to remedy these drawbacks and, more particularly, to avoid design problems and energy losses of low voltage high current power supplies, while ensuring synchronization of the subassemblies of an integrated circuit and a simple architecture of an integrated circuit.
Selon l'invention, ce but est atteint par le fait que l'entrée d'horloge de chaque sous-ensemble est connectée à un circuit d'horloge commun et en ce que l'entrée d'horloge d'au moins un sous-ensemble est connectée au circuit d'horloge commun par l'intermédiaire d'un dispositif apte à décaler les niveaux du signal d'horloge.According to the invention, this object is achieved by the fact that the clock input of each subset is connected to a common clock circuit and in that the clock input of at least one assembly is connected to the common clock circuit via a device capable of shifting the levels of the clock signal.
Selon un développement de l'invention, les sous-ensembles sont constitués de façon à ce que la somme des courants instantanés d'alimentation traversant les éléments fonctionnels élémentaires d'un sous-ensemble est voisine de celles des autres sous-ensembles.According to a development of the invention, the sub-assemblies are constituted so that the sum of the instantaneous supply currents passing through the elementary functional elements of a sub-assembly is close to those of the other sub-assemblies.
Selon un autre développement de l'invention, les entrées d'horloge d'au moins deux sous-ensembles adjacents sont connectées par un dispositif apte à décaler les niveaux du signal d'horloge.According to another development of the invention, the clock inputs of at least two adjacent subsets are connected by a device capable of shifting the levels of the clock signal.
Le dispositif apte à décaler les niveaux du signal d'horloge peut comporter au moins un condensateur et/ou au moins un transistor.The device capable of shifting the levels of the clock signal may comprise at least one capacitor and / or at least one transistor.
Selon un mode de réalisation préférentiel, chacun des sous-ensembles comporte un circuit de limitation de tension connecté entre ses bornes d'alimentation et comportant, de préférence, une diode ou un transistor. Description sommaire des dessinsAccording to a preferred embodiment, each of the sub-assemblies comprises a voltage limiting circuit connected between its supply terminals and preferably comprising a diode or a transistor. Brief description of the drawings
D'autres avantages et caractéristiques ressortiront plus clairement de la description qui va suivre de modes particuliers de réalisation de l'invention donnés à titre d'exemples non limitatifs et représentés aux dessins annexés, dans lesquels :Other advantages and characteristics will emerge more clearly from the description which follows of particular embodiments of the invention given by way of nonlimiting examples and represented in the appended drawings, in which:
Les figures 1 et 2 représentent deux modes de réalisation particuliers d'un circuit intégré selon l'invention.Figures 1 and 2 show two particular embodiments of an integrated circuit according to the invention.
Les figures 3,4 et 5 représentent différents modes de réalisation particuliers d'un sous-ensemble d'un circuit intégré selon l'invention.Figures 3,4 and 5 show different particular embodiments of a subset of an integrated circuit according to the invention.
Description de modes particuliers de réalisation.Description of particular embodiments.
Le circuit intégré représenté à la figure 1 comporte plusieurs sous-ensembles 2 (cinq sous-ensembles 2a à 2e sur la figure 1 ). Les sous-ensembles comportent chacun une première borne d'alimentation B1 , une seconde borne d'alimentation B2 et une entrée d'horloge, respectivement H1 à H5. Les sous- ensembles sont connectés en série, par l'intermédiaire de leurs bornes d'alimentation B1 et B2, aux bornes d'une source de tension d'alimentation 3, connectée en parallèle avec un condensateur de découplage 4. Les différents sous-ensembles sont parcourus par le même courant, noté I. Les entrées d'horloge H1 à H5 des sous-ensembles 2a à 2e sont connectées à un circuit d'horloge commun 5 par l'intermédiaire de dispositifs 6,7 aptes à décaler les niveaux du signal d'horloge. Le décalage des niveaux du signal d'horloge consiste à appliquer aux différents sous-ensembles 2 des signaux d'horloge dont le niveau de tension est adapté aux différentes tensions d'alimentation présentes aux bornes B1 et B2 des différents sous-ensembles 2. Il ne s'agit pas seulement, comme dans certains systèmes connus, d'appliquer un même signal d'horloge à différents circuits du système, alimentés en parallèle ou indépendamment (voir notamment US5486783). Le décalage en tension des niveaux du signal d'horloge est nécessaire pour compenser les différences de potentiel dues à l'alimentation en série des différents sous-ensembles 2.The integrated circuit shown in FIG. 1 comprises several sub-assemblies 2 (five sub-assemblies 2a to 2e in FIG. 1). The sub-assemblies each comprise a first supply terminal B1, a second supply terminal B2 and a clock input, respectively H1 to H5. The subassemblies are connected in series, via their supply terminals B1 and B2, to the terminals of a supply voltage source 3, connected in parallel with a decoupling capacitor 4. The various sub- sets are traversed by the same current, noted I. The clock inputs H1 to H5 of the sub-sets 2a to 2e are connected to a common clock circuit 5 by means of devices 6,7 capable of shifting the levels of the clock signal. The shift of the levels of the clock signal consists in applying to the different subsets 2 clock signals whose voltage level is adapted to the different supply voltages. present at terminals B1 and B2 of the different sub-assemblies 2. It is not only, as in certain known systems, applying the same clock signal to different circuits of the system, supplied in parallel or independently (see in particular US5486783). The voltage offset of the clock signal levels is necessary to compensate for the potential differences due to the series supply of the different sub-assemblies 2.
Sur la figure 1 , les entrées d'horloge de deux sous-ensembles adjacents (c'est- à-dire dont les bornes d'alimentation B1 et B2 sont connectées) sont connectées par un dispositif 6 apte à décaler les niveaux du signal d'horloge, respectivement 6a entre les entrées d'horloge H1 et H2, 6b entre les entrées d'horloge H2 et H3, 6c entre les entrées d'horloge H3 et H4, et 6d entre les entrées d'horloge H4 et H5. L'entrée d'horloge (H5) d'un des sous-ensembles (2e) situé à une extrémité de la série peut être avantageusement connecté par un dispositif 6e apte à décaler les niveaux du signal d'horloge à la sortie du circuit d'horloge commun 5. Le dispositif 6 apte à décaler les niveaux du signal d'horloge, connu de l'homme de l'art, permet de transmettre le signal d'horloge (ou tout autre signal) tout en décalant les niveaux de façon identique ou indépendante.In FIG. 1, the clock inputs of two adjacent sub-assemblies (that is to say of which the supply terminals B1 and B2 are connected) are connected by a device 6 capable of shifting the levels of the signal d clock, respectively 6a between the clock inputs H1 and H2, 6b between the clock inputs H2 and H3, 6c between the clock inputs H3 and H4, and 6d between the clock inputs H4 and H5. The clock input (H5) of one of the sub-assemblies (2e) located at one end of the series can be advantageously connected by a device 6e capable of shifting the levels of the clock signal at the output of the circuit d common clock 5. The device 6 capable of shifting the levels of the clock signal, known to those skilled in the art, makes it possible to transmit the clock signal (or any other signal) while shifting the levels so identical or independent.
Un dispositif 6 apte à décaler les niveaux du signal d'horloge peut par exemple être constitué par un simple condensateur, ou par un circuit à base de transistors ou par un circuit à base de transistors et de condensateurs, par exemple du type décrit dans l'article « Low power CMOS level shifters by bootstrapping technique » (Electronics Letters 1 st August 2002, Vol. 38 No. 16).A device 6 capable of shifting the levels of the clock signal can for example be constituted by a simple capacitor, or by a circuit based on transistors or by a circuit based on transistors and capacitors, for example of the type described in l article “Low power CMOS level shifters by bootstrapping technique” (Electronics Letters 1 st August 2002, Vol. 38 No. 16).
Il faut remarquer que la figure 1 , ainsi que les autres figures, ne représente que certains types de connexion : les connexions d'alimentation et d'horloge. D'autres connexions peuvent coexister entre les sous-ensembles par exemple pour la transmission de données, ces autres connexions pouvant comprendre des dispositifs complexes comme par exemple des dispositifs aptes à décaler des niveaux de signaux.Note that Figure 1, as well as the other figures, represents only certain types of connection: power and clock connections. Other connections can coexist between the subsets for example for data transmission, these other connections may include complex devices such as for example devices capable of shifting signal levels.
Selon un autre mode de réalisation particulier, représenté à la figure 2, l'entrée d'horloge, respectivement H1 à H5, d'un sous-ensemble, respectivement 2a à 2e, est connectée à une sortie du circuit d'horloge 5 par l'intermédiaire d'un dispositif 7 apte à décaler les niveaux du signal d'horloge (respectivement 7a à 7e), du même type que le dispositif 6 de la figure 1 .According to another particular embodiment, represented in FIG. 2, the clock input, respectively H1 to H5, of a subset, respectively 2a to 2e, is connected to an output of the clock circuit 5 by by means of a device 7 capable of shifting the levels of the clock signal (respectively 7a to 7e), of the same type as the device 6 in FIG. 1.
Comme représenté aux figures 3 à 5, un sous-ensemble 2 comporte un condensateur de découplage 8 et un circuit 9 de limitation de tension, connectés en parallèle entre les bornes d'alimentation B1 et B2, permettant ainsi d'éviter une tension trop élevée entre les bornes d'alimentation du sous-ensemble correspondant. Les circuits de limitation de tension 9 sont par exemple constitués, de manière connue, par des diodes ou des transistors. A titre d'exemple, sur la figure 3, le circuit de limitation de tension 9 est constitué par une diode Zener, sur la figure 4 par une jonction de diode polarisée en direct, et sur la figure 5, par un dispositif à base de transistors. Chaque sous-ensemble peut être composé de plusieurs éléments fonctionnels élémentaires 1 0, connectés en parallèle entre les bornes d'alimentation B1 et B2. Les éléments fonctionnels élémentaires comportent eux-mêmes un grand nombre de transistors élémentaires.As shown in Figures 3 to 5, a sub-assembly 2 includes a decoupling capacitor 8 and a voltage limiting circuit 9, connected in parallel between the supply terminals B1 and B2, thus making it possible to avoid an excessively high voltage between the supply terminals of the corresponding sub-assembly. The voltage limiting circuits 9 are for example constituted, in a known manner, by diodes or transistors. By way of example, in FIG. 3, the voltage limiting circuit 9 is constituted by a Zener diode, in FIG. 4 by a direct polarized diode junction, and in FIG. 5, by a device based on transistors. Each sub-assembly can be composed of several elementary functional elements 1 0, connected in parallel between the supply terminals B1 and B2. The elementary functional elements themselves comprise a large number of elementary transistors.
L'architecture interne particulière d'un circuit intégré selon l'invention permet l'alimentation du circuit à des tensions supérieures ou égales aux tensions standard (par exemple 3,3V) et assure l'alimentation des différents transistors sous des tensions nettement inférieures par exemple au volt, tout en assurant une synchronisation des sous-ensembles grâce à l'horloge commune. En raison de leur mise en série, tous les sous-ensembles 2 sont à des potentiels électriques différents. La différence de potentiel entre les deux sous-ensembles extrêmes est d'autant plus importante, comparée avec la tension d'alimentation aux bornes d'un des sous-ensembles, que le nombre de sous-ensembles augmente. Par conséquent, les sous-ensembles doivent être séparés par des moyens d'isolation électrique. Cette isolation électrique peut être réalisée de toute manière connue, par exemple par l'utilisation de jonctions de diode polarisées en inverse et/ou de zones diélectriques et/ou par réalisation d'îlots de silicium, isolés par des zones diélectriques, réalisés à partir d'un substrat de silicium sur isolant (« SOI : silicon-on-insulator »).The particular internal architecture of an integrated circuit according to the invention allows the supply of the circuit at voltages greater than or equal to the standard voltages (for example 3.3V) and ensures the supply of the various transistors at voltages significantly lower by example at the volt, while ensuring a synchronization of the subsets thanks to the common clock. Because of their series connection, all of the sub-assemblies 2 are at different electrical potentials. The difference in potential between the two extreme sub-assemblies is all the greater, compared with the supply voltage across one of the sub-assemblies, as the number of sub-assemblies increases. Consequently, the sub-assemblies must be separated by means of electrical insulation. This electrical isolation can be carried out in any known manner, for example by the use of reverse polarized diode junctions and / or dielectric zones and / or by the production of silicon islands, isolated by dielectric zones, produced from a silicon on insulator substrate (“SOI: silicon-on-insulator”).
La transmission du signal d'horloge aux différents sous-ensembles par les dispositifs 6,7 aptes à décaler les niveaux du signal d'horloge (6a à 6d de la figure 1 ou 7a à 7e de la figure 2) permet d'assurer une très bonne synchronisation. Le mode de réalisation à la figure 2 est un mode préférentiel, car il assure une meilleure synchronisation des sous-ensembles par principe. En effet, dans le mode de réalisation de la figure 1 , les dispositifs 6 sont en série et entraînent une sommation des retards, alors que dans le mode de réalisation de la figure 2, les dispositifs 7 sont en parallèle et les retards peuvent être identiques pour chacun des sous-ensembles.The transmission of the clock signal to the different subsets by the devices 6,7 capable of shifting the levels of the clock signal (6a to 6d in FIG. 1 or 7a to 7e in FIG. 2) makes it possible to provide a very good synchronization. The embodiment in FIG. 2 is a preferred mode, because it ensures better synchronization of the sub-assemblies in principle. Indeed, in the embodiment of Figure 1, the devices 6 are in series and cause a summation of the delays, while in the embodiment of Figure 2, the devices 7 are in parallel and the delays can be identical for each of the subsets.
Si un sous-ensemble tend à consommer à un instant donné un peu moins de courant que les autres sous-ensembles, comme le courant qui le traverse est défini, la tension aux bornes du sous-ensemble augmente. Ce mode de fonctionnement peut être toléré. Sinon, il peut être adapté d'inclure à chacun des sous-ensembles un circuit de limitation de la tension 9, du type décrit ci- dessus, par lequel passe le courant excédentaire du sous-ensemble correspondant. C'est pourquoi l'invention est aussi particulièrement intéressante quand tous les éléments fonctionnels élémentaires 10 sont identiques dans tous les sous-ensembles : les consommations sont donc alors bien toutes identiques. C'est le cas par exemple des architectures de type SIMD (abréviation du terme anglais « single instruction multiple data streams »).If a subset tends to consume slightly less current at a given instant than the other subsets, as the current flowing through it is defined, the voltage across the subsets increases. This operating mode can be tolerated. Otherwise, it can be adapted to include in each of the sub-assemblies a voltage limiting circuit 9, of the type described above, through which the excess current of the corresponding sub-assembly passes. This is why the invention is also particularly interesting. when all the elementary functional elements 10 are identical in all the sub-assemblies: the consumptions are therefore then all identical. This is the case, for example, of SIMD type architectures (abbreviation of the English term "single instruction multiple data streams").
Typiquement, en moyenne ce courant excédentaire devrait être inférieur à 20 % du courant moyen traversant le sous-ensemble. Dans ce cas, il n'est alors pas gênant de dissiper l'énergie correspondant à ce courant et à la tension du sous- ensemble.Typically, on average, this excess current should be less than 20% of the average current passing through the subassembly. In this case, it is not bothersome to dissipate the energy corresponding to this current and to the voltage of the sub-assembly.
A titre d'exemple, le circuit de limitation de la tension 9 peut être réalisé par une diode Zener (figure 3), une jonction de diode polarisée en direct (figure 4) ou un transistor de type MOSFET commandé (figure 5). La grille du MOSFET peut notamment être pilotée par la sortie d'un comparateur de tension, comparant la tension aux bornes d'un sous-ensemble à une tension de référence. Ainsi, pour chaque sous-ensemble, le circuit de limitation de la tension 9 peut être intégré dans le semi-conducteur.By way of example, the voltage limiting circuit 9 can be produced by a Zener diode (FIG. 3), a direct polarized diode junction (FIG. 4) or a transistor of controlled MOSFET type (FIG. 5). The grid of the MOSFET can in particular be controlled by the output of a voltage comparator, comparing the voltage across the terminals of a sub-assembly with a reference voltage. Thus, for each sub-assembly, the voltage limiting circuit 9 can be integrated into the semiconductor.
De même, le condensateur de découplage additionnel 8, qui peut être inclus dans chaque sous-ensemble, permet de fournir ou absorber des différences transitoires brèves de courants entre les sous-ensembles. Ces condensateurs additionnels ne doivent fournir ou absorber qu'une faible partie des impulsions de courant. De ce fait, ces condensateurs de faible valeur peuvent être intégrés dans le semi-conducteur. Cette fonction de découplage additionnel peut être assurée en tout ou en partie par la capacité parasite du sous-ensemble et du dispositif utilisé pour la limitation de la tension. Ceci représente un avantage important par rapport à l'art antérieur, qui nécessite la réalisation sur chaque sous-ensemble de forts stockages d'énergie dans les condensateurs de découplage. Un circuit intégré selon l'invention peut être alimenté par une alimentation 3 à découpage classique sous une tension de cinq volts par exemple. L'inventionLikewise, the additional decoupling capacitor 8, which can be included in each sub-assembly, makes it possible to supply or absorb brief transient differences in currents between the sub-assemblies. These additional capacitors must supply or absorb only a small part of the current pulses. As a result, these low-value capacitors can be integrated into the semiconductor. This additional decoupling function can be provided in whole or in part by the parasitic capacitance of the subassembly and of the device used for limiting the voltage. This represents an important advantage compared to the prior art, which requires the realization on each subset of high energy storage in the decoupling capacitors. An integrated circuit according to the invention can be powered by a conventional switching power supply 3 at a voltage of five volts for example. The invention
-permet d'assurer l'alimentation sous basse tension de chacun des sous- ensembles 2 de la série de sous-ensembles. Chacun des éléments nécessaires à la réalisation de l'invention (le circuit d'horloge 5 commun, les sous-ensembles-allows the supply of low voltage to each of the sub-assemblies 2 of the series of sub-assemblies. Each of the elements necessary for carrying out the invention (the common clock circuit 5, the sub-assemblies
2, l'isolation des sous-ensembles entre eux, le circuit 9 de limitation de la tension de chaque sous-ensemble, les moyens de découplage 8) sont réalisables dans un circuit intégré à semi-conducteur et utilisent une faible part de la surface du semi-conducteur, ce qui revient à un faible surcoût de la réalisation. Un substrat de type SOI est particulièrement adapté pour la réalisation de l'invention.2, the isolation of the sub-assemblies from each other, the circuit 9 for limiting the voltage of each sub-assembly, the decoupling means 8) can be produced in an integrated semiconductor circuit and use a small part of the surface semiconductor, which amounts to a low additional cost of production. An SOI type substrate is particularly suitable for carrying out the invention.
Pour minimiser la consommation d'un circuit intégré selon l'art antérieur, les éléments fonctionnels élémentaires non utilisés dans un circuit peuvent être déconnectés de l'alimentation par des transistors utilisés comme interrupteurs et la valeur de la tension d'alimentation fournie au circuit intégré par l'alimentation à découpage ou par le régulateur abaisseur dédié au circuit intégré peut être commandée.To minimize the consumption of an integrated circuit according to the prior art, the elementary functional elements not used in a circuit can be disconnected from the supply by transistors used as switches and the value of the supply voltage supplied to the integrated circuit. by the switching power supply or by the step-down regulator dedicated to the integrated circuit can be controlled.
La consommation d'un circuit selon l'invention peut être minimisée en utilisant un ou plusieurs des trois moyens suivants :The consumption of a circuit according to the invention can be minimized by using one or more of the following three means:
Déconnecter un élément fonctionnel élémentaire 10 non-utilisé d'un sous- ensemble 2 de l'alimentation de ce sous-ensemble par l'ouverture de transistors. Il faut cependant remplir le critère de consommation de courant identique des sous-ensembles. Par exemple, dans le cas de sous- ensembles identiques constitués d'éléments fonctionnels élémentaires identiques, il est préférable d'isoler le même élément fonctionnel élémentaire sur chacun des sous-ensembles au même moment. Court-circuiter les bornes d'alimentation B1 et B2 d'un sous-ensemble par un transistor auxiliaire pour annuler la consommation de ce sous-ensemble et adapter en conséquence la tension fournie au circuit intégré. Adapter la tension fournie au circuit intégré par l'alimentation à découpage ou le convertisseur abaisseur alimentant le circuit intégré.Disconnect an unused elementary functional element 10 from a sub-assembly 2 from the supply of this sub-assembly by opening transistors. However, the criterion of identical current consumption of the subassemblies must be fulfilled. For example, in the case of identical subsets made up of identical elementary functional elements, it is preferable to isolate the same elementary functional element on each of the subsets at the same time. Short-circuit the supply terminals B1 and B2 of a sub-assembly with an auxiliary transistor to cancel the consumption of this sub-assembly and adapt the voltage supplied to the integrated circuit accordingly. Adapt the voltage supplied to the integrated circuit by the switching power supply or the step-down converter supplying the integrated circuit.
La mise en série d'un grand nombre de sous-ensembles est possible. La limitation du nombre de sous-ensembles imposées par les régulations du circuit intégré selon le brevet US5703790 n'existe pas. The serialization of a large number of sub-assemblies is possible. The limitation of the number of sub-assemblies imposed by the regulations of the integrated circuit according to the patent US5703790 does not exist.

Claims

Revendications claims
1. Circuit intégré comportant au moins une partie numérique (1) comportant un grand nombre de transistors élémentaires, connectés entre eux de manière à former une pluralité d'éléments fonctionnels élémentaires (10), les éléments fonctionnels élémentaires étant groupés en sous-ensembles (2), comportant chacun des première (B1) et seconde (B2) bornes d'alimentation électrique et une entrée d'horloge (H), les sous-ensembles (2) étant connectés en série, par l'intermédiaire de leurs bornes d'alimentation (B1 et1. Integrated circuit comprising at least one digital part (1) comprising a large number of elementary transistors, connected together so as to form a plurality of elementary functional elements (10), the elementary functional elements being grouped into subsets ( 2), each comprising first (B1) and second (B2) electrical supply terminals and a clock input (H), the subassemblies (2) being connected in series, via their terminals d '' supply (B1 and
B2), aux bornes d'une source de tension d'alimentation (3), circuit intégré (1) caractérisé en ce que l'entrée d'horloge (H) de chaque sous-ensemble (2) est connectée à un circuit d'horloge commun (5) et en ce que l'entrée d'horloge (H) d'au moins un sous-ensemble (2) est connectée au circuit d'horloge commun (5) par l'intermédiaire d'un dispositif (6,7) apte à décaler les niveaux du signal d'horloge.B2), at the terminals of a supply voltage source (3), integrated circuit (1) characterized in that the clock input (H) of each sub-assembly (2) is connected to a circuit d common clock (5) and in that the clock input (H) of at least one sub-assembly (2) is connected to the common clock circuit (5) by means of a device ( 6,7) able to shift the levels of the clock signal.
2. Circuit intégré (1 ) selon la revendication 1 , caractérisé en ce que les sous- ensembles (2) sont constitués de façon à ce que la somme des courants instantanés d'alimentation traversant les éléments fonctionnels élémentaires2. Integrated circuit (1) according to claim 1, characterized in that the subassemblies (2) are constituted so that the sum of the instantaneous supply currents passing through the elementary functional elements
(10) d'un sous-ensemble soit voisine de celles des autres sous-ensembles.(10) of a subset is close to those of the other subsets.
3. Circuit intégré (1) selon l'une des revendications 1 et 2, caractérisé en ce que les entrées d'horloge (H) d'au moins deux sous-ensembles (2) adjacents sont connectées par un dispositif (6) apte à décaler les niveaux du signal d'horloge.3. Integrated circuit (1) according to one of claims 1 and 2, characterized in that the clock inputs (H) of at least two adjacent sub-assemblies (2) are connected by a device (6) capable shift the clock signal levels.
4. Circuit intégré (1) selon la revendication 3, caractérisé en ce que l'entrée d'horloge d'un des sous-ensembles d'extrémité (2e) est connectée par l'intermédiaire d'un dispositif (6e) additionnel apte à décaler les niveaux du signal d'horloge à la sortie du circuit d'horloge (5).4. Integrated circuit (1) according to claim 3, characterized in that the clock input of one of the end sub-assemblies (2e) is connected by through an additional device (6e) capable of shifting the levels of the clock signal at the output of the clock circuit (5).
5. Circuit intégré (1) selon l'une quelconque des revendications 1 à 4, caractérisé en ce que le dispositif (6,7) apte à décaler les niveaux du signal d'horloge comporte au moins un condensateur.5. Integrated circuit (1) according to any one of claims 1 to 4, characterized in that the device (6,7) capable of shifting the levels of the clock signal comprises at least one capacitor.
6. Circuit intégré (1 ) selon l'une quelconque des revendications 1 à 5, caractérisé en ce que le dispositif (6,7) apte à décaler les niveaux du signal d'horloge comporte au moins un transistor.6. Integrated circuit (1) according to any one of claims 1 to 5, characterized in that the device (6,7) capable of shifting the levels of the clock signal comprises at least one transistor.
7. Circuit intégré selon l'une quelconque des revendications 1 à 6, caractérisé en ce que tous les sous-ensembles (2) sont identiques.7. Integrated circuit according to any one of claims 1 to 6, characterized in that all the sub-assemblies (2) are identical.
8. Circuit intégré selon l'une quelconque des revendications 1 à 7, caractérisé en ce que chacun des sous-ensembles (2) comporte un circuit de limitation de tension (9) connecté entre ses bornes d'alimentation (B1 et B2).8. Integrated circuit according to any one of claims 1 to 7, characterized in that each of the sub-assemblies (2) comprises a voltage limiting circuit (9) connected between its supply terminals (B1 and B2).
9. Circuit intégré selon la revendication 8, caractérisé en ce que le circuit de limitation de tension (9) comporte une diode.9. Integrated circuit according to claim 8, characterized in that the voltage limiting circuit (9) comprises a diode.
10. Circuit intégré selon l'une des revendications 8 et 9, caractérisé en ce que le circuit de limitation de tension (9) comporte un transistor.10. Integrated circuit according to one of claims 8 and 9, characterized in that the voltage limiting circuit (9) comprises a transistor.
11. Circuit intégré selon l'une quelconque des revendications 1 à 10, caractérisé en ce que chaque sous-ensemble (2) comporte un condensateur (8) de découplage connecté entre la première (B1 ) et la seconde (B2) borne d'alimentation du sous-ensemble. 11. Integrated circuit according to any one of claims 1 to 10, characterized in that each sub-assembly (2) comprises a decoupling capacitor (8) connected between the first (B1) and the second (B2) terminal of power supply of the sub-assembly.
12. Circuit intégré selon l'une quelconque des revendication 1 à 11 , caractérisé en ce que le circuit intégré comporte des moyens d'isolation électrique entre les sous-ensembles.12. Integrated circuit according to any one of claims 1 to 11, characterized in that the integrated circuit comprises means of electrical insulation between the sub-assemblies.
13. Circuit intégré selon la revendication 12, caractérisé en ce que les moyens d'isolation électrique entre les différents sous-ensembles sont des jonctions de diode polarisées en inverse.13. Integrated circuit according to claim 12, characterized in that the electrical isolation means between the different sub-assemblies are diode junctions reverse biased.
14. Circuit intégré selon l'une des revendications 12 et 13, caractérisé en ce que les moyens d'isolation électrique entre les différents sous-ensembles sont des zones diélectriques.14. Integrated circuit according to one of claims 12 and 13, characterized in that the means of electrical insulation between the different sub-assemblies are dielectric zones.
15. Circuit intégré selon l'une quelconque des revendications 1 à 14, caractérisé en ce que le circuit intégré comporte des îlots de silicium réalisés à partir d'un substrat de silicium sur isolant. 15. Integrated circuit according to any one of claims 1 to 14, characterized in that the integrated circuit comprises islands of silicon produced from a silicon substrate on insulator.
EP03786047A 2002-11-25 2003-11-21 Integrated circuit comprising series-connected subassemblies Withdrawn EP1565804A1 (en)

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FR2847715B1 (en) 2005-03-11
FR2847715A1 (en) 2004-05-28
WO2004051446A1 (en) 2004-06-17
US20060006913A1 (en) 2006-01-12

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