FR2759507A1 - Voltage generator circuit for non-volatile memory - Google Patents

Abstract

The circuit includes a number of cells each with transistors manufactured using triple well technology. One of the cell transistors (6) has a trench (B1) which is supplied by two N type transistors (8,9). The transistor drains and gates are connected to the cell transistor and its trench, respectively. The two additional transistors are obtained in the second trench (B2) of the cell transistor. They reduce the risk of latch up thus reducing the substrate effect. They also reduce the voltage difference between the control gate and the trenches.

Description

CHARGE PUMP IN A
DOUBLE BOX TECHNOLOGY
The present invention relates to a voltage generator circuit of the charge pump type.

 Charge pumps are frequently used in integrated circuits to produce both positive and negative voltages. Thus, American patent US 5,077,691 describes a charge pump and its application in an EEPROM memory of the FLASH type.

 FIG. 1A schematically illustrates a known pump structure, produced in MOS technology from a substrate P. Such a circuit makes it possible to produce from a supply voltage Vcc, a positive voltage greater than the supply voltage . The principle of this voltage generator is to transfer electrical charges by pumping into a series of capacitors connected in series and isolated from each other by transistors or diodes.

Pumping is controlled by control signals A and
B which will be described in Figures 1C and 1D.

 The charge pump comprises a set of n elementary cells C1 to Cn, the structure of which is described in FIG. 1B. These cells are connected in series between an input 1 and an output 2. In the case of flash EEPROM type memories, the purpose of such a circuit is to produce a positive voltage VP of the order of 10 to 15 volts for the programming and erasing of memory cells.

 An elementary cell, illustrated in FIG. 1B, comprises an input 3 for receiving an input voltage IN, an output 4 for delivering an output voltage OUT, and an input 5 for receiving a clock signal CK.

It also includes:
an N-type transistor 6, the drain of which is connected to input 3 and the source to output 4, and
a capacitor 7, a first pole of which is connected to the drain and the control gate of the transistor 6, and the second pole of which is connected to the input 5.

 So that the junctions between the active regions of transistor 6 and the substrate are correctly polarized, the substrate of transistor 6 is connected to ground. Furthermore, the input 3 of the first cell C1 is connected via a transistor T to a supply terminal receiving the supply voltage Vcc. The control gate of transistor T is also connected to this supply terminal.

 In practice, the capacitor 7 is produced from an N-type transistor, the first pole of the capacitor 7 corresponding to the control gate of the transistor and the second pole corresponding to the source and to the drain connected to each other of the transistor.

 The clock signal CK applied to the input 5 is alternately either the control signal A or the control signal B illustrated in FIGS. 1C and 1D respectively.

The control signals A and B periodically switch between a ground potential (0 volts) and a supply potential Vcc. Any signal passing
B from Vcc to 0 volts causes signal A to go from 0 volts to Vcc. Conversely, any passage of signal A of
Vcc at 0 volts causes signal B to go from 0 volts to Vcc.

The operation of an elementary cell Ci is as follows: on each rising edge of the clock signal
CK (that is to say of the control signal A or B), positive charges are transmitted from input 3 to output 4 of cell Ci. Signals A and B being of opposite polarity, positive charges are then gradually transferred from one cell to another to deliver at the end of the chain a positive voltage VP on output 2. The output voltage of the charge pump is obtained by charging and discharging the capacitors consecutively.

 The voltage VP = (n + l) * (Vcc-Vt) is thus obtained at the output where Vt is the threshold voltage of the transistors 6 of the cells Ci. The amplitude of the output voltage VP is a function of the amplitude control signals (ie of the supply voltage), of the threshold voltage Vt and of the number of elementary stages of the pump.

 The charge pump as described is produced on a substrate P as has been said previously. This substrate is connected to ground so that all the junctions with the active regions of the transistor are reverse biased.

 However, the output voltage VP produced by this type of charge pump does not increase indefinitely by adding cells but tends towards an asymptotic value after a certain number of cells.

This limitation is mainly due to the substrate effect (body effect).

 Indeed, the voltage Vt depends on the source-substrate voltage Vsb which increases at each stage. The voltage Vt therefore also increases on each stage. However, for it to transfer charges from one elementary cell to another, the amplitude of the control signals, that is to say Vcc, must be greater than the threshold voltage Vt. As the threshold voltage Vt increases as one progresses towards the output 2, the transistors 6 of the elementary cells become less and less passing and the voltage VP reaches the asymptotic value when Vcc = Vt.

 This limit value is of the order of 25 volts in the case of a technology operating at 5 volts.

Since the voltages required for programming or erasing non-volatile memories rarely exceed 18 volts, this limitation of the voltage VP is not really a problem in this case.

 However, for cases where the supply voltage Vcc is lower, the threshold voltage Vt quickly becomes equal to Vcc and the voltage obtained at the output of the pump is then not very high. For example, in the case where the supply voltage Vcc is equal to 1.8 volts (key value of future technologies), the voltage VP obtained at the pump output is only 4 volts and is much lower than the value necessary for programming and erasing memory cells in non-volatile memory.

 An object of the invention is therefore to propose a charge pump structure making it possible to limit the substrate effect and thus to produce higher output voltages VP with the same number of elementary cells.

 Another object of the invention is to allow higher asymptotic values to be obtained for the same supply voltage Vcc.

 To limit the substrate effect, provision is made for the use of a double box technology, called "triple well" technology, in order to individually polarize the boxes of the transistors of the different pumping cells and to optimize the voltage Vsb for each cell. .

 It is also necessary that the casing of the pumping cell is connected to the drain or source electrode of the transistor on which the voltage is the lowest. Indeed, if the polarization voltage of the box comes to be higher than the voltage of one or other of these electrodes, the junction between this electrode and the box is then polarized directly and there is a risk of seeing a current appear parasitic through this junction. This phenomenon is called latchup in English.

 To avoid any risk of latch-up, each pumping cell includes means for biasing the well of the cell transistor.

Also, the subject of the invention is a circuit for generating a positive voltage of the charge pump type, produced from a P type substrate, and supplying an output with a positive voltage by pumping positive charges into n mounted pump cells. in series, each cell comprising at least one capacitor and an N-type flow transistor,
characterized in that the circuit is produced in a double-box technology comprising in a substrate, for each transistor, a first P-type box in which the drain zone and the source zone of said transistor are located, a second box containing the first well, the PN junctions between said wells and the substrate being reverse biased,
and in that each cell further comprises means for biasing the first well of said passage transistor to bias the first well at the lowest potential between that of the source and that of the drain of the passage transistor.

According to a first aspect of the invention, the polarization means comprise
a first N-type transistor whose control gate and drain are respectively connected to the source and to the drain of the passage transistor and whose source and the first well are connected to the first well of the passage transistor, and
- A second N-type transistor, the control gate and the source of which are connected to the drain and the source of the pass transistor, respectively, and whose drain and the first well are connected to the first well of the pass transistor.

 In the case of negative voltage generator circuits produced from a P-type substrate, technology requires that the P-type transistors of the pumping cells have an N-type well. It is therefore possible to individually polarize the wells of the pumping cells without using triple-well technology.

The invention therefore also relates to a negative voltage generator circuit of the charge pump type, produced from a P type substrate, and supplying an output with a negative voltage by pumping negative charges into n mounted pump cells. in series, each cell comprising at least one capacitor and a P-type pass transistor, each P-type transistor of the cell comprising an N-type well in the P-type substrate,
characterized in that the circuit further comprises biasing means for biasing the well of the pass transistor at the highest potential between that of the source and that of the drain of the pass transistor.

According to the invention, the means for biasing the well of the P-type pass transistor include
a first P-type transistor whose control gate and source are respectively connected to the drain and to the source of the pass transistor and whose drain and the well are connected to the well of the pass transistor, and
- A second P-type transistor whose control gate and drain are respectively connected to the source and to the drain of the passage transistor and whose source and the well are connected to the well of the passage transistor.

Other characteristics and advantages of the invention will appear on reading the detailed description which follows and which is given with reference to the appended drawings in which
- Figure lA, already described, schematically shows a charge pump of the prior art;
- Figure 1B, already described, shows a detailed diagram of an elementary cell of the pump of Figure lA;
- Figures 1C and 1D, already described, show timing diagrams of the control signals of the pump of Figure lA;
- Figure 2 shows a sectional view of an N-type transistor made in a double box technology;
- Figure 3 shows a detailed diagram of an elementary cell of a charge pump according to the invention;
- Figures 4a and 4b schematically show a second embodiment of a positive charge pump according to the invention;
- Figures 4c to 4f show timing diagrams of the control signals of the charge pump of Figure 4a;
- Figures 5a and 5b schematically show an embodiment of a negative charge pump according to the invention; and
- Figures 5c to 5f show timing diagrams of the control signals of the charge pump of Figure 5a.

 To individually polarize the substrate of the charge pump cells, the cell transistors are produced in a double box technology (triple-well in English). FIG. 2 represents a sectional view of an N-type transistor produced in this technology. This technology is well known to those skilled in the art. The transistor comprises, in the P-type substrate B3, a first P-type well B1 in which the drain region D and the source region of the transistor are located, and a second N-type well B2 containing the well B1. The transistor also includes a control gate G isolated from the well B1 by an oxide layer O.

 This technology will make it possible to polarize the wells B1 of the transistors of each cell differently. The wells and the substrate are polarized so that the P-N junctions between these three regions do not pass current. If the bias voltage of the well B1 is designated by VB1, the bias voltage of the well B2 by VB2 and the bias voltage of the substrate B3 by VB3, it is therefore necessary that VB1 <VB2 and VB3SVB2. For convenience, the substrate B3 common to all the cells will preferably be connected to ground, and we will take VB1 = VB2.

 With the use of this technology, each cell occupies a larger surface on silicon, however this loss of space is compensated by the fact that fewer cells are used to produce the desired voltage.

 To avoid any risk of latch-up, the well B1 of each transistor must be polarized so that the well-drain and well-source junctions are not directly polarized. However, the well B1 of each transistor cannot be directly connected to its drain or to its source because sometimes the drain voltage is higher than the source voltage, sometimes it is the reverse. It is therefore necessary to permanently polarize the well B1 at the lowest potential between that of the source and that of the drain of the transistor of the cell. This is the role of the polarization means described in FIG. 3.

 FIG. 3 describes an elementary cell of a positive charge pump according to the invention. This cell which corresponds to the cell of FIG. 1B is supplemented by means for biasing the well B1 of the transistor 6 of the cell. These means consist of an N-type transistor 8, the control gate and the drain of which are connected to the source and the drain of the transistor 6, respectively, and the source and of the well B1 of which are connected to the well B1 of the transistor 6. These means also include an N-type transistor 9, the control gate and the source of which are connected respectively to the drain and the source of the transistor 6, and the drain and of which the box B1 are connected to the box B1 of the transistor 6. These biasing means operate in the following way: when the input voltage IN of the cell is greater than the output voltage OUT, the transistor 9 is on, and the well B1 and the drain of the transistor 6 are then connected together. The transistor 8 is blocked. In the opposite case, when IN> OUT, the transistor 8 is on and the well B1 of the transistor 6 is connected to its source. For these means to function properly, however, the difference between the voltage difference between the drain and the source of transistor 6 must be greater than the threshold voltage Vt. This case only occurs when the charge pump is stopped.

 The addition of the transistors 8 and 9 does not cause a very significant loss of space on silicon because they are preferably made in the well B2 of the transistor 6.

 These polarization means thus make it possible to limit the risk of latch-up and to limit the voltage Vsb for each cell. Such a circuit therefore makes it possible to limit the substrate effect which greatly penalizes the gain of the last cells of the charge pump. By this circuit, the gain of the different cells of the charge pump is almost uniform while remaining as high as possible.

 This circuit also makes it possible to limit the risk of destruction of the transistors of the cells because the potential difference between the control gate and the box of the transistors is limited.

 FIGS. 4A to 4F describe a variant of the positive charge pump according to the invention. In this version, cells C1 to Cn are each controlled by two clock signals CK1 and CK2. These clock signals can alternately be either control signals A1 and A2 described in FIGS. 4C and 4D, or control signals B1 and B2 described in FIGS. 4E and 4F. These clock signals are applied to inputs 5a and 5b provided for this purpose.

 FIG. 4B describes an elementary cell of the charge pump of FIG. 4A. It takes up the structure of the cell of FIG. 3. The first pole of the capacitor 7 is no longer connected to the drain of the transistor 6 but is connected to the drain of an N-type transistor 11 whose source and well B1 are connected to the drain of transistor 6. The gate of transistor 11 is also connected to the source of transistor 6. The signal input 5 becomes input 5b.

Finally, the cell comprises an additional capacitor 10, a first pole of which is connected to the drain of transistor 6 and the second pole of which is connected to the input terminal 5a. The polarization means are identical to those of FIG. 3.

The control signals A1, A2, B1 and B2 are described respectively in FIGS. 4C to 4F. Assuming that the signals A1 and A2 are initially at o and that the signals B1 and B2 are initially at Vcc, the signals Al, A2, B1 and B2 appear in the following form:
- the rise at Vcc of signal A2 causes the descent of signal B1 to 0,
- the descent to 0 of the signal B1 causes the ascent to Vcc of the signal Al,
- the rise at Vcc of the signal Al causes the descent of the signal B2 to 0, this signal B2 rising to Vcc after a certain delay,
- the rise to Vcc of signal B2 causes the signal Al to descend to 0,
- the descent to 0 of signal Al causes the rise of signal B1 at Vcc, and
- the rise at Vcc of signal B1 causes the descent of signal A2 to 0, this signal A2 which, after a certain delay, will rise to Vcc and so on.

 The operation of such a cell is as follows: the positive charges are transferred from the input 3 to the output 4 on the falling edge of the signal CK2 (A2 or B2), the transistor 6 then being on. The input voltage IN increases by Vcc on the rising edge of the signal CK1 (Al or B1). In this second embodiment, the double box technology (triple-well) and the polarization means 8 and 9 perform the same function as in the charge pump of FIGS. 1 to 3. Thus, for each cell, the polarization of the box B1 of the transistors is different in order to optimize the voltage Vsb.

The invention also relates to a negative voltage generator circuit of the charge pump type, an embodiment of which is illustrated in FIGS. 5A to 5F. This circuit is produced from a substrate P;
The P type transistors used in this circuit include an N type box in the substrate. It is therefore not useful to realize this circuit in triple-well technology.

 The charge pump comprises a set of n elementary cells C'1 to C'n, the structure of which is described in FIG. 5B. These cells are mounted in series between a 1 'input and a 2' output.

 An elementary cell, illustrated in FIG. 5B, comprises an input 3 'to receive an input voltage IN', an output 4 'to deliver an output voltage OUT, and two inputs 5'a and 5'b to receive two signals d clock CK1 and CK2.

It also includes:
- a first 6 'P-type transistor whose source is connected to the 3' input and the drain to the 4 'output,
a second P type transistor 11 ′ whose drain and well are connected to the input 3 ′, whose source is connected to the gate of the transistor 6 ′ and whose gate is connected to the output 4 ′,
a first capacitor 7 ′, a first pole of which is connected to the control gate of the transistor 6 ′, and the second pole of which is connected to the input 5′b, and
- a second capacity 10 ', a first pole of which is connected to the input 3' and the second pole of which is connected to the input 5'a.

 The cell of the cell transistors and the substrate are reverse biased. Furthermore, the input 3 ′ of the first cell C ′ 1 is connected via a transistor T ′ to ground, the control gate of the transistor T ′ being connected to a supply terminal Vcc.

 In practice, the capacitors 7 ′ and 10 ′ are produced from P-type transistors, the first pole of these capacitors corresponding to the control gate of a transistor and the second pole corresponding to the source and to the drain connected to each other. of this transistor.

 To polarize the well of transistor 6 ', the elementary cell is completed by polarization means made up of transistors 8' and 9 '. The transistor 8 'is of type P and its control gate and its source are connected respectively to the drain and to the source of the pass transistor 6' while its drain and its well are connected to the well of the pass transistor 6 '. The transistor 9 'is also of the P type; its control gate and its drain are connected respectively to the source and to the drain of the passage transistor 6 'while its source and its well are connected to the well of the passage transistor 6'.

 The control signals A'1, A'2, B'1 and B'2 applied to the inputs 5'a and 5'b are shown in Figures 5C to 5F. These signals are the complementary signals to the signals of FIGS. 4C to 4F.

The operation of such a cell is as follows: the input voltage IN 'decreases by Vcc on the falling edge of the signal CK'1 (ie A'1 or B'1) and negative charges are transferred from input 3 'to output 4' on falling edge of the clock signal
CK'2 (ie A'2 or B'2). At any time, the well of transistor 6 'is biased at the highest potential between that of its source and that of its drain to limit the substrate effect.

Claims (4)

 1 - Positive voltage generator circuit of the charge pump type, produced from a type of substrate P, and supplying an output (2) with a positive voltage (VP) by pumping positive charges into n pumping cells (Cî, ..., Cn) connected in series, each cell comprising at least one capacity (7) and an N-type pass transistor (6),  characterized in that the circuit is made in a double-box technology comprising in a substrate, for each transistor, a first P-type box (B1) in which the drain zone (D) and the source zone (S ) of said transistor, a second well (B2) containing the first well (B1), the PN junctions between said wells and the substrate being reverse biased,  and in that each cell further comprises means for biasing (8,9) the first well (B1) of said flow transistor (6) to bias the first well (B1) at the lowest potential between that of the source and that of the drain of the passage transistor (6).  2 - Circuit according to claim 1 characterized in that said polarization means (8,9) in each cell include  - a first N-type transistor (8), the control gate and the drain of which are connected respectively to the source and the drain of the through transistor (6) and the source and the first well of which are connected to the first well of the transistor passage (6), and  - a second N-type transistor (9), the control gate and the source of which are respectively connected to the drain and the source of the through transistor (6) and the drain and the first well of which are connected to the first well of the transistor passage (6).  3 - Negative voltage generator circuit of the charge pump type, produced from a type of substrate P, and supplying an output (2 ') with a negative voltage (VN) by pumping negative charges into n pumping cells (Cl', ..., Cn ') connected in series, each cell comprising at least one capacity ( 7 ′) and a P-type pass transistor (6 ′), each P-type transistor in the cell comprising an N-type well in the P-type substrate,  characterized in that the circuit further comprises biasing means (8 ', 9') for biasing the well of the flow transistor (6 ') at the highest potential between that of the source and that of the drain of the flow transistor (6 ').  4 - Circuit according to claim 2 characterized in that the biasing means (8 ', 9') of the box of the through transistor (6 ') comprise  - a first P-type transistor (8 '), the control gate and the source of which are connected respectively to the drain and the source of the through transistor (6') and the drain and the box of which are connected to the box of the transistor passage (6 '), and  - a second P-type transistor (9 ') whose control gate and drain are connected respectively to the source and to the drain of the pass transistor (6') and whose source and box are connected to the box of the transistor passage (6 ').