EP1529310A2 - Structures d'interconnexion poreuses a faible constante dielectrique - Google Patents

Structures d'interconnexion poreuses a faible constante dielectrique

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Publication number
EP1529310A2
EP1529310A2 EP02797318A EP02797318A EP1529310A2 EP 1529310 A2 EP1529310 A2 EP 1529310A2 EP 02797318 A EP02797318 A EP 02797318A EP 02797318 A EP02797318 A EP 02797318A EP 1529310 A2 EP1529310 A2 EP 1529310A2
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EP
European Patent Office
Prior art keywords
porous dielectric
layer
etch stop
dielectric layer
porous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP02797318A
Other languages
German (de)
English (en)
Other versions
EP1529310A4 (fr
Inventor
Ann R. c/o IBM United Kingdom Limited FORNOF
Jeffrey C. Hedrick
Kang-Wook Lee
Kelly Malone
Christy S. Tyberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
Priority claimed from US10/290,682 external-priority patent/US6783862B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP1529310A2 publication Critical patent/EP1529310A2/fr
Publication of EP1529310A4 publication Critical patent/EP1529310A4/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/665—Porous materials
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers

Definitions

  • This invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and other high speed IC's.
  • the invention provides ultra low dielectric constant (low-k) interconnect structures having enhanced circuit speed, precise values of conductor resistance, and improved mechanical integrity.
  • the structures of this invention have improved toughness and adhesion along with improved control over the metal line resistance compared to conventional structures.
  • the present invention also provides many additional advantages, which shall become apparent as described below.
  • an electrical interconnect structure on a substrate comprises a first porous dielectric layer with surface region from which porogen has been removed; and an etch stop layer disposed upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed.
  • the structure may further comprise a second porous dielectric layer disposed upon the first porous dielectric layer.
  • At least one of the first porous dielectric layer and the second porous dielectric layer may be comprised of porous SiLKTM , GX-3pTM , or other porous low k dielectric materials where the porosity is formed from the decomposition of a sacrificial porogen, which may be a component of the material, as provided by the manufacturer.
  • a sacrificial porogen which may be a component of the material, as provided by the manufacturer.
  • Materials of this kind are described in Patent Cooperation Treaty International Patent Application WO 00/31183 entitled A composition containing a cross-linkable matrix precursor and a porogen, and a porous matrix prepared therefrom of Kenneth, J. Bruza et al. which is assigned to The Dow Chemical Company, the contents of which are incorporated herein in their entirety by reference.
  • the etch stop layer may be comprised of HOSPTM, HOSP BEStTM, EnsembleTM Etch Stop, EnsembleTM Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric.
  • Materials of this kind are described in United States Patent US 6,218,020 entitled Dielectric films from organohydridosiloxane resins with high organic content of Nigel P.
  • AlliedSignal Inc. and United States Patent US 6,177,199 entitled Dielectric films from organohydridosiloxane resins with low organic content of Nigel P.
  • AlliedSignal Inc. the contents of which are incorporated herein in their entirety by reference.
  • the structure may comprise a plurality of patterned metal conductors formed within a multi layer stack of porous dielectric layers on the substrate, the stack including at least the first porous dielectric layer and the second porous dielectric layer. At least one of the patterned metal conductors, located in the first porous dielectric layer, may be an electrical via. At least one of the patterned metal conductors, located in the second porous dielectric layer, may be a line connected to the via.
  • the structure may include a top hard mask or polish stop layer applied to surface regions of the second dielectric from which porogen has been removed.
  • the hard mask or polish stop layer may be comprised of HOSPTM, HOSP BEStTM, EnsembleTM Etch Stop, EnsembleTM Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric. Materials of this kind are described in United States Patent US 6,218,020 entitled Dielectric films from organohydridosiloxane resins with high organic content of Nigel P.
  • the invention is also directed to a method of forming an electrical interconnect structure on a substrate, comprising providing a first porous dielectric layer with surface region from which porogen has been removed; and forming an etch stop layer upon the first porous dielectric layer so that the etch stop layer extends to partially fill pores in the surface region of the first porous dielectric layer from which the porogen has been removed.
  • the method may further comprise removing the porogen from the first surface region.
  • the porogen may be removed by heating, and in particular, by baking on a hot surface.
  • the method may further comprise forming a second porous dielectric layer upon the first porous dielectric layer.
  • At least one of the first porous dielectric layer and the second porous dielect ⁇ c layer may be comprised of porous SiLKTM , GX-3pTM , or other porous low k dielectric materials where the porosity is formed from the decomposition of a sacrificial porogen.
  • the method may further comprise forming a metal via in the first porous dielectric layer, and forming a metal line in the second porous dielectric layer.
  • the method may further comprise forming a plurality of patterned metal conductors within a multi layer stack of porous dielectric layers on the substrate, the stack including at least the first porous dielectric layer and the second porous dielectric layer. Additional dielectric layers may be added; and the structure may be completed by adding conductors. A top hard mask or polish stop layer may be applied to surface regions of the second dielectric from which porogen has been removed.
  • the method may further comprise curing the dielectric layers to render the dielectric layer porous.
  • the dielectric layers in the stack are preferably cured in a single step after sequential application in a single tool.
  • the dielectric application tool may be a spin coating tool containing high temperature hot plate baking chambers, and the curing step may be a furnace curing step conducted at a temperature of from about 300°C to about 500°C for about 15 minutes to about 3 hours.
  • the present invention is also directed to a metal wiring plus porous low dielectric constant (low-k) interconnect structure of the dual damascene type with a spin-on buried RIE stop, having improved adhesion.
  • This aspect of the inventive structure is comprised of: A) a multilayer structure of all spin-on dielectric materials which are applied sequentially in a single tool, and then cured in a single furnace cure step, and B) a plurality of patterned metal conductors within the dielectric multilayer structure.
  • the improved adhesion is obtained by partially burning out the porogen near the surface of the via level Porous SiLK prior to applying the etch stop.
  • the structure of the invention has improved adhesion over conventional spin-on buried etch stop structures as a result of the increased surface area of contact between the porous SiLK and etch stop, due to partial burnout of porogen at the surface.
  • the structure of this invention is unique in that it has a layer of Porous SiLK, prior to porogen burnout, with a partial burnout of sacrificial porogens near the surface. This results in the top layer of pores being partially filled with the spin-on buried etch stop, leading to increased adhesion between the dielectric and the etch stop.
  • the structures of this invention are unique in that they have an ultra-thin non-porous tough dielectric layer between the porous dielectric and the buried etch stop layer.
  • This tough, thin non- porous dielectric layer serves several purposes: it improves toughness, adhesion and reliability of the interconnect structure.
  • the non-porous layer is a version of the porous dielectric with a fracture toughness of greater than 0.3 MPa-m 1/2 which will covalently bond with the porous dielectric to create one network, while increasing the surface area of contact with the etch stop layer by eliminating pores at the surface.
  • Increased toughness is achieved by incorporating a tough material near the interface in the area of increased stress in the structure.
  • This type of tough material does not have the necessary properties to support the very small pores required by the porous dielectric and therefore generally cannot be used as the matrix for the porous dielectric.
  • smoother lines can be achieved by eliminating pores at the bottom of the etch stop.
  • the present invention is directed to a metal wiring plus porous low dielectric constant (low-k) interconnect structure having improved toughness and adhesion, of the dual damascene type with a spin-on buried RIE stop.
  • the inventive structure is comprised of : a) a multilayer of all spin-on dielectric materials which are applied sequentially in a single tool, and then cured in a single furnace cure step, and b) a plurality of patterned metal conductors within the dielectric multilayer.
  • the improved toughness and adhesion is obtained by incorporating a thin, non-porous dielectric layer, which has a fracture toughness greater than 0.3 MPa-m 1/2 , between the porous dielectric and the etch stop, between the etch stop and the porous dielectric, or both.
  • a structure and in particular an electrical interconnect structure, comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer.
  • the thin, non-porous dielectric layer may have a thickness of substantially 25 to 150 Angstroms.
  • the thin, non-porous dielectric layer has a composition with reactive functionalities identical to those of the porous dielectric layers and in particular a composition, which forms a covalent bond with the composition of the porous dielectric layers.
  • the thin, non-porous dielectric layer may be comprised of a material selected from the group consisting of SiLK TM, GX-3TM , or other low k dielectric materials that exhibit fracture toughness values greater than 0.3 MPa-m ⁇ preferably greater than 0.35 MPa-rn 72 , and will covalently bond to the porous dielectric layer.
  • Materials of this kind are described in Patent Cooperation Treaty International Patent Application WO 00/40637 entitled Low Dielectric Constant Polymers Having Good Adhesion and Toughness and Articles Made With Such Polymers of Edward O. Shaffer II et al. which is assigned to The Dow Chemical Company.
  • At least one of the porous dielectric layers is comprised of a material selected from the group consisting of porous SiLK TM, GX-3pTM, or other porous low-k dielectric layers. Materials of this kind are described in Patent Cooperation Treaty International Patent Application WO 00/31183 entitled A composition containing a cross-linkable matrix precursor and a porogen, and a porous matrix prepared therefrom of Kenneth, J. Bruza et al. which is assigned to The Dow Chemical Company, the contents of which are incorporated herein in their entirety by reference. It may have a thickness of substantially 600-5000 Angstroms. In general, at least one of the porous dielectric layers has the same chemical composition as another of the porous dielectric layers. At least one of the porous dielectric layers may be of substantially the same thickness as another of the porous dielectric layers and have a thickness of substantially 600-5000 Angstroms.
  • the etch stop layer may be comprised of HOSPTM, HOSP BEStTM, EnsembleTM Etch Stop, EnsembleTM Hard Mask, organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric.
  • Materials of this kind are described in United States Patent US 6,218,020 entitled Dielectric films from organohydridosiloxane resins with high organic content of Nigel P.
  • AlliedSignal Inc. and United States Patent US 6,177,199 entitled Dielectric films from organohydridosiloxane resins with low organic content of Nigel P.
  • AlliedSignal Inc. the contents of which are incorporated herein in their entirety by reference. It may have a thickness of substantially 200 - 600 Angstroms.
  • the structure may further comprise a plurality of patterned metal conductors formed within a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers. At least one of the patterned metal conductors may be an electrical via or a line connected to the via.
  • the invention is also directed to a method for forming an electrical interconnect structure on a substrate, the structure having a plurality of porous dielectric layers disposed on the substrate and an etch stop layer between a first of the dielectric layers and a second of the dielectric layers.
  • the method comprises forming at least one thin, non-porous dielectric layer between at least one of the porous dielectric layers and the etch stop layer.
  • the method further comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. At least one of the patterned metal conductors may be formed as an electrical via. At least one of the patterned metal conductors may be a line connected to the via.
  • the multilayer dielectric stack is applied to the substrate by spin coating.
  • the method may further comprise baking the individual layers of the multilayer dielectric stack on a hot plate.
  • the method may further comprise curing the multilayer dielectric stack. The curing of the multilayer dielectric stack may be accomplished using a furnace in a single step.
  • the method also includes applying a multilayer dielectric stack to the substrate and baking the multilayer dielectric stack, so that the applying and baking are accomplished in a single spin-coat tool. Additional dielectric layers may be added, and dual damascene conductors may be formed in the additional layers.
  • Figure 1A and Figure 1B are schematic drawings of a prior art porous dielectric with a buried etch stop before RIE and metallization.
  • Figures 2A through 2D are schematic drawings of the inventive structures with partial burnout of porogen near the surface of the via level before RIE and metallization.
  • Figure 3 is a schematic drawing of the inventive structures after RIE and metallization.
  • Figure 4 is a process flow chart of a method for make the structure of Figure 2.
  • Figure 5 is a schematic drawing of a porous dielectric with a buried etch stop in accordance with the prior art, before RIE and metallization.
  • Figure 6A is a schematic drawing of a structure in accordance with the invention with a thin layer below the etch stop before RIE and metallization.
  • Figure 6B is a schematic drawing of a structure in accordance with the invention with a thin layer above the etch stop before RIE and metallization.
  • Figure 6C is a schematic drawing of a structure in accordance with the invention with a thin layer both above and below the etch stop before RIE and metallization.
  • Figure 7 is a schematic drawing of a structure in accordance with the invention, after RIE and metallization.
  • a silicon substrate 1 has thereon a first porous low k dielectric layer 5, an etch stop layer 7, and a second porous low k dielectric layer 9.
  • Furnace curing may produce a weak interface between porous low k dielectric layer 5, an etch stop layer 7. This is because during this type of processing of porous SiLKTM (a Dow Company proprietary organic ultra low-k interlayer dielectric resin) with a spin-on buried etch stop layer, the porogen is not burnt out of the porous SiLKTM until both the line and via levels of porous SiLKTM along with the buried etch stop have been applied.
  • porous SiLKTM a Dow Company proprietary organic ultra low-k interlayer dielectric resin
  • improved adhesion is obtained by partially burning out the porogen near the surface of the via level Porous SiLKTM prior to applying the etch stop ( Figure 2B).
  • the porogen near the surface can be partially removed. This results in a higher surface area of contact between the via level Porous SiLKTM and etch stop resulting in improved adhesion.
  • substrate 1 may contain electronic devices such as, for example, transistors and an array of conductor elements.
  • An interconnect structure 3, in accordance with the invention is formed on substrate 1.
  • Structure 3 is comprised of a first porous SiLKTM dielectric layer 5, having a thickness of 600 - 5000 Angstroms which may have a highly aromatic structure, that is thermally stable to approximately 425°C, with a glass transition temperature above 450°C, and a low dielectric constant of 2.2. The thickness may be selected within this broad range in accordance with the technology being implemented.
  • This material has good adhesion to the non-porous SiLKTM and thermal stability to a temperature of greater than 425°C, and a low dielectric constant of 3.2 or less.
  • a top hard mask or polish stop layer 11 may be applied on surface regions of the second porous dielectric layer 9, from which porogen has been removed in the manner set forth herein.
  • Patterned metal lines 13 and vias 14, formed by a dual damascene process, are formed within the dielectric multilayer structure described above.
  • low-k spin coated materials may be used for the dielectric layers 5 and 9 and for the etch stop layer 7.
  • examples of other materials that could be used for layers 5 and 9 are GX-3pTM, or other porous low k dielectric materials where the porosity is formed as a result of the decomposition of a sacrificial porogen.
  • examples of other materials that could be used for layer 7 are HOSP BEStTM, EnsembleTM Etch Stop, EnsembleTM Hard Mask, .organo silsesquioxanes, hydrido silsesquioxanes, hydrido-organo silsesquioxanes, siloxanes, or other spin-on material with etch selectivity to the porous dielectric.
  • the stack of dielectric layers is formed
  • the interconnect structure 3 in accordance with the invention may be applied to the substrate 1 or wafer by spin on techniques.
  • the first layer 5 in the structure 3 is preferably a porous low k dielectric with a desired thickness of 600-5000 Angstroms. This low k dielectric is applied by a spin-on technique with a spin speed of 1000-4000 rpm.
  • the substrate 1 is hot plate baked to remove the solvent of the low k dielectric at 100-350°C, for 30-120 seconds.
  • the substrate 1 is then placed on an oxygen-controlled hot plate and cured at 400°C for 5-10 minutes, or 400°C for 2 minutes, followed by 430°C for 2 minutes. These times and temperatures are sufficient to render the film of the first layer 5 insoluble, and to remove porogen at the surface of the film.
  • a buried etch stop layer 7, with a desired thickness of 200-300 Angstroms, is applied by a spin-on technique with a spin speed of 1000-4000 rpm.
  • the wafer is then placed on a hot plate and baked at 100-300°C for 30-120 seconds to remove the solvent. It is then placed on a 300 - 400°C oxygen controlled hot plate for 1-2 minutes. This time promotes sufficient crosslinking to render the film insoluble.
  • the top dielectric layer 9 is applied in a similar fashion. Layer 9 is the same composition as layer 5 with a slightly greater thickness.
  • the desired thickness of the top low k dielectric layer 9 is 600-5000 Angstroms. This layer is spun at 1000-4000 rpm, and the wafer is then hot plate baked at 100-350°C, for 30-120 seconds, to remove the solvent.
  • the stack of dielectric layers is cured in a single cure step
  • the wafer is placed in a furnace in an atmosphere of pure N 2 (with very low O 2 and H 2 O concentrations), and cured at 350- 450°C for 15 minutes to 3 hours to crosslink the stack and burn out the sacrificial porogen.
  • the sacrificial porogen thermally degrades and then diffuses out of the dielectric stack through the free volume of the dielectric layers and etch stop layer, leaving the porous dielectric layers in the stack.
  • BEOL back end of line
  • Example 1 A Porous SiLKTM/HOSPTM/Porous SiLKTM Structure is Produced
  • the stack of dielectric layers is formed as in Figure 1.
  • a 200mm diameter silicon wafer substrate is treated with adhesion promoter by applying a solution of AP 4000 to the wafer followed by spinning at 3000 rpm for 30 seconds.
  • the wafer is then placed on a hot plate at 185°C for 90 seconds for a first hot plate bake.
  • the first layer of low k dielectric (porous SiLK TM) is applied (layer 5, Figure 1 ).
  • the SiLK TM solution is placed on the wafer and the wafer is spun at 3000 rpm for 30 seconds. After spinning, the wafer is placed on a 150°C hot plate for 2 minute to partially dry the solvent, at 26 (second hot plate bake). It is then transferred to a 400°C hot plate for 5 minutes. As an alternative, at 26, the wafer is placed on a 150°C hot plate for 2 minute to partially dry the solvent, transferred to a 400°C hot plate for 2 minutes, and then transferred to a 430°C hot plate for 2 minutes.
  • the time and temperature schedule should be sufficient to render the film insoluble and burnout sacrificial porogen near the surface.
  • a solution of HOSPTM diluted to achieve a film thickness of 250A° at a spin speed of 3000 rpm, is applied to the wafer and spun at 3000 rpm for 30 seconds, to produce etch stop layer 7 ( Figure 1 ).
  • the wafer is placed on a hot plate at 150°C for 2 minute to partially dry the solvent. It is then moved to a 400°C hot plate for 2 minutes to partially crosslink the film. This time and temperature is sufficient to render the film insoluble.
  • a second layer of Porous SiLK is applied in a manner similar to the first layer to produce layer 9 (Fig. 1 ). Porous SiLK is applied to the wafer and the wafer is spun at 3000 rpm for 30 seconds.
  • the wafer is placed on a 150°C hot plate for 2 minute to partially dry the solvent.
  • the wafer is placed in an oxygen controlled oven and cured at 430°C for 80 minutes to cure the SiLK and etch stop layers, promote crosslinking between the layers, and thermally degrade and burn out the porogen.
  • the cured wafer containing the layers described above was placed in a PE CVD reactor and a 350 Angstrom layer of Silicon Nitride was deposited at 350°C, and then a 1500 Angstrom layer of SiO 2 was deposited at 350°C. This completes the formation of the dielectric multilayer of the Example 1.
  • Lithography and etching processes are then performed as described in, for example, United States Patent No. 6.383,920.
  • the dual damascene structure is then completed using standard process methods known in the industry (the etched trench and via opening are filled with a liner and then with Cu, and the Cu is planarized by CMP).
  • the silicon dioxide layer deposited in step C is removed, leaving the structure shown in Figure 3.
  • all of the dielectric layers (5, 7, and 9) shown in Figure 3 have been cured in a single furnace cure step after sequential application of the three layers in a single spin/apply tool.
  • a structure on which, for example, an integrated circuit may be fabricated includes a substrate 101 , a first porous dielectric layer 105, and a second porous dielectric layer 113.
  • an etch stop layer 109 may be disposed between dielectric layers 105 and 113.
  • Substrate 101 is generally comprised of silicon, and may include a dielectric, a metal region, an adhesion promoter, or any combination thereof.
  • Substrate 101 may be a semiconductor wafer of a different composition
  • porous dielectric layers 105 and 113 may be comprised of a material sold under the trademark porous SiLK M) (a Dow Chemical Company proprietary organic ultra low-k interlayer dielectric resin).
  • Other possible materials include GX-3pTM , or other porous low k dielectric materials.
  • a non- porous dielectric layer with a fracture toughness greater than 0.3 MPa-m 1 2 107 is provided between porous dielectric layer 105 and etch stop layer 109.
  • Dielectric layer 107 may have a thickness of approximately 25-150 Angstroms.
  • Dielectric layer 107 has increased fracture toughness compared to porous SiLKTM due to a decreased network density, as described in above mentioned International Patent Application WO 00/40637. This structure has the same reactive functionalities as a porous SiLKTM layer and can crosslink with a porous SiLKTM layer.
  • Layer 107 preferably has a highly aromatic structure, which is thermally stable to approximately 425°C with a glass transition temperature above 430°C, and a low dielectric constant of approximately 2.65.
  • the structure of Figure 6B is similar to that of Figure 6A, but does not include layer 107. Instead, the structure of Figure 6B includes a layer 111 disposed between etch stop layer 109 and porous dielectric layer 113. Layer 111 may be, in all respects except location, similar to layer 107.
  • the structure shown therein includes both a layer 107 and a layer 111 , having the characteristics described above.
  • FIG. 7 schematically illustrates another specific embodiment of the invention.
  • a substrate 101 may contain transistors and an array of conductor elements.
  • An interconnect structure 103 in accordance with the invention, is disposed on the substrate 101.
  • Structure 103 is comprised of a first porous SiLKTM dielectric layer 105, having a thickness of 600-5000 Angstroms and having a highly aromatic structure which is thermally stable to approximately 425°C, with a glass transition temperature above approximately 450°C, and a low dielectric constant of approximately 2.2.
  • a thin non porous SiLK TM layer 107 having a fracture toughness greater than 0.30 MPa-m 1 2 and having a thickness of approximately 25- 150 Angstroms, is disposed on the first porous SiLK layer 105.
  • layer 107 has increased fracture toughness compared to porous SiLK due to a decreased network density.
  • This structure has the same reactive functionalities as the porous SiLK layer 105 and can crosslink with porous SiLK layer 105.
  • Layer 107 is a highly aromatic structure, which is thermally stable to approximately 425°C with a glass transition temperature above approximately 430°C, and a low dielectric constant of approximately 2.65.
  • a HOSP BEStTM (a spin-on hybrid organic-inorganic low-k dielectric) etch stop layer 109 of thickness 200 - 600 Angstroms (more preferably 200-300 Angstroms), and having an atomic composition that gives etch selectivity of at least 10:1 to the porous dielectric is disposed on the thin SiLKTM layer 107.
  • the material of layer 109 has good adhesion to SiLKTM, thermal stability to approximately 450°C, and a low dielectric constant of approximately 2.7.
  • a thin non-porous SiLK layer 111 having a fracture toughness greater than 0.30 MPa-m 1/2 and having a thickness of approximately 25- 150 Angstrom, is disposed on the etch stop layer 109.
  • Layer 111 has increased fracture toughness compared to porous SiLKTM due to a decreased network density.
  • Layer 111 has the same reactive functionalities as a porous SiLKTM layer and can crosslink with a porous SiLKTM layer.
  • Layer 111 has a highly aromatic structure, which is thermally stable to approximately 425°C with a glass transition temperature above approximately 430°C, and a low dielectric constant of approximately 2.65.
  • dielectric layers 105 and 113 may be used for dielectric layers 105 and 113, for etch stop layer 109, and for the thin toughening layers 107 and 111.
  • the inventive interconnect structure 103 is applied to the substrate 101 by spin on techniques.
  • the first layer 105 in the structure is preferably a porous low k dielectric with a desired thickness of 600- 5000A°.
  • This low k dielectric is applied by a spin-on technique with a spin speed of 1000-4000 rpm. After spinning the low k dielectric is hot plate baked to dry the solvent and render the film insoluble at 200-400°C for 1-2 minutes. This time and temperature is sufficient to render the film insoluble without eliminating the porogen.
  • a thin layer of a dielectric having a fracture toughness greater than 0.30 MPa-m 1/2 107 capable of crosslinking with the bottom porous dielectric layer, and having a thickness of approximately 25-150 Angstroms is applied by spin coating.
  • the dielectric After spinning the dielectric is hot plate baked to dry the solvent and render the film insoluble at 200-400°C for 1-2 minutes.
  • the buried RIE etch stop layer 109 After cooling, the buried RIE etch stop layer 109, with a desired thickness of approximately 200-600 Angstroms, is applied by a spin-on technique with a spin speed of 1000-4000 rpm.
  • the etch stop layer is hot plate baked to dry the solvent and render the film insoluble at 200-400°C for 1-2 minutes. This time promotes sufficient crosslinking to render the film insoluble.
  • a second thin layer of a dielectric having a fracture toughness greater than 0.30 MPa-m 1/2 111 capable of crosslinking with the top porous dielectric layer, and having a thickness of 25-150 Angstroms is applied by spin coating.
  • the low k dielectric After spinning the low k dielectric is hot plate baked to dry the solvent and render the film insoluble at 200-400°C for 1 -2 minutes. After cooling, the top dielectric layer 113 is applied in a similar fashion. Layer 113 may be of the same composition as layer 105, but with a slightly higher thickness. The desired thickness of the top low k dielectric layer 113 is approximately 600 - 5000 Angstroms. This layer is spun at 1000 - 4000 rpm, then hot plate baked at approximately 100-400°C for approximately 30-120 seconds to partially dry the solvent.
  • the stack of dielectric layers is cured in a single cure step
  • the wafer is placed in a furnace in an atmosphere of pure N 2 (with very low O 2 and H 2 O concentrations) and cured at approximately 300-450°C for approximately 15 minutes to 3 hours to crosslink the stack and burn out the sacrificial porogen.
  • the first layer of low k dielectric porous SiLKTM is applied to the substrate by spin coating (layer 105, Figure 7). After spinning, the wafer is placed on a 250°C hot plate for 2 minute to partially dry the solvent. It is then transferred to a 310°C hot plate for 2 minutes and a 400°C hot plate for 2 minutes. This time and temperature are sufficient to render the film insoluble.
  • SiLKTM such as, for example, the composition specified in International Patent Application WO 00/40637 on page 17, Table II
  • resin I diluted to achieve a film thickness of about 100A° at a spin speed of 3000 rpm is applied to the wafer and spun at 3000 rpm for 30 seconds, to produce layer 107 (Fig. 7).
  • the wafer is placed on a hot plate at 310°C for 1 minute to dry the solvent. It is then moved to a 400°C hot plate for 2 minutes to partially crosslink the film. This time and temperature are sufficient to render the film insoluble.
  • the second layer of porous SiLKTM is applied in a manner similar to that for the first layer to produce layer 113 (Fig. 7). Porous SiLKTM is applied to the wafer and the wafer is spun at 3000 rpm for 30 seconds. The wafer is placed on a 250°C hot plate for 2 minute to partially dry the solvent.
  • the wafer is placed in an oxygen controlled oven and cured at 430°C for 80 minutes to cure the SiLK and etch stop layers, to promote crosslinking between the layers, and to thermally degrade and burn out the porogen.
  • the cured wafer containing the layers described above was placed in a PE CVD reactor and a 350 Angstrom layer of silicon nitride 115 was deposited at 350°C, and then a 1500 Angstrom layer of SiO 2 was deposited at 350°C. This completes the formation of the dielectric multilayer of Example 2.
  • Lithography and etching processes are then performed as described in the above referenced United States Patent No. 6, 383, 920.
  • the dual damascene structure is then completed using standard process methods known in the industry (the etched trench and via opening are filled with a liner and then with copper, and the copper is planarized by CMP).
  • silicon dioxide layer deposited in step C is removed, leaving the structure shown in Fig. 7. It should be noted that all the dielectric layers (105, 107, 109, 111 and 113) shown in Fig. 7 have been cured in a single furnace cure step after sequential application of the 5 layers in a single spin/apply tool.
  • the structure of the invention has improved adhesion over conventional buried etch stop structures because the non-porous layer will increase the surface area of contact with the etch stop layer by eliminating pores at the surface, and form covalent bonds with the porous dielectric to create one network.
  • Increased toughness is achieved by incorporating a tough material near the interface in the area of increased stress in the dielectric stack.
  • This type of tough material may not have the necessary properties to support very small pores required by the porous dielectric and therefore cannot be used as the matrix for the porous dielectric.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne une structure d'interconnexion électrique sur un substrat, qui comprend une première couche diélectrique poreuse à zone de surface dans laquelle un porogène a été épuisé; et une couche d'arrêt d'attaque placée sur cette première couche de manière à s'étendre pour combler partiellement les pores de la zone de surface de ladite première couche débarrassée du porogène, ce qui permet d'améliorer l'adhésion durant le traitement ultérieur. L'invention concerne une autre structure, qui comprend: un substrat; plusieurs couches diélectriques poreuses sur le substrat; une couche d'arrêt d'attaque entre une première couche diélectrique et une seconde couche diélectrique; et au moins une couche diélectrique non poreuse, mince, résistante, entre au moins une des couches diélectriques et la couche d'arrêt d'attaque. L'invention concerne également des procédés relatifs à la formation de ces structures.
EP02797318A 2001-12-13 2002-12-13 Structures d'interconnexion poreuses a faible constante dielectrique Withdrawn EP1529310A4 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US33973401P 2001-12-13 2001-12-13
US339734P 2001-12-13
US10/290,682 US6783862B2 (en) 2001-12-13 2002-11-08 Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures
US10/290,616 US6933586B2 (en) 2001-12-13 2002-11-08 Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens
US290616 2002-11-08
US290682 2002-11-08
PCT/US2002/040020 WO2003054928A2 (fr) 2001-12-13 2002-12-13 Structures d'interconnexion poreuses a faible constante dielectrique

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US7071539B2 (en) * 2003-07-28 2006-07-04 International Business Machines Corporation Chemical planarization performance for copper/low-k interconnect structures
US7365009B2 (en) 2006-01-04 2008-04-29 United Microelectronics Corp. Structure of metal interconnect and fabrication method thereof
US8486843B2 (en) 2008-09-04 2013-07-16 The Board Of Trustrees Of The University Of Illinois Method of forming nanoscale three-dimensional patterns in a porous material
US9054110B2 (en) 2011-08-05 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Low-K dielectric layer and porogen

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US6071809A (en) * 1998-09-25 2000-06-06 Rockwell Semiconductor Systems, Inc. Methods for forming high-performing dual-damascene interconnect structures
US6171945B1 (en) * 1998-10-22 2001-01-09 Applied Materials, Inc. CVD nanoporous silica low dielectric constant films
US6465365B1 (en) * 2000-04-07 2002-10-15 Koninklijke Philips Electronics N.V. Method of improving adhesion of cap oxide to nanoporous silica for integrated circuit fabrication
US6472306B1 (en) * 2000-09-05 2002-10-29 Industrial Technology Research Institute Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer
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WO2003054928A3 (fr) 2005-02-24
JP4437922B2 (ja) 2010-03-24
AU2002361679A8 (en) 2003-07-09
EP1529310A4 (fr) 2009-06-10
IL162436A0 (en) 2005-11-20
JP2005519455A (ja) 2005-06-30
AU2002361679A1 (en) 2003-07-09

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