EP1529310A4 - Structures d'interconnexion poreuses a faible constante dielectrique - Google Patents
Structures d'interconnexion poreuses a faible constante dielectriqueInfo
- Publication number
- EP1529310A4 EP1529310A4 EP02797318A EP02797318A EP1529310A4 EP 1529310 A4 EP1529310 A4 EP 1529310A4 EP 02797318 A EP02797318 A EP 02797318A EP 02797318 A EP02797318 A EP 02797318A EP 1529310 A4 EP1529310 A4 EP 1529310A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- interconnect structures
- porous low
- dielectric interconnect
- dielectric
- porous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
- H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33973401P | 2001-12-13 | 2001-12-13 | |
US339734P | 2001-12-13 | ||
US10/290,616 US6933586B2 (en) | 2001-12-13 | 2002-11-08 | Porous low-k dielectric interconnects with improved adhesion produced by partial burnout of surface porogens |
US290616 | 2002-11-08 | ||
US10/290,682 US6783862B2 (en) | 2001-12-13 | 2002-11-08 | Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures |
US290682 | 2002-11-08 | ||
PCT/US2002/040020 WO2003054928A2 (fr) | 2001-12-13 | 2002-12-13 | Structures d'interconnexion poreuses a faible constante dielectrique |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1529310A2 EP1529310A2 (fr) | 2005-05-11 |
EP1529310A4 true EP1529310A4 (fr) | 2009-06-10 |
Family
ID=27403994
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02797318A Withdrawn EP1529310A4 (fr) | 2001-12-13 | 2002-12-13 | Structures d'interconnexion poreuses a faible constante dielectrique |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1529310A4 (fr) |
JP (1) | JP4437922B2 (fr) |
AU (1) | AU2002361679A1 (fr) |
IL (1) | IL162436A0 (fr) |
WO (1) | WO2003054928A2 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7071539B2 (en) * | 2003-07-28 | 2006-07-04 | International Business Machines Corporation | Chemical planarization performance for copper/low-k interconnect structures |
US7365009B2 (en) | 2006-01-04 | 2008-04-29 | United Microelectronics Corp. | Structure of metal interconnect and fabrication method thereof |
WO2010027962A2 (fr) | 2008-09-04 | 2010-03-11 | The Board Of Trustees Of The University Of Illinois | Procédé d'obtention d'un nanomotif tridimensionnel dans un semi-conducteur poreux |
US9054110B2 (en) | 2011-08-05 | 2015-06-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Low-K dielectric layer and porogen |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0881678A2 (fr) * | 1997-05-28 | 1998-12-02 | Texas Instruments Incorporated | Améliorations dans ou relatives à des structures diélectriques poreuses |
WO2000024050A1 (fr) * | 1998-10-22 | 2000-04-27 | Applied Materials, Inc. | Depot chimique en phase vapeur de films a constante dielectrique faible de silice nanoporeuse |
WO2001078127A2 (fr) * | 2000-04-07 | 2001-10-18 | Philips Semiconductors, Inc. | Procede pour ameliorer l'adherence d'une couche de recouvrement sur une couche de matiere poreuse deposee sur une plaquette |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6071809A (en) * | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
US6472306B1 (en) * | 2000-09-05 | 2002-10-29 | Industrial Technology Research Institute | Method of forming a dual damascene opening using CVD Low-K material and spin-on-polymer |
US6383920B1 (en) * | 2001-01-10 | 2002-05-07 | International Business Machines Corporation | Process of enclosing via for improved reliability in dual damascene interconnects |
-
2002
- 2002-12-13 EP EP02797318A patent/EP1529310A4/fr not_active Withdrawn
- 2002-12-13 WO PCT/US2002/040020 patent/WO2003054928A2/fr active Application Filing
- 2002-12-13 JP JP2003555557A patent/JP4437922B2/ja not_active Expired - Lifetime
- 2002-12-13 AU AU2002361679A patent/AU2002361679A1/en not_active Abandoned
- 2002-12-13 IL IL16243602A patent/IL162436A0/xx unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0881678A2 (fr) * | 1997-05-28 | 1998-12-02 | Texas Instruments Incorporated | Améliorations dans ou relatives à des structures diélectriques poreuses |
WO2000024050A1 (fr) * | 1998-10-22 | 2000-04-27 | Applied Materials, Inc. | Depot chimique en phase vapeur de films a constante dielectrique faible de silice nanoporeuse |
WO2001078127A2 (fr) * | 2000-04-07 | 2001-10-18 | Philips Semiconductors, Inc. | Procede pour ameliorer l'adherence d'une couche de recouvrement sur une couche de matiere poreuse deposee sur une plaquette |
Also Published As
Publication number | Publication date |
---|---|
JP2005519455A (ja) | 2005-06-30 |
AU2002361679A1 (en) | 2003-07-09 |
JP4437922B2 (ja) | 2010-03-24 |
WO2003054928A2 (fr) | 2003-07-03 |
IL162436A0 (en) | 2005-11-20 |
EP1529310A2 (fr) | 2005-05-11 |
AU2002361679A8 (en) | 2003-07-09 |
WO2003054928A3 (fr) | 2005-02-24 |
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Legal Events
Date | Code | Title | Description |
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PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
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17P | Request for examination filed |
Effective date: 20040528 |
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Kind code of ref document: A2 Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LI LU MC NL PT SE SI SK TR |
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A4 | Supplementary search report drawn up and despatched |
Effective date: 20090511 |
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RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01L 23/532 20060101ALI20090504BHEP Ipc: H01L 23/48 20060101AFI20050303BHEP Ipc: H01L 21/768 20060101ALI20090504BHEP |
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17Q | First examination report despatched |
Effective date: 20090901 |
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STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
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18D | Application deemed to be withdrawn |
Effective date: 20100112 |